Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure

Abstract

Encryption is an important step for secure data transmission, and a true random number generator (TRNG) is a key building block in many encryption algorithms. Static random-access memory (SRAM) chips can be easily available sources of true random numbers, benefiting from noisy SRAM cells whose start-up values flip between different power-on cycles. Embarking from this phenomenon, a novel performance (i.e., randomness and throughput) improvement method of SRAM-based TRNG is proposed, and its implementation can be divided into two phases: irradiation exposure and hardware postprocessing. As the randomness of original SRAM power-on values is fairly low, ionization irradiation is utilized to enhance its randomness, and the min-entropy can increase from about 0.03 to above 0.7 in the total ionizing irradiation (TID) experiments. Additionally, while the data remanence effect hampers obtaining random bitstreams with high speed, the ionization irradiation can also weaken this impact and improve the throughput of TRNG. In the hardware postprocessing stage, Secure Hash Algorithm 256 (SHA-256) is implemented on a Field Programmable Gate Array (FPGA) with clock frequency of 200 MHz. It can generate National Institute of Standards and Technology (NIST) SP 800-22 compatible true random bitstreams with throughput of 178 Mbps utilizing SRAM chip with 1 Mbit memory capacity. Furthermore, according to different application scenarios, the throughput can be widely scalable by adjusting clock frequency and SRAM memory capacity, which makes the novel TRNG design applicable for various Internet of Things (IOT) devices.

1. Introduction

To keep the communication between Internet of Things (IOT) devices secure, the data often require encryption before being transmitted [1], and true random number generators (TRNGs) are indispensable primary components in many encryption algorithms [2,3]. TRNGs usually extract random numbers from the outcome of non-deterministic physical processes, such as thermal noise of resistors [4], random jitter of clock signals [5], random telegraph noise (RTN) [6] and metastable oscillation of latch circuits [7]. Various TRNGs proposed in the literature can be further categorized into analog and digital ones according to the types of circuits. The analog TRNGs generally amplify thermal noise directly to a measurable level and then utilize a comparator to quantize it [8]. However, these analog schemes require elaborative calibrations to remove bias in generated random bits. Extensive analog designs also bring out difficulties in system integration [8]. Digital TRNGs have advantages over analog ones in terms of integration and robustness to environmental variations [8]. Researchers have proposed different digital TRNGs based on oscillator jitter [9], metastability [10] and other device noise. It is easy to design and verify ring oscillator jitter based TRNGs on FPGA, but their randomness is relatively poor [11]. Metastability-based solutions possess high throughput and power efficiency but often need run-time controlling logic to remove mismatches in devices [10].

There also exists one common drawback of these TRNG designs in that they cannot reuse standard integrated circuit components and are usually used as single-purpose circuits, which increases the cost of production and decreases usage flexibility [12]. Especially with advancement of ubiquitous IOT applications (e.g., smart home, wireless sensor networks, and even smart city), the secure data transmission become more and more of a concern [13]. However, these IOT devices are usually source-constrained and lack dedicated hardware security components such as TRNGs, which leads to poorly encrypted communication, or often no encryption at all. Thus, it will be attractive to reuse existing standard components as primary security components, and static random-access memory (SRAM) is a potential option. It has been reported that memories will consume over 70% of active area, most being SRAM [13]. SRAM is available in many digital integrated circuits and system-on-chips [14], and thus there is no need for additional hardware. It is easy and low-cost to integrate commercial SRAM chips into IOT devices and reuse them as TRNGs [15,16,17].

The source of randomness of SRAM-based TRNGs is the noisy power-on values of SRAM cells [15]. One SRAM chip contains large amounts of six-transistor (6-T) cells, as displayed in Figure 1. When it is powered up, each cell in the chip is randomly initialized to ‘0′ or ‘1′ depending on the random mismatches deduced by production variations [18]. Then, a binary power-on sequence will be generated; this sequence can be used to derive a chip fingerprint or generate a true random number hinging on its entropy [15,19]. In experimental evaluations, the min-entropy is usually regarded as the worst-case (i.e., the greatest lower bound) measure of randomness (entropy) for SRAM power-on values [20]. The min-entropy of every bit ($bi{t}_i)$ in the SRAM power-on sequence can be calculated by Equations (1) and (2).

$$H_{min}^{bi{t}_i}=-lo{g}_2{P}_{i,max}$$

(1)

$$P_{i,max}=\max \left(P_{i,1},P_{i,0}\right)$$

(2)

where $P_{i,1}$ ($P_{i,0}$) is the probability of the corresponding cell being initialized to ‘1′ (‘0′).

Assuming that every bit in the start-up sequence is independent, the average min-entropy of per bit can be defined as follows [19]:

$$H_{min}^{bit}=\frac{{{\displaystyle \sum }}_{i=1}^n{H}_{min}^{bi{t}_i}}{n}=\frac{-{{\displaystyle \sum }}_{i=1}^{n}lo{g}_2{P}_{i,max}}{n}$$

(3)

$$0\le H_{min}^{bit} \le 1$$

(4)

where n represents the length (number of bits) of the start-up sequence. Unless otherwise specified, min-entropy hereinafter means$H_{min}^{bit}$.

Low min-entropy indicates that start-up values possess good repeatability and are suitable for extracting chip-specific fingerprints [19]. On the other hand, a higher min-entropy indicates that SRAM power-on values will be more random and can provide a great entropy source for the construction of a TRNG [21].

Thorough simulations and measurements of SRAM cells reveal that the mismatch of threshold voltage between P1 and P2 ($\Delta V_{th}$,$\left|\Delta V_{th}\right|=|V_{th,p1}-V_{th,p2}|$) dominates the power-on process [22,23,24]. Assuming $\left|\Delta V_{th}\right|$ is large enough (e.g., $\left|V_{th,p1}\left|\gg \right|V_{th,p2}\right|$), such a cell is called a strong cell. Strong cells have preferred (nonrandom) power-on values [21] and thus their occurrence must be minimized as much as possible for the TRNG construction in this paper.

On the other hand, there always exist some cells in which $\left|\Delta V_{th}\right|$ is very small ($\left|V_{th,p1}\right|\approx \left|V_{th,p2}\right|$); these are called noisy (weak) cells [24,25]. The power-on values of such cells are easy to flip between any two power-on measurements due to inevitable environmental noise. These noisy cells increase the entropy of the power-on sequence and provide a superb source of randomness, therefore making it possible to utilize SRAM as a TRNG [19].

2. Related Works and Our Contributions

As far as we know, studies on utilizing SRAM power-on values to construct TRNGs have newly risen in the last several years. Holcomb and Burleson et al. [15] first proposed the idea of extracting random numbers from SRAM power-on values. The main bottleneck of this type of application is that only a small percentage of SRAM bits behave with noisy power-on characteristics and the min-entropy generally does not exceed 0.1. Besides that, the data remanence effect [26] also severely limits the throughput of generated random bitstreams. To overcome the issue of randomness, several approaches have been recently proposed.

Aysu and Gulcan et al. [27] xored the raw SRAM power-on bytes multiple times to generate random numbers. In their implementation, 1024 bits of raw SRAM data is 8-fold XORed to obtain a 128-bit random string. Vincent and Erik et al. [19] proposed one method of conditioning an original power-on sequence into a true random seed using Secure Hash Algorithm 256 (SHA-256) and then instantiating a deterministic random bit generator (DRBG) with this seed to generate pseudorandom bitstreams. Due to low entropy, no less than 1600 bytes of SRAM power-on values must be condensed to generate a 256-bit true random seed in this work. In order to improve the randomness of the original SRAM power-on sequence, Kiamehr and Golanbari et al. [21] suggested leveraging the transistor aging effect to increase min-entropy to about 0.5. However, they did not carry out accelerated aging experiments to verify the scheme. In addition, the throughput of generated true random numbers was seldom taken into consideration in the previous works.

The performance of SRAM-based TRNG is strengthened specifically by the following main contributions in this work:

• Ionization irradiation increases the min-entropy over 20 times, which is a remarkable randomness improvement upon the existing works. In other words, about only 5% of the SRAM cells are needed to generate the true random bitstreams of the same length as the ones before irradiation, which significantly promotes the utilization rate of memory cells and decreases the area and power consumption per random bit generation. Furthermore, putting SRAM chips that are powered off into the irradiation lab is the main operation in our randomness improvement scheme, and this has a much lower cost and is simpler to implement compared to designing a dedicated SRAM cell to enhance inherent noise sensitivity (as in [11]).
• Throughput is another obstacle for utilizing SRAM as a TRNG because the power-down time between two power-on cycles must be long enough to avoid the degradation of the randomness of power-on values by the remaining charge. Many researchers even give up optimizing throughput [13,21,27,28]. Ionization irradiation can accelerate charge leakage and hence decrease the minimal power-down period between successive two power-on cycles from approximately 250 ms to about 1.5 ms, which makes a great contribution to the throughput of TRNG. It can generate National Institute of Standards and Technology (NIST) SP 800-22 compatible true random bitstreams with throughput of 178 Mbps, which is four times as high as that achieved in [19].

The rest of this paper is organized as follows: The entire TRNG design scheme is outlined in Section 3. The comprehensive improvements of total ionizing irradiation (TID) on SRAM power-on characteristics are described in detail in Section 4. Thereafter, the compact hardware postprocessing to achieve cryptographic quality randomness is implemented on FPGA in Section 5. Finally, conclusions are drawn in Section 6.

3. Proposed SRAM-Based TRNG Scheme

The procedure of the proposed TRNG is shown in Figure 2. In the stage of radiation exposure, the randomness of SRAM power-on sequence is enhanced by TID. In the subsequent hardware postprocessing, SRAM is repeatedly powered on to get true random bitstreams continuously. During each power-on cycle, every $n$ bits of power-on values are integrated into one block, which is conditioned into a 256-bit true random string with full entropy (i.e., the amount of entropy in the string is equal to its length [20,29]) by means of SHA-256 hash function.

In order for the output string of SHA-256 to have full entropy (256 bits), the amount of entropy at the input of the hash function should be at least 256 bits [19,30]. This transforms into the demand for the block size.

$$H_{min}^{bit}\times n\ge 256$$

(5)

In addition, throughput of the true random bitstreams is also in the scope of this work.

$$\begin{array}{c}throughput=\frac{amount of bits generated per cycle}{needed time}= \frac{S}{P{D}_T+SH{A}_T}=\frac{256\times i}{P{D}_T+i\times \frac{c}{f}}\\ =\frac{256\times \frac{m}{n}}{P{D}_T+\frac{m}{n}\times \frac{c}{f}}=\frac{256}{\frac{P{D}_T\times n}{m}+\frac{c}{f}}\end{array}$$

(6)

where $S$ represents the amount of true random bits generated during per power-on cycle, $P{D}_T$ is the power-down period between two power-on cycles, $SH{A}_T$ is the time taken by SHA-256 calls, $f$ represents the clock frequency of hardware platform used to perform SHA-256, $c$ denotes the number of clock cycles taken to perform SHA-256 single call, $i$ and $n$ respectively represent the number of blocks and the size of single block and $m$ expresses the capacity of SRAM memory.

It is obvious from Equation (6) that fast clock frequency ($f$) and large memory capacity ($m$) both are beneficial to throughput; short power-down period ($P{D}_T$) and small block size ($n$) are also preferred considering throughput.

However, the contradiction between throughput and randomness must be noticed. On the one hand, both block size and power-down time should be decreased as much as possible to improve throughput. However, power-down time must be long enough to avoid the remaining charge [26] between the two power-on cycles degrading the randomness of power-on values. Analogously, with too small of a block size, it be cannot guaranteed that the generated bitstreams will process full entropy [19,31].

In the next section, we will explain how to utilize TID to resolve the contradiction between randomness and throughput.

4. Impact of TID on SRAM Power-On Characteristics

In order to utilize the TID effect to improve SRAM power-on characteristics, there should be no supply voltage connected to the power pin of SRAM chip, and the other signal pins must also be grounded during radiation experiments, so the all transistors will undergo ionization irradiation with zero voltage bias. The detailed physical mechanisms behind this type of irradiation bias are illustrated in the Appendix A. The basic idea is described below.

Assume that there is a strong cell (e.g., $\left|V_{th,p1}\right|\gg \left|V_{th,p2}\right|$). In such case, the oxide field existing in P1 is weaker than that in P2 during irradiation with zero voltage bias. Although the electron–hole pairs generated per second are equal in both transistors, the amount of un-recombined holes that become trapped charges is lower in P1 due to a feebler oxide field. Therefore, the threshold voltage shift of P1 will be smaller than that of P2, and the threshold voltage of P2 will gradually catch up with P1 after multiple iterative irradiation experiments. In sum, the TID effect with zero voltage transforms a strong cell ($\left|V_{th,p1}\left|\ll \right|V_{th,p2}\right|$ or $\left|V_{th,p1}\left|\gg \right|V_{th,p2}\right|$) into a weak cell ($\left|V_{th,p1}\left|\approx \right|V_{th,p2}\right|$). As for a weak cell, it retains a noisy power-on characteristic under radiation, as the threshold voltages of both two P-channel Metal Oxide Semiconductor (PMOS) transistors shift almost equally.

Considering the above factors, the randomness of all of the SRAM chip power-on values will be enhanced under irradiation with zero voltage bias. To assess the impact of TID on SRAM power-on characteristics quantificationally, irradiation experiments were performed on one type of commercial SRAM with a memory capacity of 1 Mbit, manufactured by 90 nm CMOS technology. Our experiments were carried out using the Cobalt-60 Irradiation Source of Peking University in China, and its dose rate is 50 Rad/s. Five SRAM chips (hereinafter denoted as Chip #1 to Chip #5) were randomly selected for testing. The experiment steps are shown in Figure 3.

Every tested chip was powered on, and its start-up values were sampled 100 times before irradiation, for contrast with the postirradiation cases. Thereafter, the chips were powered off and suffered ionization irradiation iteratively; for each additional 500 Krad(SiO₂) doses, the chips were taken out to observe their power-on characteristics. To ensure that the normal read–write function of SRAM chips would not be damaged by the TID effect, 2 Mrad(SiO₂) was chosen as the maximal irradiation dose.

As an important indicator of randomness, the min-entropy ($H_{min}^{bit}$) was calculated at each dose step. As displayed in Figure 4, the min-entropy grew from about 0.03 to more than 0.75 as the total dose gradually increased to 2 Mrad(SiO₂) for all tested chips, which exceeds a 20-fold increase. Besides the improvement of randomness, the rising min-entropy can also help to decrease the block size ($n$) and thus increase the throughput in the subsequent hardware postprocessing, as discussed in Section 5.

It can be also observed that the sample chip with the worst randomness improvement was the Chip #4; this chip is regarded as one special sample for evaluating the proposed TRNG scheme conservatively in the following statements.

Figure 5 shows the probabilities of cells in Chip #4 being initialized to ‘0′ (P0). Before irradiation, the P0 value of most cells was either 0 or 1, which means that the SRAM power-on values are not random. However, by applying irradiation iteratively, P0 of most cells gradually converged close to 0.5. This reveals the obvious randomness improvement of the SRAM power-on values.

In addition to the assessment of randomness, the data remanence effect, which exerts strong influence on the throughput of the proposed TRNG, was characterized. One SRAM chip was powered down after initializing its cells to all 0′s or all 1′s; following a short period, the chip was repowered on. If the power-down period ($P{D}_T$) was too short, then the data would deterministically revert to the previous written state. As the power-down period increased, the charges remaining in the parasitic capacitors would gradually be reduced so that more and more SRAM cells would turn over their power-on values which were opposite to the previous written ones [26]. If the power-down period was long enough, then the charges would leak completely and the SRAM chip would power up to its random state (i.e., the data stored in about 50% of cells would flip). We denote the shortest power-down period making the portion of flipped cells converge to a stable value near 50% as $P{D}_{T\_min}$. When SRAM power-on values are utilized to construct a TRNG, the power-down period between any two power-on cycles must not be lower than $P{D}_{T\_min}$ to avoid the influence of data remanence and guarantee randomness of the generated bitstreams.

Figure 6a shows the portions of flipped cells in Chip #4 when the power-down period was swept from 10 to 325 ms before irradiation. In both write ‘1′ and write ‘0′ cases, $P{D}_{T\_min}$ reached up to about 250 ms. Figure 6b displays the sweep results of when Chip #4 was exposed to irradiation of 2 Mrad(SiO₂), and $P{D}_{T\_min}$ took only approximately 1.4 ms for both write ‘1′ and write ‘0′ cases. The dramatic decrease of $P{D}_{T\_min}$ will make a great contribution to the throughput of a TRNG.

5. Hardware Postprocessing

As depicted in Section 4, irradiation exposure can make SRAM chips a great entropy source. The decrease of $P{D}_{T\_min}$ also makes it possible to generate random bitstreams with high throughput. However, it is still necessary to rigorously judge the viability of utilizing the raw power-on values as true random bitstreams. For this purpose, the National Institute of Standards and Technology (NIST) SP 800-22 test was carried out on the power-on sequence of Chip #4 for both pre- and postirradiation cases. As is shown in

Table 1. National Institute of Standards and Technology (NIST) test results for different bitstreams. The list of applied tests is as follows: (1) monobit frequency test, (2) block frequency test, (3) run test, (4) longest run, (5) binary matrix rank, (6) spectral test, (7) non-overlapping template matching, (8) overlapping template matching, (9) Maurer’s universal statistic test, (10) linear complexity test, (11) serial test, (12) approximate entropy test, (13) cumulative sums (forward) test and (14) cumulative sums (reverse) test.

	Pre-Irradiation (Power-Down Period ($\mathit{P}{\mathit{D}}_{\mathit{T}}$) = 3 ms, Block Size ($\mathit{n}$) = 370)		Under 2 Mrad(SiO2) (Power-Down Period ($\mathit{P}{\mathit{D}}_{\mathit{T}}$) = 3 ms, Block Size ($\mathit{n}$) = 370)
	Power-on Sequence	Conditioned Bitstreams	Power-on Sequence	Conditioned Bitstreams
1	✕	✓	✓	✓
2	✕	✓	✓	✓
3	✕	✓	✓	✓
4	✕	✓	✓	✓
5	✓	✕	✓	✓
6	✕	✕	✓	✓
7	✕	✓	✓	✓
8	✕	✓	✓	✓
9	✕	✓	✕	✓
10	✓	✓	✓	✓
11	✕	✕	✓	✓
12	✕	✕	✕	✓
13	✕	✓	✓	✓
14	✕	✓	✓	✓

, the power-on sequence before irradiation failed almost all of the tests due to low entropy and strong data remanence effect at the power-down period of 3 ms (as is illustrated in Figure 6a); the power-on sequence under 2 Mrad(SiO₂) dose showed a great randomness improvement in behavior but still could not pass all the tests, needing postprocessing to improve the statistical properties [32].

Actually, the raw random bits of many TRNGs become biased and cannot meet the NIST SP800-22 test standards [10]; therefore, some postprocessing methods are commonly employed on the raw random bits to generate the true random numbers with full entropy that can pass all NIST test items. The postprocessing schemes include but are not limited to digital postprocessing using the XOR function [33,34,35,36,37], Von Neumann extractor [38,39,40,41], Hash functions (e.g., Secure Hash Algorithm 256, (SHA-256)) [11,19,42] and even circuit calibration technologies [10,43]. SHA-256 was selected to complete conditioning in this paper as it exists in many encrypted communication coprocessors [42] and its use might not increase overheads in practical applications.

We performed SHA-256 on Xilinx XC7Z020 [44] with clock frequency of 200 MHz, and our implementation could perform one hash at 64 clocks. By performing this kind of compact postprocessing on the power-on values under 2 Mrad(SiO₂), conditioned random bitstreams with throughput of 178 Mbps were generated, which were able to pass all NIST test items, as shown in Table 1. For the sake of contrast, the same operations were implemented on the power-on values before irradiation, which could generate bitstreams with the same throughput as the ones under 2 Mrad(SiO₂). However, the conditioned bitstreams still could not pass all tests, as displayed in Table 1.

It can be summarized from the above NIST test results that high throughput requires small block size (i.e., input string length of SHA-256) and short power-down period. The power-on sequences under 2 Mrad(SiO₂) could completely meet these two requirements and hence generate true random bitstreams with throughput up to 178 Mbps. However, power-on sequences without irradiation collected at such a small block size (370 bits) and short power-down period (3 ms) behave too poorly in terms of randomness due to large mismatches in SRAM cells and strong data remanence effect.

Additionally, it is necessary to further investigate the upper limit of throughput on the promise of generating true random numbers with full entropy by means of the proposed hardware implementation. As is revealed by Equation (6), the throughput is mainly constrained by block size ($n$), power-down period ($P{D}_T$), memory capacity ($m$) and clock frequency ($f$). Under the promise of the conditioned bitstreams behaving with full entropy, the lower bound of block size can be defined by Equation (5) (i.e., $n\ge \frac{256}{H_{min}^{bit}}$), and $P{D}_T$ cannot be shorter than $P{D}_{T\_min}$ to eliminate the impact of remaining charge. Thus, the upper bound of throughput can be approximated as follows:

$$throughput =\frac{256}{\frac{P{D}_T\times n}{m}+\frac{64}{f}}\le \frac{256}{\frac{P{D}_T\times 256}{m\times H_{min}^{bit}}+\frac{64}{f}} \le \frac{ 256}{\frac{P{D}_{T\_min}\times 256}{m\times H_{min}^{bit}}+\frac{64}{f}}$$

(7)

$P{D}_{T\_min}$ and $H_{min}^{bit}$of Chip #4 were measured in Section 4 for both pre- and postirradiation situations and thus can be seen as constants here. Next, the maximum throughputs at different memory capacities and clock frequencies are compared for both pre- and postirradiation situations.

Before irradiation, the low entropy and long power-down period heavily encumber throughput. As displayed in Figure 7a, the three almost coincident curves indicate that neither large memory capacity nor high clock frequency can produce reasonable throughput, as it cannot reach 1 Mbps even with memory capacity of 8 Mb and clock frequency of 667 MHz. Thus far, we can conclude that it is unpractical to generate true random bitstreams with high speed by utilizing the raw power-on values without irradiation.

For the chip under 2 Mrad, random bitstreams with high throughput can be obtained due to the mutual improvements of both randomness and throughput benefiting from irradiation exposure. As shown in Figure 7b, both large memory capacity and high clock frequency vigorously motivate the throughput. It also shows that the throughput can be widely adjusted according to the application requirements by using different clock frequencies and memory capacities. Of course, at a certain clock frequency, the throughput gradually reaches its saturation point with the memory capacity increase. This characteristic can also provide a reference for optimized design of a TRNG.

Finally, a comparison with prior works is presented in

Table 2. Comparison with prior works.

	[1]	[21]	[11]	[45]	This Work
Min-entropy of SRAM power-on values	0.02	0.5	0.89	0.103	0.75
Type of conditioned bitstreams	Pseudorandom	--	True random	Pseudorandom	True random
Throughput of conditioned bitstreams	40 Mbps	--	--	--	178 Mbps
NIST SP 800-22 tests on conditioned bitstreams	Pass	--	Pass	Pass	Pass
Postprocessing	Hash	--	Hash	Hash	Hash
Normal storage function	Yes	Yes	No	Yes	Yes

. The entropy of SRAM power-on sequence obtains more significant improvement by impact of ionizing irradiation, and our proposed SRAM-based TRNG can generate true random bitstreams with higher throughput, rather than obtaining a true random seed to instantiate a deterministic random bit generator (DRBG) and generate pseudorandom bitstreams [21].

6. Conclusions

In our work, a novel SRAM-based TRNG is proposed; its implementation consists of two phases: irradiation exposure with zero voltage bias and hardware postprocessing. During the irradiation phase, the TID effect is utilized to make SRAM cells less mismatched and hence to obtain more random power-on values. The experiment results show that the min-entropy of SRAM power-on values can increase over 20 times as ionization dose is accumulated to 2 Mrad(SiO₂). Besides, the minimal power-down period between two successive power-on cycles can decrease from approximately 250 ms to about 1.5 ms, which makes a great contribution to the throughput of a TRNG. In the subsequent hardware postprocessing, SRAM chip should be repeatedly powered up; during each power-on cycle, SRAM power-on values are conditioned into true random bitstreams by means of SHA-256. One implementation on FPGA can generate bitstreams with throughput of 178 Mbps, which can pass all NIST SP 800-22 tests.