The principal aim is energy harvesting from low RF density waves available at 868 MHz. The received RF power generally ranges from 0 to −30 dBm relative to transmitted power. We propose adding an inductor

L in series with

C_{1} (

Figure 3) in order to store the energy in a magnetic field. Energy is stored during the negative cycle wave and returned during the positive one. The couple (

L,

C_{1}) operates like an additional power source during the positive alternation [

19]. The power stored in the inductance magnetic field is given by the following relation, Equation (3), in terms of the current

i:

#### 4.1. Novel Approach for a Signal Voltage Multiplier Circuit

To explain the principle of this approach, we have carried out a simulation of the circuit at low frequency with standard elements using Simplorer software.

Figure 4 illustrates the inductor voltage and current during the transitional period.

The current passing through the inductor is always continuous. The potential of the inductor is not proportional to the inductor current. The current passing through the inductor is constantly charging and discharging. Therefore, the inductor generates an opposite voltage polarity in order to limit the current variation [

20]. This potential can be used to charge the capacitances

C_{1} and

C_{2}. Current and voltage discontinuity, presented in

Figure 4, is caused by the status variation of diodes

D_{1} and

D_{2}. The simulation results show the voltage behavior of the circuit elements for different time slots (

Figure 5).

During phase 1,

D_{2} is blocked until the condition given by Equation (4) is fulfilled:

C_{1} and

C_{2} are equal to 1 mF. The negative alternation of the input voltage (

V_{in} equal 5 V, the frequency is equal to 1 kHz) crosses

D_{1} to charge the capacitor

C_{1} and the inductor

L. We denote that

R is equal to 0.1 Ω, which is the internal resistance, and

V_{ɣ} is equal to 0.8 V, which is the threshold voltage of the diodes. The variation of the inductor current

i causes an opposite voltage polarity

V_{L} across its terminals. The voltage

V_{C}_{1} across

C_{1} is determined by Equation (5):

During phase 2,

D_{1} is blocked and the capacitance

C_{1} discharges through

D_{2} to charge the capacitor

C_{2}. The voltage across C

_{2} is determined by Equation (6):

The system change the status from phase 2 to another phase when Equation (7) is fulfilled:

During phase 3, both diodes D_{1} and D_{2} are blocked as long as Equations (4) and (7) are verified. The charging cycle of C_{1} or C_{2} restarts again depending on the conditions established by Equations (4) or (7). At the end, the system is stable. C_{1} and C_{2} maintain the charge level.

The proposed approach aims to ameliorate the charging of capacitances

C_{1} and

C_{2} using the opposite voltage polarity generated by the inductor

L.

Figure 6 shows a comparison between the classic voltage multiplier circuit and the novel approach. The novel approach provides higher output voltage (

V_{C}_{2}) and exceeds the classic voltage multiplier circuit (

V_{C}_{20}). The system establishing time is reduced by the same inductor. Simulations with varied inductor values show a better performance for L equal to 0.023 mH (

Figure 6).

The first sub-circuit of

Figure 3 represents a second order system. The solution of its equations leads to determine the charging expression of

C_{1}, as defined in Equation (8):

Where

V (Equation (9)) and

ѱ (Equation (10)) are, respectively, the amplitude and the phase of the particular solution.

The damping coefficient

λ is defined in Equation (11):

The comparison between the simulation and the analytical expression validates the expression of

V_{C}_{1} during phase 1. For phase 2,

C_{1} is discharging and

C_{2} is charging. From the simulation results,

V_{C}_{1} and

V_{C}_{2} are characterized with the same slope but in opposite sign (negative for

V_{C}_{1} and positive

V_{C}_{2}). In order to determine the expression of the optimal inductor value from the expression of

V_{C}_{2} max, it is necessary to express the initial charge of

C_{1} for phase 2. Since it is difficult to solve such equations with multiple transcendental functions, we propose to solve it with numerical methods. After multiple simulations, with a varied input parameters, the result show that for

ɷ equal

ɷ_{in} the system has a higher outcome. Where

ɷ_{in} is the pulse of the input signal and

ɷ is defined in Equation (12):

Based on these simulations results, it is easy to give an optimal expression estimation of

L (Equation (13)):

#### 4.3. Simulations for a Modified Voltage Multiplier Circuit

The modified voltage doubler circuit is simulated using Advanced Design System (ADS) from Agilent. The ADS simulation employs the device model of HSMS-2850 Schottky diode parameters and achieved the results presented in

Figure 9.

To discuss the RF-DC converter circuit performances, simulations were carried out. The results presented in

Figure 10 show the conversion efficiency for one and three multiplier stages for variable input power from −40 to 20 dBm. The proposed design with inductor is compared to the classic voltage multiplier circuit without inductor for a resistive load of 50 kΩ. The novel design reaches an efficiency which is much higher than the classic voltage multiplier circuit, especially for low input power. With one stage, the novel design reaches greater efficiency, with a peak of 79%. With three stages, the novel design reaches 83% peak efficiency. The novel RF-DC converter circuit consists of diodes, which have nonlinear component behavior. In addition, the circuit design itself exhibits nonlinear effects due to the parasitic influence of the used elements. This implies that the response of the harvester circuit varies with the received power amount delivered by the antenna. RF input power variation does not correlate with the output power of the harvesting circuit.

The output load of the RF-DC converter circuit needs to be improved using harmonic balance in order to enhance the PCE. The output DC power is measured around 50 kΩ resistive load.

Figure 11 illustrates the load influence on one stage RF-DC converter circuit PCE. The previous simulation parameters and a variable resistive load are used to investigate the load impact on the PCE. Referred to the sensor node impedance and according to sleep mode, the proposed RF-DC converter is loaded by 50 kΩ.

The novel designed RF-DC converter is capable to convert an RF wave to a DC signal and achieving higher efficiency based on passive elements. Simulations are conducted in ADS under the same scenarios in order to prove one voltage multiplier topology from Villard or Dickson configurations.

Figure 12 shows the simulation results for two stages Dickson configuration compared to two stages Villard configuration. The Dickson topology efficiency surpasses Villard topology efficiency all over the full input power range. The Dickson architecture is selected as a parallel capacitor configuration to reduce losses in each stage.

The number of RF-DC converter stages has a signficant effect on the circuit output power. The voltage multiplier stages are reformed and arranged in cascade. The output power is directly proportional to the stage number and the input power. However, practical constraints limit the approved stages number and, therefore, the output power. Sweep input power parameters from −40 to 20 dBm was used in simulations with a variety of stage numbers from 1 to 11 stages.

Figure 13 shows the impact of the stages number on PCE and the output power of the new RF-DC converter circuit design. Finally, the PCE variation becomes negligible. However, when the stage number increases, the efficiency curve shifts towards the higher input power region. This means an increase of the power losses in the region of low input power.

#### 4.4. Design and Experiment Setup for a Modified Dual Stages Voltage Multiplier Circuit

The receiver antenna is connected to the RF-DC converter block via a reactive matching circuit in order to efficiently load and increase the voltage gain. This allows a decrease in the reflected signal and, therefore, losses.

Figure 14 presents a two-stage voltage multiplier circuit. The return loss S

_{11} parameter and the circuit impedance are measured relative to the input RF power at −10 dBm and the effective frequency matched to 50 Ω.

Experiment results prove that the circuit design runs at 868 MHz. The final modified RF-DC converter printed circuit board (PCB), shown in

Figure 15, is fabricated using FR-4 substrate. It contains two layers, one electrically connects the passive components and the second is a ground plane. A large deviation between simulation and experiment results is shown in

Figure 15. This divergence is caused by components’ tolerances and the parasitic capacitance produced by the circuit layout. PCB layers and non-ideal component behaviour generate upper losses, particularly, for high frequency and the low input power range. The HSMS-2850 library model is being supplied for simulation to reflect typical baseline aspects. Certain performance modulations miss the perfection compared to the real Schottky diode behavior. The model limitation and the sensitivity of Schottky diode parameters to the ambient temperature produce a mismatch between the simulation and experimental results.

At −10 dBm input power the measured PCE of the modified RF-DC converter is about 19.49%. The proposed design provides 19.43 µW output power and around 1 V output voltage. The circuit achieves 26.21% of PCE at −6 dBm. It delivers 78.72 µW and reaches 2 V output voltage. This means the proposed modified RF-DC converter design can power a diversity of microcontrollers. Among them, the MSP430L092, which runs with 0.9 V with 6 µW power consumption in standby mode and 3 µW in off mode. It consumes 45 µA in active mode and works at 1.3 V [

22].

In order to evaluate the efficiency of the proposed dual-stage design, we compare archived experimental results to the state of the art presented in [

23]. LPD, presented in [

23], is a low power design harvester consisting of a seven-stage classic voltage multiplier circuit connected to a 100 kΩ load. It operates at 915 MHz and employs Agilent HSMS-2852 Schottky diodes, which are used for our proposed design. The setup results of the LDP, as published in [

23], are presented in

Figure 16. LPD-PCE is about 10% at −10 dBm input power and around 15% at −6 dBm. Consequently, this performance evaluation purpose shows a comparison of LPD-PCE and the proposed dual-stage design. The proposed dual-stage design provides higher efficiency. The performance of the proposed dual-stage design stands out in the low power region where the LPD efficiency is low. The main target of this RF energy harvesting system is to yield energy of a low RF density area. The incident RF power in the energy harvesting case is very low. The input power range is limited and rarely exceeds 0 dBm for ambient RF energy harvesting. In [

23] a comparison of LPD with the commercial RF energy harvester from a Powercast P1100 is carried out.

Figure 16 shows a PCE of P1100 across the 100 kΩ load [

23]. The comparison demonstrates that the proposed design leads to a higher PCE than the P1100 at low input power.