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Open AccessArticle

A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction

Institute of Microelectronics, Tsinghua University, Beijing 100084, China
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Academic Editor: Leonhard M. Reindl
Sensors 2015, 15(9), 22509-22529; https://doi.org/10.3390/s150922509
Received: 17 July 2015 / Revised: 20 August 2015 / Accepted: 25 August 2015 / Published: 4 September 2015
(This article belongs to the Section Sensor Networks)
This paper proposes a real-time feature extraction VLSI architecture for high-resolution images based on the accelerated KAZE algorithm. Firstly, a new system architecture is proposed. It increases the system throughput, provides flexibility in image resolution, and offers trade-offs between speed and scaling robustness. The architecture consists of a two-dimensional pipeline array that fully utilizes computational similarities in octaves. Secondly, a substructure (block-serial discrete-time cellular neural network) that can realize a nonlinear filter is proposed. This structure decreases the memory demand through the removal of data dependency. Thirdly, a hardware-friendly descriptor is introduced in order to overcome the hardware design bottleneck through the polar sample pattern; a simplified method to realize rotation invariance is also presented. Finally, the proposed architecture is designed in TSMC 65 nm CMOS technology. The experimental results show a performance of 127 fps in full HD resolution at 200 MHz frequency. The peak performance reaches 181 GOPS and the throughput is double the speed of other state-of-the-art architectures. View Full-Text
Keywords: AKAZE; binary feature descriptor; feature extraction; hardware architecture; VLSI implementation AKAZE; binary feature descriptor; feature extraction; hardware architecture; VLSI implementation
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Jiang, G.; Liu, L.; Zhu, W.; Yin, S.; Wei, S. A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction. Sensors 2015, 15, 22509-22529.

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