Figure 1.
Electronic interface for portable sensing applications.
2.1. Sensor Signal Processing System
Figure 2 shows the block diagram of the custom sensor signal processing system. It has been designed in a low cost 1.8 V-0.18 µm CMOS technology. The system design is fully compatible with digital technologies, thus allowing its implementation in future mixed-mode full-custom System-on-Chip (SoC) solutions. The signal processing system consists of a pre-conditioning amplifier and a dual-phase LIA.
The pre-conditioning amplifier, based on a classical inverting operational amplifiers (OpAmp)-based scheme, provides high input impedance, sets the adequate common-mode voltage to VDC_ref = VDD/2 for a maximum input range under single VDD supply operation and amplifies the sensor OUTPUT signal by a gain factor G selectable through an external feedback resistor REXT. Besides, the maximum bandwidth of this input stage can be reduced by means of an external capacitor CEXT in parallel with REXT to reduce noise contribution.
Figure 2.
Block diagram of the signal conditioning stage.
Figure 2.
Block diagram of the signal conditioning stage.
Next, the integrated dual-phase LIA recovers the information from the preconditioned sensor signal
Vin. The choice of a dual-phase architecture avoids phase dependency [
11,
12]. Each of the two parallel PSD branches includes an instrumentation amplifier (IA) with switched inputs, which are respectively controlled by two square signals
Vr and
Vr90, with 90° phase shift, so that the PSD or mixer output is:
In this way, Vin is rectified over the virtual ground VDC_ref = VDD/2. Then Vmixer_x, Vmixer_y are low-pass filtered providing the mean values VX, VY. An external selectable first order RLCL low pass filter has been chosen for high versatility. For the tests next conducted, the low pass filter cut-off frequency has been set to 5 Hz, as a trade-off between low pass filtering and measurement speed.
Finally, for signal information recovery, if
Vin is a sinusoidal signal, its amplitude
A and phase φ can be recovered from
VX and
VY as indicated in [
11]. Likewise, if
Vin is a square signal, then signal amplitude and phase φ can be obtained as indicated in
Table 1 [
22].
Table 1.
Amplitude and phase recovery equations for an input square wave.
Table 1.
Amplitude and phase recovery equations for an input square wave.
VX | VY | A | φ |
---|
| | | |
| | | |
| | | |
| | | |
Figure 3 details the scheme of the dual LIA. A precision differential amplifier architecture with input buffering has been chosen as instrumentation amplifier. Resistors R
F and R
G have been implemented with a value of 10 kΩ, thus setting the gain of this stage to 1. The IA active building blocks are operational amplifiers, all identical and equal to the OpAmp used in the pre-conditioning stage for modularity. Besides, this unity-gain design makes that the dynamic performances of the IA are straightforward determined by those of the core OpAmp, which is thus a critical device. Due to the lowering of power and supply voltage in portable applications, OpAmps lose a significant amount of operating range. These constraints impose special demands on their low-voltage low-power (LVLP) high performance CMOS design [
20].
Figure 3.
LIA scheme, detailing the instrumentation amplifier architecture: a precision differential architecture design with input buffering.
Figure 3.
LIA scheme, detailing the instrumentation amplifier architecture: a precision differential architecture design with input buffering.
In our case, rail-to-rail input/output operation maximizes the input signal span and increases the signal-to-noise ratio (SNR). It is also necessary to guarantee that the signal is exactly rectified at the midpoint of the supply voltage range (
VDD/2). Class AB operation improves power-efficiency, but it also allows fast settling response and high slew rate. This reduces phase jitter between the input and the processed signals and allows processing square signals, as those provided in microcontrolled-based systems [
23]. Other performances, such as high common-mode rejection ratio (CMRR), low distortion, high power supply rejection ratio (PSRR) and bandwidth (BW) are also to be preserved.
Taking into consideration all the above,
Figure 4 shows the schematic of the specifically designed two-stage AB OpAmp. Rail-to-rail common-mode input range is achieved by using a novel LVLP technique for rail-to-rail operation based on a MOS input stage with only one differential pair and switched level shifters driven by an auxiliary control circuit [
24]. Further, the NMOS input pair M
1 is class AB biased by means of adaptive biasing. The reason is twofold: firstly to boost the input pair currents when a large differential input signal
Vdiff =
Vin+ −
Vin− is applied, and secondly, to reduce the dependence of the input pair currents (and then, the transconductance) on the common mode voltage. In this case, cross-coupled floating batteries (M
1A, M
4, M
5) have been used for adaptive biasing. A rail-to-rail push-pull output stage has been used for a class AB output [
20]. The first stage output
V01 is directly tied to the PMOS transistor M
6 of the rail-to-rail push-pull output block, and through a level shifter (M
8, M
9) in the complementary NMOS transistor M
7 biased with an adequate DC level. Finally, the two stage OpAmp is compensated by means of a classical Miller compensation.
Table 2 summarizes the main characteristics of this integrated 0.18 μm CMOS OpAmp supplied at a single 1.8 V.
Figure 4.
Schematic of the designed 1.8 V class AB rail-to-rail two stage OpAmp. The auxiliary control circuit for rail-to-rail operation is depicted in grey.
Figure 4.
Schematic of the designed 1.8 V class AB rail-to-rail two stage OpAmp. The auxiliary control circuit for rail-to-rail operation is depicted in grey.
Table 2.
Operational amplifier performance summary.
Table 2.
Operational amplifier performance summary.
CMOS Process | 0.18 μm |
Supply | 1.8 V |
Open Loop Aain | 74 dB * |
Gain-Bandwidth Product | 2 MHz |
CMRR | 96 dB * |
Slew-Rate | 2.3 V/μs (for a capacitive load of 1 nF) |
THD | −62 dB (1 kHz, 1.75 Vpp) |
Input Common-Mode Range | Rail-to-rail |
Output Swing | Rail-to-rail |
Input Referred Noise | 63 nV/Hz1/2* (100 kHz) |
Power | 468 μW |
Figure 5 shows a microphotograph of the LIA active area (detail). The chip area and quiescent power consumption equal 306 × 157 μm
2 and below 2 mW per branch respectively.
Figure 5.
Integrated lock-in amplifier (detail) for the prototype, with an active area of 306 × 114 μm2. It includes the switches and instrumentation amplifiers (IA).
Figure 5.
Integrated lock-in amplifier (detail) for the prototype, with an active area of 306 × 114 μm2. It includes the switches and instrumentation amplifiers (IA).
2.2. Control System
The processing interface is controlled by a P8X32A Propeller microcontroller from Parallax (Parallax Inc., Rocklin, CA, USA). This microcontroller has been selected due to its high-speed processing features while maintaining a low current consumption and a small physical footprint. In order to perform this high-speed processing it comprises eight modules or processors (cogs) that can operate simultaneously. All eight processors are controlled from the same internal system clock so they use the same time reference. Each processor contains two advanced numerically controlled oscillators (NCO) that allow a precise frequency selection and phase shift. This feature allows using the microcontroller to generate in each cog two accurate square signals in quadrature configuration Vr and Vr90 required by the LIA to perform the PSD measurements.
The capability of the microcontroller to generate several quadrature square signals is especially relevant interfacing sensors arrays, as for instance, the so called electronic noses [
19,
23]. In these applications several sensors are employed in order to achieve a more precise measurement.
Using a 5 MHz quartz crystal as external reference combined with the 32-bit precision used by the microcontroller, it allows generating square signals up to 500 kHz with a frequency resolution of 0.001 Hz.
Finally, the LIA DC output voltages V
X and V
Y are digitized by two LTC2400 24-bit ADCs from Linear Technology (Linear Technology Corporate Headquarters, Milpitas, CA, USA). These devices provide a resolution of a few microvolts operating under a single power supply of 3.3 V. This high resolution is required when applying the herein proposed LIA interface with the microcantilever-based sensors used forward in this work to prove the system capability. These devices are controlled by a serial peripheral interface (SPI) protocol, providing the corresponding readings to the microcontroller. In this way, from the digitized values of
VX and
VY provided by the ADCs, the microcontroller recovers the amplitude and phase shift of the sensor signal
VIN applying the equations showed in
Table 1.