Search Results (3)

We report a dual-readout self-resetting CMOS image sensor that achieves a signal-to-noise ratio (SNR) exceeding 70 dB and resolves sub-percent optical contrast variations by effectivly suppressing reset artifacts. The proposed sensor employs a Dual-Readout architecture with two independent scanners operating with a temporal offset; while one readout system is in the self-reset “dead time”, the other remains active, thereby physically ensuring continuous data acquisition. To minimize pixel area while achieving high reconstruction accuracy, a minimum frame-to-frame difference algorithm is utilized for signal restoration without requiring in-pixel counters. A prototype chip fabricated in a 0.35-$\mathsf{\mu }$m process demonstrated SNR characteristics near the shot-noise limit, with a peak SNR exceeding 70 dB. Vascular phantom experiments using a carbon black suspension successfully visualized ±0.25% contrast fluctuations—dynamic signals previously undetectable by conventional sensors. This device provides a powerful platform for high-precision bio-imaging applications, including brain surface blood flow monitoring, where both wide dynamic range and high SNR are essential. Full article

To combine homomorphic public key encryption with reversible data hiding, a reversible data hiding scheme in homomorphic encrypted image based on EC-EG is proposed. Firstly, the cover image is segmented. The square grid pixel group randomly selected by the image owner has one reference pixel and eight target pixels. The n least significant bits (LSBs) of the reference pixel and all bits of target pixel are self-embedded into other parts of the image by a method of predictive error expansion (PEE). To avoid overflowing when embedding data, the n LSBs of the reference pixel are reset to zero before encryption. Then, the pixel values of the image are encrypted after being encoded onto the points of the elliptic curve. The encrypted reference pixel replaces the encrypted target pixels surrounding it, thereby constructing the mirroring central ciphertext (MCC). In a set of MCC, the data hider embeds the encrypted additional data into the n LSBs of the target pixels by homomorphic addition in ciphertexts, while the reference pixel remains unchanged. The receiver can directly extract additional data by homomorphic subtraction in ciphertexts between the target pixels and the corresponding reference pixel; extract the additional data by subtraction in plaintexts with the directly decrypted image; and restore the cover image without loss. The experimental results show that the proposed scheme has higher security than the similar algorithms, and the average embedding rate of the scheme is 0.25 bpp under the premise of ensuring the quality of the directly decrypted image. Full article

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle. Full article