Search Results (2)

Background/Objectives: Closed-loop phase-locked TMS aims to deliver stimulation at targeted EEG phases, but real-time phase prediction remains a practical bottleneck. Timing errors are especially harmful near peaks and troughs, where small offsets can substantially degrade phase targeting. We benchmark representative predictors and develop models that improve phase consistency while reducing peak/trough lag. Methods: Using the publicly available Monash University TEPs–MEPs dataset, we benchmark classical predictors (AR- and FFT-based) and recurrent baselines (LSTM, GRU). To quantify extremum-specific behavior critical for closed-loop triggering, we propose Mean Lag Time (MLT), defined as the average temporal offset between predicted and ground-truth extrema, alongside PLV, APE, MAE, and RMSE. We further propose a parallel DSC-Attention-GRU architecture combining depthwise separable convolutions for efficient multi-channel spatio-temporal feature extraction with self-attention for spatial reweighting and dependency modeling, followed by a GRU phase predictor. A lightweight SqueezeNet-Attention-GRU variant is also designed for real-time constraints. Results: LSTM/GRU outperform AR/FFT in capturing temporal dynamics but retain residual peak/trough lag. Across stimulation intensities and frequency bands, DSC-Attention-GRU consistently improves phase consistency and prediction accuracy and reduces extremum lag, lowering MLT from ~7.77–7.79 ms to ~7.50–7.56 ms. The lightweight variant maintains stable performance with an average 3.7% inference speedup. Conclusions: Explicitly optimizing extremum timing via MLT and enhancing multi-channel modeling with DSC and attention reduces peak/trough lag and improves phase-consistent prediction, supporting low-latency closed-loop phase-locked TMS. Full article

This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs. Full article