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Keywords = dummy WL

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9 pages, 4157 KiB  
Communication
Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory
by Kaikai You, Lei Jin, Jianquan Jia and Zongliang Huo
Micromachines 2023, 14(10), 1916; https://doi.org/10.3390/mi14101916 - 9 Oct 2023
Viewed by 1999
Abstract
To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. [...] Read more.
To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced by erasing disturbance of the dummy WLs at the joint region (Joint-DMYs) under multiple cycling. More specifically, after several erase cycling stresses, the increasing joint-DMY’s threshold voltage (Vt) due to the operational stress will finally result in additional disturbance to the adjacent data WLs. In this paper, we proposed this disturbance during erase originates from the backward injected electrons through FN tunneling based on our TCAD simulation result. Moreover, we also proposed an optimal erase scheme to reduce the backward electron injection and suppress the abnormal joint-DMY disturbance during the erase cycling. Full article
(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)
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6 pages, 1893 KiB  
Article
Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory
by Beomsu Kim and Myounggon Kang
Electronics 2022, 11(17), 2738; https://doi.org/10.3390/electronics11172738 - 31 Aug 2022
Cited by 1 | Viewed by 3142
Abstract
In this study, we have analyzed the optimal bias condition of dummy WL for the sub-block gate induced drain leakage (GIDL) erase operation in 16-layer 3D NAND flash memory. Three-dimensional NAND flash memory performs an erase operation in units of pages. Increasing the [...] Read more.
In this study, we have analyzed the optimal bias condition of dummy WL for the sub-block gate induced drain leakage (GIDL) erase operation in 16-layer 3D NAND flash memory. Three-dimensional NAND flash memory performs an erase operation in units of pages. Increasing the number of stacks increases the number of cells that are erased at one time, which can lead to undesirable durability degradation. In this case, the sub-block erase operation can reduce the burden on the cell by up to half, due to the erase operation. The distribution of the hole density (hDensity) and the potential, according to VDummy, was analyzed when block1 and block2 were erased by setting WL0:WL7 to block1, WL9:WL15 to block2, and WL8 to dummy WL. For the simulation results, block1 showed an optimal distribution of hDensity and potential in the order of 20 V, floating, and 0 V. In block2, the optimal distribution of hDensity was shown in the order of 20 V, floating, and 0 V, with the optimal distribution of the potential in the order of floating and 0 V. Full article
(This article belongs to the Special Issue Development and Application of New CMOS Devices)
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7 pages, 2017 KiB  
Article
Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location
by Sangwoo Han, Youngseok Jeong, Heesauk Jhon and Myounggon Kang
Electronics 2020, 9(2), 268; https://doi.org/10.3390/electronics9020268 - 5 Feb 2020
Cited by 8 | Viewed by 5951
Abstract
Natural local self-boosting (NLSB) was analyzed according to the location of a selected word-line (WL) where potential boosting occurs. When the same pattern occurred, it was found that the top cells (WL11 through WL15) and bottom cells (WL0 through WL4) have identically symmetrical [...] Read more.
Natural local self-boosting (NLSB) was analyzed according to the location of a selected word-line (WL) where potential boosting occurs. When the same pattern occurred, it was found that the top cells (WL11 through WL15) and bottom cells (WL0 through WL4) have identically symmetrical potential boosting. In addition, in the region of the middle cells (WL6 through WL10), a slight change in the potential boosting was also almost the same. In the 3D NAND, where there was a dummy WL (DWL), the NLSB for the edge WL changed as the pattern of the DWL changed. The DWL did not affect the NLSB of the main cell, regardless of the pattern. Therefore, the high potential of the edge WL could reduce the potential difference between the main cell and the edge WL using the DWL. Full article
(This article belongs to the Special Issue New CMOS Devices and Their Applications)
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