Sign in to use this feature.

Years

Between: -

Subjects

remove_circle_outline

Journals

Article Types

Countries / Regions

remove_circle_outline

Search Results (1)

Search Parameters:
Keywords = digital quadricorrelator frequency detector (DQFD)

Order results
Result details
Results per page
Select all
Export citation of selected articles as:
16 pages, 1618 KiB  
Article
A Referenceless Digital CDR with a Half-Rate Jitter-Tolerant FD and a Multi-Bit Decimator
by Jaekwon Kim, Youngjun Ko, Jahoon Jin, Jaehyuk Choi and Jung-Hoon Chun
Electronics 2022, 11(4), 537; https://doi.org/10.3390/electronics11040537 - 11 Feb 2022
Cited by 1 | Viewed by 3899
Abstract
A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Additionally, we proposed a multi-bit decimator circuit [...] Read more.
A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Additionally, we proposed a multi-bit decimator circuit that losslessly down-samples up/down data from a phase detector to reduce the recovered clock jitter. The down-sampled multi-bit phase information is processed by a digital loop filter to adjust the phase of the recovered clock. Fabricated in a 28-nm CMOS technology, the test chip achieves a power efficiency of 1.3 pJ/bit at 10 Gb/s. Full article
(This article belongs to the Section Circuit and Signal Processing)
Show Figures

Figure 1

Back to TopTop