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Keywords = digital PA (DPA)

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15 pages, 12762 KiB  
Review
Advanced Doherty Power Amplifier Architectures for 5G Handset Applications: A Comprehensive Review of Linearity, Back-Off Efficiency, Bandwidth, and Thermal Management
by Shihai He and Huan Chen
Chips 2025, 4(2), 20; https://doi.org/10.3390/chips4020020 - 6 May 2025
Viewed by 1324
Abstract
This paper presents a comprehensive review of GaAs HBT-based Doherty power amplifiers (DPAs) targeting 5G New Radio (NR) handset applications. Focusing on the critical challenges of linearity enhancement, back-off efficiency improvement, bandwidth extension under low-voltage (3.4 V) operation, and chip thermal management, the [...] Read more.
This paper presents a comprehensive review of GaAs HBT-based Doherty power amplifiers (DPAs) targeting 5G New Radio (NR) handset applications. Focusing on the critical challenges of linearity enhancement, back-off efficiency improvement, bandwidth extension under low-voltage (3.4 V) operation, and chip thermal management, the authors analyze state-of-the-art DPAs published in recent years. Key innovations including dynamic power division technique, third order intermodulation (IM3) cancellation technology, and compact output combiners are comparatively studied. Using 5G NR signals, the critical performance of the latest reported PA such as maximum linear power, back-off efficiency, bandwidth, and operating voltage are quantitatively investigated. The measurement results demonstrated that the best performance in recent DPAs achieved high linear power of 31 dBm with 34% PAE and 30 dBm with 31% PAE at the N78 and N77 bands, respectively. The corresponding adjacent channel leakage ratios (ACLRs) were lower than −36.5 dBc without digital pre-distortion (DPD). This review provides a comprehensive understanding of the latest advancements and future directions in highly efficient and linear DPA designs for 5G handset front-end modules. Full article
(This article belongs to the Special Issue IC Design Techniques for Power/Energy-Constrained Applications)
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16 pages, 3903 KiB  
Article
A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application
by Xianfeng Que, Jun Li and Yanjie Wang
Electronics 2024, 13(10), 1882; https://doi.org/10.3390/electronics13101882 - 11 May 2024
Cited by 4 | Viewed by 2195
Abstract
This article presents a new broadband three-way series Doherty power amplifier (DPA) topology, which enables a broadband output power back-off (OBO) efficiency enhancement of up to 10 dB or higher. The proposed DPA topology achieves Doherty load modulation and three-way power combining through [...] Read more.
This article presents a new broadband three-way series Doherty power amplifier (DPA) topology, which enables a broadband output power back-off (OBO) efficiency enhancement of up to 10 dB or higher. The proposed DPA topology achieves Doherty load modulation and three-way power combining through a transformer, which requires only a low coupling factor, thus facilitating its implementation in double-sided PCBs or monolithic microwave integrated circuit (MMIC) processes. The design equations for the proposed DPA topology are proposed and analyzed in detail. A proof-of-concept PA at the 2.1–2.8 GHz band using commercial GaN transistors was designed and fabricated to validate the proposed concept. Within the operating frequency band, it achieves a saturated output power (Psat) of 44.5–46.5 dBm with a peak drain efficiency (DE) of 60–72%, and 43–52% DE at 10 dB OBO. Moreover, under a 20 MHz long-term evolution (LTE)-modulated signal, the PA demonstrates a 36.8–37.5 dBm average output power (Pavg) and 47–53% average drain efficiency (DEavg). Notably, the adjacent channel leakage ratio (ACLR) is as low as −35–−28.2 dBc without any digital predistortion (DPD). Full article
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21 pages, 6976 KiB  
Article
Multiphase Interpolating Digital Power Amplifiers for TX Beamforming
by Zhidong Bai, Wen Yuan, Ali Azam and Jeffrey S. Walling
Chips 2022, 1(1), 30-50; https://doi.org/10.3390/chips1010004 - 26 May 2022
Cited by 3 | Viewed by 3362
Abstract
This paper presents a four-channel beamforming TX implemented in 65 nm CMOS. Each beamforming TX is comprised of a C-2C split-array multiphase switched-capacitor power amplifier (SAMP-SCPA). This is the first use of multiphase interpolation (MPI) for beam steering. This technique is ideal for [...] Read more.
This paper presents a four-channel beamforming TX implemented in 65 nm CMOS. Each beamforming TX is comprised of a C-2C split-array multiphase switched-capacitor power amplifier (SAMP-SCPA). This is the first use of multiphase interpolation (MPI) for beam steering. This technique is ideal for low-frequency beamforming and MIMO, as it does not require passive or LO-based phase shifters. The SCPA is ideal for use as the core element since it can perform frequency translation and data conversion, and drive an output at high power and efficiency in a compact die area. A prototype four-element beamforming TX, occupying 2mm×2.5mm, can achieve a peak output power of 24.4 dBm with a peak system efficiency (SE) of 24%, while achieving <1 phase resolution and <1 dB gain error. When transmitting a 15 MHz, 64-QAM long-term evolution (LTE) signal it outputs 18.4 dBm at 14% SE with a measured adjacent channel leakage ratio (ACLR) of <30 dBc and an error vector magnitude (EVM) of 3.27% RMS at 1.75 GHz. A synthesized beam pattern based on measured results from a single die achieves <0.32 RMS beam angle error and <0.1 dB RMS beam amplitude error. Full article
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