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Keywords = deuterium high pressure anneal

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6 pages, 1652 KB  
Article
Impact of Iterative Deuterium Annealing in Long-Channel MOSFET Performance
by Dong-Hyun Wang, Ja-Yun Ku, Dae-Han Jung, Khwang-Sun Lee, Woo Cheol Shin, Byung-Do Yang and Jun-Young Park
Materials 2022, 15(5), 1960; https://doi.org/10.3390/ma15051960 - 7 Mar 2022
Cited by 12 | Viewed by 4667
Abstract
In contrast to conventional forming gas annealing (FGA), high-pressure deuterium annealing (HPD) shows a superior passivation of dangling bonds on the Si/SiO2 interface. However, research detailing the process optimization for HPD has been modest. In this context, this paper demonstrates the iterative [...] Read more.
In contrast to conventional forming gas annealing (FGA), high-pressure deuterium annealing (HPD) shows a superior passivation of dangling bonds on the Si/SiO2 interface. However, research detailing the process optimization for HPD has been modest. In this context, this paper demonstrates the iterative impact of HPD for the better fabrication of semiconductor devices. Long-channel gate-enclosed FETs are fabricated as a test vehicle. After each cycle of the annealing, device parameters are extracted and compared depending on the number of the HPD. Based on the results, an HPD condition that maximizes on-state current (ION) but minimizes off-state current (IOFF) can be provided. Full article
(This article belongs to the Topic Inorganic Thin Film Materials)
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9 pages, 3463 KB  
Article
Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory
by Jun-Kyo Jeong, Jae-Young Sung, Woon-San Ko, Ki-Ryung Nam, Hi-Deok Lee and Ga-Won Lee
Micromachines 2021, 12(11), 1401; https://doi.org/10.3390/mi12111401 - 15 Nov 2021
Cited by 6 | Viewed by 4547
Abstract
In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with [...] Read more.
In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability. Full article
(This article belongs to the Special Issue Miniaturized Memory Devices)
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8 pages, 2956 KB  
Article
High Pressure Deuterium Passivation of Charge Trapping Layer for Nonvolatile Memory Applications
by Jae-Young Sung, Jun-Kyo Jeong, Woon-San Ko, Jun-Ho Byun, Hi-Deok Lee and Ga-Won Lee
Micromachines 2021, 12(11), 1316; https://doi.org/10.3390/mi12111316 - 27 Oct 2021
Cited by 5 | Viewed by 4214
Abstract
In this study, the deuterium passivation effect of silicon nitride (Si3N4) on data retention characteristics is investigated in a Metal-Nitride-Oxide-Silicon (MNOS) memory device. To focus on trap passivation in Si3N4 as a charge trapping layer, deuterium [...] Read more.
In this study, the deuterium passivation effect of silicon nitride (Si3N4) on data retention characteristics is investigated in a Metal-Nitride-Oxide-Silicon (MNOS) memory device. To focus on trap passivation in Si3N4 as a charge trapping layer, deuterium (D2) high pressure annealing (HPA) was applied after Si3N4 deposition. Flat band voltage shifts (ΔVFB) in data retention mode were compared by CV measurement after D2 HPA, which shows that the memory window decreases but charge loss in retention mode after program is suppressed. Trap energy distribution based on thermal activated retention model is extracted to compare the trap density of Si3N4. D2 HPA reduces the amount of trap densities in the band gap range of 1.06–1.18 eV. SIMS profiles are used to analyze the D2 profile in Si3N4. The results show that deuterium diffuses into the Si3N4 and exists up to the Si3N4-SiO2 interface region during post-annealing process, which seems to lower the trap density and improve the memory reliability. Full article
(This article belongs to the Special Issue Miniaturized Memory Devices)
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