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Keywords = deadzone-compensated frequency detector

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13 pages, 7428 KB  
Article
Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology
by Ligong Sun, Yixin Luo, Zhiyao Deng, Jinchan Wang and Bo Liu
Electronics 2024, 13(18), 3586; https://doi.org/10.3390/electronics13183586 - 10 Sep 2024
Cited by 3 | Viewed by 2467
Abstract
This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) [...] Read more.
This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs. Full article
(This article belongs to the Section Circuit and Signal Processing)
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16 pages, 1618 KB  
Article
A Referenceless Digital CDR with a Half-Rate Jitter-Tolerant FD and a Multi-Bit Decimator
by Jaekwon Kim, Youngjun Ko, Jahoon Jin, Jaehyuk Choi and Jung-Hoon Chun
Electronics 2022, 11(4), 537; https://doi.org/10.3390/electronics11040537 - 11 Feb 2022
Cited by 1 | Viewed by 4586
Abstract
A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Additionally, we proposed a multi-bit decimator circuit [...] Read more.
A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Additionally, we proposed a multi-bit decimator circuit that losslessly down-samples up/down data from a phase detector to reduce the recovered clock jitter. The down-sampled multi-bit phase information is processed by a digital loop filter to adjust the phase of the recovered clock. Fabricated in a 28-nm CMOS technology, the test chip achieves a power efficiency of 1.3 pJ/bit at 10 Gb/s. Full article
(This article belongs to the Section Circuit and Signal Processing)
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