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16 pages, 361 KiB

Open AccessArticle

Di-Forcing Polynomials for Cyclic Ladder Graphs CL_n

by Yantong Wang

Mathematics 2023, 11(16), 3598; https://doi.org/10.3390/math11163598 - 20 Aug 2023

Cited by 3 | Viewed by 1417

The cyclic ladder graph

C L_{n}

is the Cartesian product of cycles

C_{n}

and paths

P_{2}

, that is

C L_{n} = C_{n} \times P_{2}

(n \geq 3)

. The di-forcing polynomial of [...] Read more.

The cyclic ladder graph

C L_{n}

is the Cartesian product of cycles

C_{n}

and paths

P_{2}

, that is

C L_{n} = C_{n} \times P_{2}

(n \geq 3)

. The di-forcing polynomial of

C L_{n}

is a binary enumerative polynomial of all perfect matching forcing and anti-forcing numbers. In this paper, we derive recursive formulas for the di-forcing polynomial of cyclic ladder graph

C L_{n}

by classifying and counting the matching cases of the associated edges of a given vertex, from which we obtain the number of perfect matching, the forcing and anti-forcing polynomials, and the generating function and by computing some di-forcing polynomials of the lower order

C L_{n}

. Full article

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21 pages, 2170 KiB

Open AccessArticle

Reconfigurable Logic Controller—Direct FPGA Synthesis Approach

by Adam Milik, Marcin Kubica and Dariusz Kania

Appl. Sci. 2021, 11(18), 8515; https://doi.org/10.3390/app11188515 - 14 Sep 2021

Cited by 9 | Viewed by 3481

Abstract

Programmable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity. The classic approach, based on programmatic serial-cyclic execution, results in an unacceptable extension of response time. To overcome long response time massive parallel program execution is proposed. It utilize direct in hardware program implementation in field programmable devices. The paper brings a formal method of representing control programs using flow graphs and enabling single cycle computations. The developed method accepts ladder diagrams (LD) and sequential function charts (SFC), according to IEC61131-3 standard requirements. It is capable of handling logic and arithmetic computations, enabling its hardware mapping. The intermediate form is optimized using flow graph representation and BDDs for analyzing logic dependencies. The BDD representation of logic dependencies enables direct mapping to lookup tables of a selected FPGA family. All the above steps deliver high-performance and direct hardware implementation of the control program given by standard languages. The controller response time is short, predictable, and independent from logic conditions during program execution. Full article

(This article belongs to the Special Issue Programmable Logic Controllers)

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