Search Results (4)

The SiGe/Si multilayer is a critical component for fabricating stacked Si channel structures for next-generation three-dimensional (3D) logic and 3D dynamic random-access memory (3D-DRAM) devices. Achieving these structures necessitates highly selective SiGe etching. Herein, CF₄/O₂ and CF₄/N₂ gas chemistries were employed to elucidate and enhance the selective etching mechanism. To clarify the contribution of radicals to the etching process, a nonconducting plate (roof) was placed just above the samples in the plasma chamber to block ion bombardment on the sample surface. The CF₄/N₂ gas chemistries demonstrated superior etch selectivity and profile performance compared with the CF₄/O₂ gas chemistries. When etching was performed using CF₄/O₂ chemistry, the SiGe etch rate decreased compared to that obtained with pure CF₄. This reduction is attributed to surface oxidation induced by O₂, which suppressed the etch rate. By minimizing the ion collisions on the samples with the roof, higher selectivity, and a better etch profile were obtained even in the CF₄/N₂ gas chemistries. Under high-N₂-flow conditions, X-ray photoelectron spectroscopy revealed increased surface concentrations of GeF_x species and confirmed the presence of Si–N bond, which inhibited Si etching by fluorine radicals. A higher concentration of GeF_x species enhanced SiGe layer etching, whereas Si–N bonds inhibited etching on the Si layer. The passivation of the Si layer and the promotion of adhesion of etching species such as F on the SiGe layer are crucial for highly selective etching in addition to etching with pure radicals. This study provides valuable insights into the mechanisms governing selective SiGe etching, offering practical guidance for optimizing fabrication processes of next-generation Si channel and complementary field-effect transistor (CFET) devices. Full article

We systematically investigate the combined impact of process variation effects (PVEs), metal gate work function fluctuation (WKF), and random dopant fluctuation (RDF) on the key electrical characteristics of sub-1-nm technology node gate-all-around silicon nanosheet complementary field-effect transistors (GAA Si NS CFETs). Through comprehensive statistical analysis, we reveal that the interplay of these intrinsic and extrinsic sources of variability induces significant fluctuations in the off-state leakage current across both N-/P-FETs in GAA Si NS CFETs. The sensitivity to process-induced variability is found to be particularly pronounced in the P-FETs, primarily due to the enhanced parasitic conduction associated with the bottom nanosheet channel. Given the correlated nature of PVE, WKF, and RDF factors, the statistical sum (RSD) of the fluctuation for each factor is overestimated by less than 50% compared with the simultaneous fluctuations of PVE, WKF, and RDF factors. Furthermore, although the static power dissipation remains relatively small compared to dynamic and short-circuit power components, it exhibits the largest relative fluctuation (approximately 82.1%), posing critical challenges for low-power circuit applications. These findings provide valuable insights into the variability-aware design and optimization of GAA NS CFET device fabrication processes, as well as the development of robust and reliable CFET-based integrated circuits for next-generation technology nodes. Full article

The complementary field-effect transistor (CFET) with N-type FET (NFET) stacked on P-type FET (PFET) is a promising device structure based on gate-all-around FET (GAAFET). Because of the high-density stacked structure, the self-heating effect (SHE) becomes more and more severe. Buried thermal rail (BTR) technology on top of the buried power rail (BPR) process is proposed to improve heat dissipation. Through a systematical 3D Technology Computer Aided Design (TCAD) simulation, compared to traditional CFET and CFET with BPR only, the thermal resistance ($R_{th}$) of CFET can be significantly reduced with BTR technology, while the drive capability is also improved. Furthermore, based on the proposed BTR technology, different power delivery structures of top-VDD–top-VSS (TDTS), bottom-VDD–bottom-VSS (BDBS), and bottom-VDD–top-VSS (BDTS) were investigated in terms of electrothermal and parasitic characteristics. The $R_{th}$ of the BTR-BDTS structure is decreased by 5% for NFET and 9% for PFET, and the $I_{on}$ is increased by 2% for NFET and 7% for PFET. Full article

We have demonstrated the method of threshold voltage (V_T) adjustment by controlling Ge content in the SiGe p-channel of N1 complementary field-effect transistor (CFET) for conquering the work function metal (WFM) filling issue on highly scaled MOSFET. Single WFM shared gate N1 CFET was used to study and emphasize the V_T tunability of the proposed Ge content method. The result reveals that the Ge mole fraction influences V_TP of 5 mV/Ge%, and a close result can also be obtained from the energy band configuration of Si_1-xGe_x. Additionally, the single WFM shared gate N1 CFET inverter with V_T adjusted by the Ge content method presents a well-designed voltage transfer curve, and its inverter transient response is also presented. Furthermore, the designed CFET inverter is used to construct a well-behaved 6T-SRAM with a large SNM of ~120 mV at V_DD of 0.5 V. Full article