Search Results (2)

In semiconductor manufacturing, the final testing phase is critical for ensuring chip quality and operational efficiency. Accurate yield prediction at this stage optimizes testing workflows, boosts production efficiency, and enhances quality control. However, existing research primarily focuses on wafer-level yield prediction, leaving the unique challenges of final testing—such as test condition variability and complex failure patterns—insufficiently addressed. This is especially critical for Radio Frequency Front-End (RFFE) chips, where high precision is essential, highlighting the need for a specialized prediction approach. In our study, a rigorous RF correlation parameter selection process was applied, leveraging metrics such as Spearman’s correlation coefficient and variance inflation factors to identify key RF-related features, such as multiple frequency-point PAE measurements and other critical electrical parameters, that directly influence final test yield. To overcome the limitations of traditional methods, this study proposes a multistrategy dynamic weighted fusion model for yield prediction. The proposed approach combines convolutional neural networks (CNNs) and long short-term memory (LSTM) networks with sliding window averaging to capture both local features and long-term dependencies in RFFE test data, while employing a learnable weighting mechanism to dynamically fuse outputs from multiple submodels for enhanced prediction accuracy. It further incorporates incremental training to adapt to shifting production conditions and utilizes principal component analysis (PCA) in data preprocessing to reduce dimensionality and address multicollinearity. Evaluated on a dataset of over 24 million RFFE chips, the proposed model achieved a Mean Absolute Error (MAE) below 0.84% and a Root Mean Square Error (RMSE) of 1.24%, outperforming single models by reducing MAE and RMSE by 7.69% and 13.29%, respectively. These results demonstrate the high accuracy and adaptability of the fusion model in predicting semiconductor final test yield. Full article

GNSS receivers with multi-system and multi-frequency capabilities allow more reliable positioning, especially in challenging environments. However, increased available systems and signals lead to hardware resource allocation problems. This issue escalates when ten correlators per tracked GNSS signal are used. Moreover, the communication interface between the PL and the PS affects the time complexity and challenges the capability of the maximum number of tracking channels. This paper presents the GOOSE v2, a MPSoC-based GNSS receiver, which is composed of a quad-band (L1, L2, L5/E5 and S band) RFFE and baseband digital signal processing. The SoC includes a quad-core 64-bit processor and an FPGA. The on-chip communication between the processors and the FPGA offers high bandwidth, significantly reducing the time complexity. The preliminary evaluation of this new receiver platform shows that, in addition to the legacy signals, it supports NavIC L5 and S-band signals. Furthermore, this receiver closes the tracking loops faster than its legacy version (GOOSE v1), opening the door to implementing more complex algorithms requiring higher time complexity. Full article