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18 pages, 688 KB

Open AccessArticle

An Optimized Hardware Implementation of a Non-Adjacent Form Algorithm Using Radix-4 Multiplier for Binary Edwards Curves

by Asher Sajid, Omar S. Sonbul, Muhammad Rashid, Muhammad Arif and Amar Y. Jaffar

Appl. Sci. 2024, 14(1), 54; https://doi.org/10.3390/app14010054 - 20 Dec 2023

Cited by 1 | Viewed by 1978

Abstract

Binary Edwards Curves (BEC) play a pivotal role in modern cryptographic processes and applications, offering a combination of robust security as well as computational efficiency. For robust security, this article harnesses the inherent strengths of BEC for the cryptographic point multiplication process by utilizing the Non-Adjacent Form (NAF) algorithm. For computational efficiency, a hardware architecture for the NAF algorithm is proposed. Central to this architecture is an Arithmetic Logic Unit (ALU) designed for streamlined execution of essential operations, including addition, squaring, and multiplication. One notable innovation in our ALU design is the integration of multiplexers, which maximize ALU efficiency with minimal additional hardware requirements. Complementing the optimized ALU, the proposed architecture incorporates a radix-4 multiplier, renowned for its efficiency in both multiplication and reduction. It eliminates resource-intensive divisions, resulting in a substantial boost to overall computational speed. The architecture is implemented on Xilinx Virtex series Field-Programmable Gate Arrays (FPGAs). It achieves throughput-to-area ratios of 14.819 (Virtex-4), 25.5 (Virtex-5), 34.58 (Virtex-6), and 37.07 (Virtex-7). These outcomes underscore the efficacy of our optimizations, emphasizing an equilibrium between computational performance and area utilization. Full article

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17 pages, 2355 KB

Open AccessArticle

Power/Area-Efficient ECC Processor Implementation for Resource-Constrained Devices

by Medien Zeghid, Anissa Sghaier, Hassan Yousif Ahmed and Osman Ahmed Abdalla

Electronics 2023, 12(19), 4110; https://doi.org/10.3390/electronics12194110 - 30 Sep 2023

Cited by 3 | Viewed by 2190

Abstract

The use of resource-constrained devices is rising nowadays, and these devices mostly operate with sensitive data. Consequently, security is a key issue for these devices. In this paper, we propose a compact ECC (elliptic curve cryptography) architecture for resource-constrained devices based on López–Dahab (LD) projective point arithmetic operations on GF(2^m). To achieve an efficient area-power hardware ECC implementation, an efficient digit-serial multiplier is developed. The proposed multiplier is built on a Bivariate Polynomial Basis representation and a modified Radix-n Interleaved Multiplication (mRnIM) method (for area and power complexities reduction). Furthermore, the LD-Montgomery point multiplication algorithm is adjusted for accurate scheduling in the compact ECC architecture to eliminate data reliance and improve signal management. Meanwhile, the area complexity is reduced by reuse of resources, and clock gating and asynchronous counter are exploited to reduce the power consumption. Finally, the proposed compact ECC architecture is implemented over GF(2^m) (m = 163, 233, 283, 409, and 571) on Xilinx FPGAs’ (Field-Programmable Gate Array) Virtex 5, Virtex 6, and Virtex 7, showing that the efficiency of this design outperforms to date when compared to reported works individually. It utilizes less area and consumes low power. The FPGA results clearly demonstrate that the proposed ECC architecture is appropriate for constraint-resources devices. Full article

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21 pages, 721 KB

Open AccessArticle

A Crypto Accelerator of Binary Edward Curves for Securing Low-Resource Embedded Devices

by Asher Sajid, Omar S. Sonbul, Muhammad Rashid, Atif Raza Jafri, Muhammad Arif and Muhammad Yousuf Irfan Zia

Appl. Sci. 2023, 13(15), 8633; https://doi.org/10.3390/app13158633 - 26 Jul 2023

Cited by 3 | Viewed by 2021

Abstract

This research presents a novel binary Edwards curve (BEC) accelerator designed specifically for resource-constrained embedded systems. The proposed accelerator incorporates the fixed window algorithm, a two-stage pipelined architecture, and the Montgomery radix-4 multiplier. As a result, it achieves remarkable performance improvements in throughput and resource utilization. Experimental results, conducted on various Xilinx Field Programmable Gate Arrays (FPGAs), demonstrate impressive throughput/area ratios observed for

G F (2^{233})

. The achieved ratios for Virtex-4, Virtex-5, Virtex-6, and Virtex-7 are 12.2, 19.07, 36.01, and 38.39, respectively. Furthermore, the processing time for one-point multiplication on a Virtex-7 platform is 15.87 µs. These findings highlight the effectiveness of the proposed accelerator for improved throughput and optimal resource utilization. Full article

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19 pages, 515 KB

Open AccessArticle

A Hybrid Approach for Efficient and Secure Point Multiplication on Binary Edwards Curves

by Asher Sajid, Omar S. Sonbul, Muhammad Rashid and Muhammad Yousuf Irfan Zia

Appl. Sci. 2023, 13(9), 5799; https://doi.org/10.3390/app13095799 - 8 May 2023

Cited by 10 | Viewed by 2558

Abstract

The focus of this article is to present a novel crypto-accelerator architecture for a resource-constrained embedded system that utilizes elliptic curve cryptography (ECC). The architecture is built around Binary Edwards curves (BEC) to provide resistance against simple power analysis (SPA) attacks. Furthermore, the [...] Read more.

G F (2^{m})

. This includes the use of a Montgomery radix-2 multiplier and the projective coordinate hybrid algorithm (combination of Montgomery ladder and double and add algorithm) for scalar multiplication. A two-stage pipelined architecture is employed to enhance throughput. The design is modeled in Verilog HDL and verified using Vivado and ISE design suites from Xilinx. The obtained results demonstrate that the proposed BEC accelerator offers significant performance improvements compared to existing solutions. The obtained throughput over area ratio for

G F (2^{233})

on Virtex-4, Virtex-5, Virtex-6, and Virtex-7 Xilinx FPGAs are 9.43, 14.39, 26.14, and 28.79, respectively. The computation time required for a single point multiplication operation on the Virtex-7 device is 19.61 µs. These findings indicate that the proposed architecture has the potential to address the challenges posed by resource-constrained embedded systems that require high throughput and efficient use of available resources. Full article

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16 pages, 416 KB

Open AccessArticle

Low-Cost, Low-Power FPGA Implementation of ED25519 and CURVE25519 Point Multiplication

by Mohamad Ali Mehrabi and Christophe Doche

Information 2019, 10(9), 285; https://doi.org/10.3390/info10090285 - 14 Sep 2019

Cited by 31 | Viewed by 8020

Abstract

Twisted Edwards curves have been at the center of attention since their introduction by Bernstein et al. in 2007. The curve ED25519, used for Edwards-curve Digital Signature Algorithm (EdDSA), provides faster digital signatures than existing schemes without sacrificing security. The CURVE25519 is a Montgomery curve that is closely related to ED25519. It provides a simple, constant time, and fast point multiplication, which is used by the key exchange protocol X25519. Software implementations of EdDSA and X25519 are used in many web-based PC and Mobile applications. In this paper, we introduce a low-power, low-area FPGA implementation of the ED25519 and CURVE25519 scalar multiplication that is particularly relevant for Internet of Things (IoT) applications. The efficiency of the arithmetic modulo the prime number

2^{255} - 19

, in particular the modular reduction and modular multiplication, are key to the efficiency of both EdDSA and X25519. To reduce the complexity of the hardware implementation, we propose a high-radix interleaved modular multiplication algorithm. One benefit of this architecture is to avoid the use of large-integer multipliers relying on FPGA DSP modules. Full article

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