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Keywords = FBMMC

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23 pages, 5075 KB  
Article
Fast DC Fault Current Suppression and Fault Ride-Through in Full-Bridge MMCs via Reverse SM Capacitor Discharge
by Munif Nazmus Sakib, Sahar Pirooz Azad and Mehrdad Kazerani
Energies 2022, 15(13), 4595; https://doi.org/10.3390/en15134595 - 23 Jun 2022
Viewed by 2345
Abstract
In the event of a DC side fault in modular multilevel converters (MMCs), the fault current contributions are initially made by submodule (SM) capacitor discharge, which occurs before the fault is detected, followed by the AC side contribution to the DC side fault. [...] Read more.
In the event of a DC side fault in modular multilevel converters (MMCs), the fault current contributions are initially made by submodule (SM) capacitor discharge, which occurs before the fault is detected, followed by the AC side contribution to the DC side fault. While the AC side currents can be regulated using fault blocking SMs, the initial discharge of the SM capacitors results in high DC fault currents, which can take several milliseconds to be brought under control. This paper presents a method to actively control the rate of rise of the DC fault current by regulating the discharge of SM capacitors and accelerating the suppression of fault current oscillations during fault ride-through (FRT) in a full-bridge (FB)-MMC system. In the proposed method, the discharge direction of the FBSM capacitors is reversed following the detection of a DC side fault, which leads to a reversal in the fault current direction and a fast drop-off towards the zero-crossing. Immediately after the zero-crossing of the DC fault current, the DC fault is cleared by adjusting the arm voltage references and operating the MMC as a static synchronous compensator (STATCOM) to provide voltage support to the AC grid. The proposed control scheme provides faster fault current suppression, more effective SM capacitor voltage regulation, low AC side and MMC arm current transient peaks, and an overall superior DC-FRT performance compared to methods in which the conventional fault ride-through operation is initiated immediately upon DC fault detection. Full article
(This article belongs to the Section F3: Power Electronics)
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15 pages, 3205 KB  
Article
Hybrid HVDC (H2VDC) System Using Current and Voltage Source Converters
by José Rafael Lebre, Paulo Max Maciel Portugal and Edson Hirokazu Watanabe
Energies 2018, 11(6), 1323; https://doi.org/10.3390/en11061323 - 23 May 2018
Cited by 14 | Viewed by 6055
Abstract
This paper presents an analysis of a new high voltage DC (HVDC) transmission system, which is based on current and voltage source converters (CSC and VSC) in the same circuit. This proposed topology is composed of one CSC (rectifier) and one or more [...] Read more.
This paper presents an analysis of a new high voltage DC (HVDC) transmission system, which is based on current and voltage source converters (CSC and VSC) in the same circuit. This proposed topology is composed of one CSC (rectifier) and one or more VSCs (inverters) connected through an overhead transmission line in a multiterminal configuration. The main purpose of this Hybrid HVDC (H2VDC), as it was designed, is putting together the best benefits of both types of converters in the same circuit: no commutation failure and system’s black start capability in the VSC side, high power converter capability and low cost at the rectifier side, etc. A monopole of the H2VDC system with one CSC and two VSCs—here, the VSC is the Modular Multilevel Converter (MMC) considered with full-bridge submodules—in multiterminal configuration is studied. The study includes theoretical analyses, development of the CSC and VSCs control philosophies and simulations. The H2VDC system’s behavior is analyzed by computational simulations considering steady-state operation and short-circuit conditions at the AC and DC side. The obtained results and conclusions show a promising system for very high-power multiterminal HVDC transmission. Full article
(This article belongs to the Special Issue Power Electronics and Power Quality)
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