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Journal = Microelectronics

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29 pages, 8225 KB  
Review
Quantum Biosensors on Chip: A Review from Electronic and Photonic Integrated Circuits to Future Integrated Quantum Photonic Circuits
by Yasaman Torabi, Shahram Shirani and James P. Reilly
Microelectronics 2025, 1(2), 5; https://doi.org/10.3390/microelectronics1020005 - 22 Oct 2025
Viewed by 597
Abstract
Quantum biosensors offer a promising route to overcome the sensitivity and specificity limitations of conventional biosensing technologies. Their ability to detect biochemical signals at extremely low concentrations makes them strong candidates for next-generation sensing systems. This paper reviews the current state of quantum [...] Read more.
Quantum biosensors offer a promising route to overcome the sensitivity and specificity limitations of conventional biosensing technologies. Their ability to detect biochemical signals at extremely low concentrations makes them strong candidates for next-generation sensing systems. This paper reviews the current state of quantum biosensors and discusses their future implementation in chip-scale platforms that combine microelectronic and photonic technologies. It covers key quantum biosensing approaches including quantum dots (QDs), and nitrogen-vacancy (NV) centers. This paper also considers their potential compatibility with electronic integrated circuits (EICs), photonic integrated circuits (PICs) and integrated quantum photonic (IQP) systems for future biosensing applications. To our knowledge, this is the first review to systematically connect quantum biosensing technologies with the development of microelectronic and photonic chip-based devices. The goal is to clarify the technological trajectory toward compact, scalable, and high-performance quantum biosensing systems. Full article
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18 pages, 3294 KB  
Article
Compact and Efficient First-Order All-Pass Filter in Voltage Mode
by Khushbu Bansal, Bhartendu Chaturvedi and Jitendra Mohan
Microelectronics 2025, 1(1), 4; https://doi.org/10.3390/microelectronics1010004 - 20 Sep 2025
Viewed by 458
Abstract
This paper presents a new compact and efficient first-order all-pass filter in voltage mode based on a second-generation voltage conveyor, along with two resistors, and a capacitor. This circuit delivers an all-pass response from the low-impedance node and eliminates the need for a [...] Read more.
This paper presents a new compact and efficient first-order all-pass filter in voltage mode based on a second-generation voltage conveyor, along with two resistors, and a capacitor. This circuit delivers an all-pass response from the low-impedance node and eliminates the need for a voltage buffer in cascading configurations. A thorough non-ideal analysis, accounting for parasitic impedances and the non-ideal gains of the active module, shows negligible effects on the filter performance. Furthermore, a sensitivity analysis with respect to both active and passive components further validates the robustness of the design. The proposed all-pass filter is validated by Cadence PSPICE simulations, utilizing 0.18 µm TSMC CMOS process parameter and ±0.9 V power supply, including Monte Carlo analysis and temperature variations. Additionally, experimental validation is carried out using commercially available IC AD844, showing great consistency between theoretical and experimental results. Resistor-less realization of the proposed filter provides tunability feature. A quadrature sinusoidal oscillator is presented to validate the proposed structure. The introduced circuit provides a simple and effective solution for low-power and compact analog signal processing applications. Full article
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21 pages, 4543 KB  
Article
Back-Gate Bias Effects on Breakdown Voltage in Lateral Silicon-on-Insulator Power Devices
by Viswanathan Naveen Kumar, Mohammed Tanvir Quddus, Zeinab Ramezani, Mihir Mudholkar and Prasad Venkatraman
Microelectronics 2025, 1(1), 3; https://doi.org/10.3390/microelectronics1010003 - 20 Sep 2025
Viewed by 405
Abstract
The influence of back-gate (BG) bias on the breakdown voltage (BV) of lateral SOI power devices is investigated using TCAD simulations. A reference SOI-LDMOS structure with BVREF = 73.7 V, optimized based on RESURF and charge-sharing principles, is selected as the baseline for [...] Read more.
The influence of back-gate (BG) bias on the breakdown voltage (BV) of lateral SOI power devices is investigated using TCAD simulations. A reference SOI-LDMOS structure with BVREF = 73.7 V, optimized based on RESURF and charge-sharing principles, is selected as the baseline for analysis. The BV response to BG bias is shown to fall into three distinct regimes: (i) a linear decrease with increasing magnitude of negative BG bias (−65 V ≤ VG2 ≤ −5 V), (ii) an invariant region where the BV reaches its maximum value (−5 V ≤ VG2 ≤ +10 V), and (iii) a sharp reduction under increasing magnitude of positive BG bias (+10 V ≤ VG2 ≤ +65 V). Qualitative analysis of impact ionization and charge distribution confirms that inversion, depletion, and accumulation conditions in the drift region govern these behaviors. Furthermore, parametric variations in drift doping, drift thickness, and buried oxide thickness reveal significant shifts in the optimum design window, with the buried oxide thickness emerging as a critical factor for ensuring robustness of BV under BG bias. These results provide valuable design guidelines for achieving stable high-voltage performance in practical SOI-LDMOS power devices. Full article
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19 pages, 1310 KB  
Review
A Survey of Machine and Deep Learning Techniques in Analog Integrated Circuit Layout Synthesis
by Ricardo M. F. Martins
Microelectronics 2025, 1(1), 2; https://doi.org/10.3390/microelectronics1010002 - 1 Aug 2025
Cited by 1 | Viewed by 1458
Abstract
Automatic techniques for analog integrated circuit layout design have been proposed in the literature for over four decades. However, as analog design moves into deep nanometer integration nodes, the increasing number of design rules, the influence of layout-dependent effects, congestion, and the impact [...] Read more.
Automatic techniques for analog integrated circuit layout design have been proposed in the literature for over four decades. However, as analog design moves into deep nanometer integration nodes, the increasing number of design rules, the influence of layout-dependent effects, congestion, and the impact of parasitic structures constantly challenges existing automatic layout generation techniques and keeps the pressure on for further improvement. At the time of writing, no automatic tool or flow has been established in the industrial environment, resulting in a time-consuming and difficult-to-reuse design process. However, very recently, machine and deep learning techniques started to offer solutions for problems not dealt with in the previous generation of automatic layout tools and are reshaping analog design automation. Therefore, this paper conducts a review of the most recent analog integrated circuit automatic layout techniques powered by machine and deep learning methods, covering placement, routing, and trends on post-layout performance estimation, as well as providing an actual, complete, and comprehensive guide for circuit designers and design automation developers. Full article
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3 pages, 231 KB  
Editorial
Microelectronics—An Open-Access Journal for Advancing Microelectronics Technologies
by M. Jamal Deen
Microelectronics 2025, 1(1), 1; https://doi.org/10.3390/microelectronics1010001 - 4 Jun 2025
Viewed by 3069
Abstract
The field of microelectronics is at the heart of modern technological progress, driving innovations that span computing, communications, healthcare, and energy [...] Full article
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