High-Efficiency Reconfigurable CMOS RF-to-DC Converter System for Ultra-Low-Power Wireless Sensor Nodes with Efficient MPPT Circuitry

Abstract

This paper presents a novel CMOS RF-to-DC converter for ultra-low-power wireless sensor nodes powered by RF wireless power transfer. The proposed converter achieves 10% higher power conversion efficiency than a conventional rectifier, with only a 1% increase in power consumption. The system employs a reconfigurable Dickson topology, operates on the unlicensed 868 MHz ISM band, and includes a built-in power-efficient MPPT system architecture. Experimental measurements show a maximum power conversion efficiency of 55% in the power range from −22 dBm to 0 dBm, with a power sensitivity of −22 dBm for a DC output voltage of 2.4 V. The proposed converter offers a promising solution for efficient wireless power transfer and energy harvesting in ultra-low-power wireless sensor nodes.

1. Introduction

Wireless Sensor Nodes (WSNs) are becoming more widespread due to their increasing complexity and ability to perform sensing, data analysis, and communication [1]. However, powering these nodes efficiently and effectively presents a challenge. Conventional nodes typically rely on batteries, which can lead to increased costs, maintenance requirements, and difficulties in miniaturization [2]. Battery-free devices are becoming increasingly popular among engineers as a convenient option, especially in applications such as high-temperature or hazardous locations, wearable devices, or biomedical applications [3]. For these reasons, designers are showing more interest in RF Wireless Power Transfer (WPT) and energy harvesting (EH) technologies.

RF WPT is gaining attention due to its ability to reach non-visible locations and its widespread availability. Unlike other energy sources, such as photovoltaic and kinetic, which are highly dependent on weather conditions, RF WPT takes advantage of the high prevalence of RF signals and their lower time dependence [4]. However, implementing efficient RF WPT can be complex, and designing a low-input-power RF-to-DC converter is always challenging. Despite the prevalence of RF signals, the available RF power is typically low, making it only possible to power electronic devices with ultra-low power consumption (several microwatts). This limited RF power is due to space path loss and regulations that limit RF power emissions to protect human health [5]. Despite restricted transmission power and space path loss, optimizing the design of RF-to-DC converters for power conversion efficiency (PCE) and power sensitivity can convert received RF power into sufficient electrical power to supply electronic devices [6]. Power sensitivity refers to the minimum RF power required for the converter to start harvesting energy into a storage device. Designers aim to minimize power sensitivity to harvest energy from distant and low-power sources. Various design methods, techniques, and circuit topologies for RF-to-DC converters have been proposed in the literature to achieve optimal power sensitivity performance [7,8,9,10,11].

Many of these papers propose techniques for efficiently biasing the transistors that rectify the low-voltage input signal, with a focus on compensating for the threshold voltage ${\mathrm{V}}_{\mathrm{T}}$ of the gate-source voltage of the transistor, as this directly affects the rectifier’s efficiency. For example, the authors of [12] proposed a self-compensation method that extends the length of the compensating bridges to increase the gate bias offset, while the authors of [13] used a static and dynamic self-compensation technique to decrease the threshold voltage of the rectifying transistors. The authors of [14] report a dual-topology CMOS rectifier with a peak PCE of 78.4% operating at 900 MHz. While these publications have proposed improvements for power sensitivity performance regardless of the RF-to-DC converter topology, they do not consistently contribute to the further optimization of PCE performance when the input-received RF power is increased beyond the power sensitivity. As a result, conventional RF-to-DC converters typically exhibit decreasing PCE performance as input power increases, which can be inefficient in WPT applications that deal with variable power conditions, such as asset tracking tags and over-the-distance wireless battery chargers, where the relative distance between the power transmitter and receiver is not constant [6,15]. To address this problem, several authors have proposed reconfigurable RF-to-DC converter architectures to increase output power and improve the PCE over a wide range of input power levels. For example, the authors of [16] presented a reconfigurable RF-to-DC converter, while the authors of [17] proposed a maximum power point tracking (MPPT) technique to optimize the number of rectifiers in a reconfigurable RF-to-DC converter for high PCE. Similarly, the authors of [18] presented a reconfigurable RF-to-DC converter to improve PCE performance. In [19], the authors describe a RF energy-harvesting system based on a reconfigurable rectifier designed to maintain high PCE over a wide range of input power levels, achieving a maximum PCE of 39% from −22 dBm to −2 dBm. The authors of [20] showcased a solution for MPPT, where they utilized an auxiliary RF rectenna to provide a RF power-dependent reference voltage (Vref). This Vref was then used to harvest the maximum available power from the main rectenna for a range of received RF power from −11 dBm to 3 dBm. The authors of [21] present a novel circuit architecture for a Dickson-based reconfigurable rectifier with a wide power dynamic range, achieving a PDR of 14 dB and a peak PCE of 34.93% operating at 900 MHz.

This work proposes an RF-to-DC converter architecture operating in the 868 MHz ISM band that implements an MPPT system. The MPPT system allows for maximizing the power conversion efficiency of a RF WPT system over a wide range of input power levels that is achieved through a converter with a configurable number of rectifier stages and an innovative open-circuit voltage measurement technique. The result is a cost-effective and silicon area-effective MPPT system that increases the PCE of the system, regardless of the voltage rectifier topology. The system combines reconfigurable voltage rectifiers with indirect monitoring of input-received power using the open-circuit voltage of an unloaded voltage rectifier. This study presents the underlying theory, layout implementation, and experimental results for the CMOS implementation.

This work introduces several innovative aspects, including the following:

• Development of a system-level strategy for correctly biasing the operating point of the RF-to-DC converter, which is a novel concept not commonly found in existing architectures. This strategy focuses on optimizing the output voltage of the rectifier by properly biasing the system, rather than just the rectifier itself. This approach provides a more effective way to maximize power conversion efficiency with no impact on the power sensitivity performance, with negligible impact on circuit complexity and effective die area. The proposed method and guidelines provide a practical solution for achieving optimal performance in RF-to-DC converter architectures.
• Implementation of an innovative ultra-low power voltage measurement technique that uses a simple rectifier to indirectly monitor input-received power, which is a novel concept not commonly found in existing RF-to-DC converter architectures and provides a more accurate and efficient way to optimize power conversion efficiency. This technique uses a very small silicon area, making it a cost-effective solution for practical applications.
• Combination of reconfigurable voltage rectifiers with indirect monitoring of input-received power to create a cost-effective and silicon area-effective MPPT system that increases the PCE of the system, regardless of the voltage rectifier topology. The proposed MPPT system uses an ultra-low power circuit with minimal impact in terms of extra power consumption and effective die area increase, making it a practical solution for energy harvesting applications.

Section 2 describes the architecture of a conventional WPT system. Section 3 explains the proposed MPPT technique and shows experimental results demonstrating the achieved PCE improvement compared to a conventional RF-to-DC converter architecture along with the measurement setup and experimental results. Section 4 provides a summary and discussion of the achieved results.

2. Materials and Methods

Figure 1 shows a simplified and generic block diagram of a WPT RF power conversion system that, in its minimal architecture, comprises the following building blocks:

• The RF power transmitter is responsible for transmitting a maximum RF power in compliance with regulations that ensure human health is not compromised.
• The Matching Network (MN) matches the impedance of the antenna with that of the RF-to-DC converter to optimize the power transfer.
• The RF-to-DC converter rectifies and amplifies the input voltage.
• The storage capacitor ${\mathrm{C}}_{\mathrm{storage}}$ stores the harvested energy.
• The ultra-low-power management system regulates and controls the voltage supplied to the load, which is typically a wireless sensor node.

The reference performance metrics for designing the RF-to-DC converter include the minimum distance ${\mathrm{d}}_{\min }$ to cover between the power transmitter and receiver, the sensitivity power level ${\mathrm{P}}_{\mathrm{RF}\_\min }$, the DC output voltage ${\mathrm{V}}_{\mathrm{DC}}$, the DC output power ${\mathrm{P}}_{\mathrm{DC}\_\min }$, and the operating frequency.

Regarding the minimum distance ${\mathrm{d}}_{\min }$, the System on Chip (SoC) is defined for an application to cover a distance of more than 7 m between the power transmitter and receiver under the following conditions:

• Free-space WPT.
• Unity gain for both transmitter and receiver antennas.
• Transmitted power = 27 dBm.
• Frequency = 868 MHz.

Concerning the sensitivity power level, i.e., the minimum output power $\mathrm{RF}\_\min$ to achieve the minimum distance ${\mathrm{d}}_{\min }$ in the conditions expressed above, the following specifications are set for the RF-to-DC converter:

• ${\mathrm{P}}_{\mathrm{RF}\_\min }$ = −22 dBm = 6.3 $\mathsf{\mu }\mathrm{W}$
• ${\mathrm{PCE}}_{\min }=40\%$

Regarding the DC output voltage ${\mathrm{V}}_{\mathrm{DC}}$ and the minimum DC output power ${\mathrm{P}}_{\mathrm{DC}\_\min }$ to meet the specification of powering other standard components with a typical supply voltage of 1.8 V, the following specifications are set for the RF-to-DC converter:

• Output voltage ${\mathrm{V}}_{\mathrm{DC}\_\mathrm{oc}}$ = 4.8 V (Open Circuit condition).
• Output Voltage ${\mathrm{V}}_{\mathrm{DC}}$ = 2.4 V (at ${\mathrm{I}}_{\mathrm{DC}}$ = 1 $\mathsf{\mu }\mathrm{A}$).
• Min Output Power ${\mathrm{P}}_{\mathrm{DC}\_\min }$ = 2.4 $\mathsf{\mu }\mathrm{W}$ = −26 dBm.

Regarding the operating frequency, the system operates at 868 MHz in the ISM band, which offers a good balance between long-distance WPT and a small antenna form factor. This frequency band allows for the maximum permitted RF power of 27 dBm, resulting in high RF power transmission. Although lower frequencies like 433 MHz have lower free space path loss, the lower power allowed in transmission offsets this advantage, and larger antennas may be required. Higher frequencies like 2.4 GHz offer higher antenna efficiency and better form factor, but the maximum allowed transmitted power is limited to 20 dBm. Choosing the best frequency for WPT involves a trade-off between factors like allowed transmitted power, Free Space Path Loss (FSPL), and WSN size.

3. Results

3.1. MPPT Technique with Reconfigurable RF-to-DC Converter

The performance achieved by the RF-to-DC converter discussed in this work is in good agreement with targeted specifications in terms of sensitivity power level (−22 dBm) and PCE at the sensitivity power level (40%). Indeed, the RF-to-DC converter can still provide a DC output power higher than −26 dBm and, the system meets the required specification of ${\mathrm{d}}_{\min }$ > 7 m.

Figure 2 illustrates the schematic of a conventional three-stage CMOS Dickson rectifier, which comprises a series of cascaded voltage doublers.

The circuit architecture cascades multiple rectifier stages to meet the required power sensitivity and achieve a DC output voltage across a specified load. However, this RF-to-DC converter circuitry achieves maximum PCE performance at only one input power level ${\mathrm{P}}_{\mathrm{RF}}$, which is typically very similar, if not the same, as the sensitivity power level ${\mathrm{P}}_{\mathrm{RF}\_\min }$. In a typical WSN that is self-powered by an RF-to-DC converter, the SoC actively regulates the output DC voltage through the ultra-low power management to maintain a constant value of ${\mathrm{V}}_{\mathrm{ope}}$. This value is usually the maximum voltage that the rectifier devices can handle. As shown in Figure 3, maintaining a constant output voltage ${\mathrm{V}}_{\mathrm{DC}}$ (i.e., ${\mathrm{V}}_{\mathrm{DC}}={\mathrm{V}}_{\mathrm{ope}}$) and the same number of rectifier stages ${\mathrm{N}}_{\mathrm{oS}}$ while increasing the input power ${\mathrm{P}}_{\mathrm{RF}}$ prevents the circuit from operating at its optimal condition for power conversion efficiency.

The PCE performance of the conventional RF-to-DC converter is experimentally characterized in Figure 4 by varying the input power ${\mathrm{P}}_{\mathrm{RF}}$. The measurement results demonstrate that the PCE performance decreases as the input power ${\mathrm{P}}_{\mathrm{RF}}$ increases. The maximum PCE of 45% is achieved by the RF-to-DC converter at an input RF power of −20 dBm. Both Figure 3 and Figure 4 refer to the experimental characterization of a six-stage CMOS Dickson rectifier that provides a DC output voltage ${\mathrm{V}}_{\mathrm{DC}}$ of 2.4 V when loaded with a 2.2 M$\mathsf{\Omega }$ load resistor $R_{load}$, which is the load required to achieve the sensitivity power level. The circuit operates at a frequency of 868 MHz and, during the measurement sessions, it was directly powered through a RF power source with nine different RF power levels ranging from the sensitivity power level ${\mathrm{P}}_{\mathrm{RF}\_\min }$ of −22 dBm to the maximum specified power ${\mathrm{P}}_{\mathrm{RF}\_\max }$ of 0 dBm. Figure 5 illustrates that to achieve maximum sensitivity performance while optimizing the PCE, it is necessary to vary dynamically the number of converter stages ${\mathrm{N}}_{\mathrm{oS}}$ starting from the measurement of the input power ${\mathrm{P}}_{\mathrm{in}}$. This suggests the implementation of a reconfigurable RF-to-DC converter. Simulation results, later confirmed by experimental measurements, show that the best PCE performance is achieved by choosing ${\mathrm{N}}_{\mathrm{oS}}$ = 6, ${\mathrm{N}}_{\mathrm{oS}}$ = 4, and ${\mathrm{N}}_{\mathrm{oS}}$ = 3. As a result, the figure shows an RF-to-DC converter with three distinct configurations that differ in the number of rectifier stages: ${\mathrm{N}}_{\mathrm{oS}}$ = 6, ${\mathrm{N}}_{\mathrm{oS}}$ = 4, and ${\mathrm{N}}_{\mathrm{oS}}$ = 3. At the highest number of rectifier stages (${\mathrm{N}}_{\mathrm{oS}}$ = 6), the PCE is maximum at the minimum input power (${\mathrm{P}}_{\mathrm{in}}$ = −22 dBm). However, as the input power increases to ${\mathrm{P}}_{\mathrm{in}}$ = −14 dBm, the maximum PCE is achieved by decreasing the number of rectifier stages to ${\mathrm{N}}_{\mathrm{oS}}$ = 4. Further increasing the input power to ${\mathrm{P}}_{\mathrm{in}}$ = −10 dBm requires decreasing the number of rectifier stages to ${\mathrm{N}}_{\mathrm{oS}}$ = 3 to re-establish the highest PCE.

The graph depicted in Figure 6 illustrates how the PCE and power sensitivity of the RF-to-DC converter vary with changes in input power, for three different configurations of the number of rectifier stages ${\mathrm{N}}_{\mathrm{oS}}$: 6, 4, and 3. The graph illustrates how the minimum RF power required to operate the RF-to-DC converter decreases with an increase in the number of rectifier stages ${\mathrm{N}}_{\mathrm{oS}}$. For instance, when ${\mathrm{N}}_{\mathrm{oS}}$ is 6, the converter produces a DC output power of 2.4 $\mathsf{\mu }\mathrm{W}$ with a RF input power of −22 dBm, while ${\mathrm{N}}_{\mathrm{oS}}$ values of 4 and 3 require minimum RF input powers of −20 dBm and greater than −16 dBm, respectively, to achieve the same DC output power. The highest power sensitivity performance is achieved with the maximum number of rectifier stages, but as RF power increases, the PCE tends to decrease, making it beneficial to reduce ${\mathrm{N}}_{\mathrm{oS}}$ to 4 when ${\mathrm{P}}_{\mathrm{RF}}$ exceeds −18 dBm. However, when ${\mathrm{P}}_{\mathrm{RF}}$ reaches −12 dBm, it is advantageous to apply the technique again and reduce the number of rectifier stages to 3, resulting in a maximum PCE improvement of up to 10% compared to the six-rectifier-stage RF-to-DC converter without MPPT. Figure 7 compares the PCE performance of the RF-to-DC converter with and without the MPPT feature. The experimental characterization involved directly supplying the circuit with RF power (${\mathrm{P}}_{\mathrm{RF}}$) that varied from −22 dBm to 0 dBm. The graph shows that the system with MPPT achieves ≈ 10% higher PCE at peak performance while maintaining the same power sensitivity performance.

3.2. MPPT System Architecture: System Design, Experimental Measurements and Validation

To perform MPPT by optimally configuring the number of rectifier stages ${\mathrm{N}}_{\mathrm{oS}}$ of the RF-to-DC converter, it is essential to continuously measure the input-received power ${\mathrm{P}}_{\mathrm{RF}}$. However, measuring ${\mathrm{P}}_{\mathrm{RF}}$ is challenging due to the need for an ultra-low-power architecture and circuitry. This work proposes an indirect and innovative method to measure ${\mathrm{P}}_{\mathrm{RF}}$ by monitoring the open-circuit voltage ${\mathrm{V}}_{\mathrm{oc}}$ at the output of the RF-to-DC converter. The relationship between the open-circuit voltage of a two rectifier stage converter and the input-received power ${\mathrm{P}}_{\mathrm{RF}}$ is illustrated in Figure 8.

As shown in the conceptual block diagram in Figure 9, the RF-to-DC converter architecture comprises two separate rectifiers connected to the same antenna to prevent energy losses that may occur when disconnecting the converter from the antenna. These rectifiers perform different functions, with one rectifier responsible for power conversion, while the other monitors and measures the RF input power through the indirect measurement of the open-circuit voltage ${\mathrm{V}}_{\mathrm{oc}}$. The RF-to-DC converter used for power monitoring is loaded with a very high impedance ${\mathrm{R}}_{\mathrm{load}\_\mathrm{oc}}$ higher than 10 M$\mathsf{\Omega }$, i.e., the input gate of an NMOS transistor, it has a lower number of rectifier stages compared to the power converter stage (M < N). Using an RF-to-DC converter with a minimal number of rectifier stages has the advantages of reduced energy consumption and operation at a lower DC voltage level. The DC output of the RF-to-DC converter used for monitoring the input power is connected to a high impedance, which is the typical input stage of a CMOS comparator. Therefore, the power consumption of the power monitoring converter is significantly lower than that of the RF-to-DC power converter, and it has a negligible effect on the system PCE performance. The RF-to-DC power converter is designed with a dynamically reconfigurable number of rectifier stages ${\mathrm{N}}_{\mathrm{oS}}$ that varies as a function of the received power ${\mathrm{P}}_{\mathrm{RF}}$. It is worth highlighting that, with a careful layout, the RF-to-DC converter used for power monitoring and the RF-to-DC converter used for power conversion share the same PVT conditions. Indeed, across different PVT conditions, the system can track the Maximum Power Point. This aspect is an advantage of the system, as it ensures that the power monitor can accurately track the power conversion efficiency of the system, even under PVT variations.

The data presented in Figure 10 suggest that decreasing the number of rectifier stages can improve the PCE performance as the RF input power increases. Specifically, when the RF input power exceeds −18 dBm, the number of rectifier stages should be reduced from 6 to 4, and when it exceeds −12 dBm, the stages should be reduced from 4 to 3. Therefore, to determine the optimal number of rectifier stages, it is necessary to monitor the open-circuit voltage ${\mathrm{V}}_{\mathrm{oc}}$. As shown in Figure 10, to achieve an improvement in PCE performance, the number of rectifier stages must be reduced from 6 to 4 as soon as ${\mathrm{V}}_{\mathrm{oc}}$ exceeds 1.2 V (${\mathrm{P}}_{\mathrm{RF}}$ > −18 dBm), and from 4 to 3 as soon as ${\mathrm{V}}_{\mathrm{oc}}$ exceeds 1.5 V (${\mathrm{P}}_{\mathrm{RF}}$ > −12 dBm).

As illustrated in Figure 11, an ultra-low-power voltage comparator is used to monitor the voltage ${\mathrm{V}}_{\mathrm{oc}}$. The optimum number of rectifier stages for the RF-to-DC power conversion is determined by an asynchronous Finite State Machine (FSM) through the digital signal ${\mathrm{N}}_{\mathrm{oS}}$. The FSM circuitry also manages the signals hth and lth, which define the voltage threshold provided as a voltage reference for the voltage comparator. To prevent any quiescent current due to an oscillator and affect the system performance in terms of PCE, the FSM is asynchronous and has four different states. The Power-On Reset (POR) circuitry resets the FSM when the voltage ${\mathrm{V}}_{\mathrm{DC}}$ is below 1.4 V.

3.3. Dual RF-to-DC Converter for Power Monitoring and Power Conversion

Figure 12 shows the schematic of the dual RF-to-DC converter. The schematic shows the power monitor section implemented with a fixed 1-stage rectifier. The power conversion section is reconfigurable through the 6-bit digital bus d_NoS[5:0] provided by the FSM. The digital bus d_NoS[5:0] selects the number of stages as described in

Table 1. Digital configuration of the reconfigurable rectifier.

d_NoS[5:0]	${\mathit{N}}_{\mathbf{oS}}$	Topology
000000	6	6-stage rectifier
011010	4	4-stage rectifier
101101	3	3-stage rectifier

. It is worth highlighting that the 3-stage rectifier is configured by splitting into two sections, the 6-stage rectifier (M1 to M12), and reconnecting in parallel the two 3-stage sections (M1 to M6 in parallel with M7 to M12), to contribute in optimizing the PCE.

To ensure that the power monitor section does not affect the PCE by more than 1%, the maximum power consumption of the additional circuitry must be limited to 60 nW at 868 MHz and at the minimum ${\mathrm{P}}_{\mathrm{RF}}$ power of −22 dBm. Achieving this required an accurate design of the power monitoring RF-to-DC converter and a nano-power architecture of the voltage comparator. The power monitoring RF-to-DC converter has only one rectifier stage, optimized sizes of rectifying devices, and minimized parasitic capacitances to achieve a power consumption below 50 nW when the power ${\mathrm{P}}_{\mathrm{RF}}$ is −22 dBm at 868 MHz. As a result, the total power consumption added by the circuitry to perform the MPPT contributes to only 1% of the 6 $\mathsf{\mu }\mathrm{W}$ (−22 dBm) of the input sensitivity power ${\mathrm{P}}_{\mathrm{RF}\_\min }$. This solution provides an effective advantage, as it achieves a net increase of ≈10% in PCE performance by investing only 1% of extra power consumption. Figure 13 displays the circuit layout of the RF-to-DC converter. The picture shows that adding the power monitoring circuitry to the conventional RF-to-DC converter results in a negligible overhead in silicon area.

3.4. Finite State Machine

Figure 14 depicts the FSM state diagram, which shows that the FSM enters ‘State 1’ after a reset. In this state, the digital bus d_NoS[5:0] is set to “000000” and configures the RF-to-DC converter to work with the maximum number of six rectifier stages. The signal $l_{th}$ is set high to establish the lower voltage threshold ${\mathrm{V}}_{\mathrm{th}\_\mathrm{low}}$ of 1.2 V as a voltage reference to the voltage comparator, while the signal $h_{th}$ is low. The voltage ${\mathrm{V}}_{\mathrm{oc}}$ remains below ${\mathrm{V}}_{\mathrm{th}\_\mathrm{low}}$ and the signal ‘cs’ is low as long as the power ${\mathrm{P}}_{\mathrm{RF}}$ remains below −18 dBm. When the power ${\mathrm{P}}_{\mathrm{RF}}$ exceeds −18 dBm, the voltage ${\mathrm{V}}_{\mathrm{oc}}$ increases beyond ${ }_{\mathrm{th}\_\mathrm{low}}$, causing the signal ‘cs’ to go high and triggering the FSM to transition from ‘State 1’ to ‘State 2’. In ‘State 2’, the digital bus d_NoS[5:0] is set to “011010” and the RF-to-DC converter operates with four rectifier stages to improve the PCE performance. The signal $l_{th}$ is low, while $h_{th}$ is high, to configure the higher voltage threshold ${\mathrm{V}}_{\mathrm{th}\_\mathrm{high}}$ of 1.5 V as the voltage reference for the voltage comparator. When the power ${\mathrm{P}}_{\mathrm{RF}}$ exceeds −12 dBm, the voltage ${\mathrm{V}}_{\mathrm{oc}}$ increases beyond ${\mathrm{V}}_{\mathrm{th}\_\mathrm{high}}$, causing the signal ‘cs’ to go high and triggering the FSM to transition from ‘State 2’ to ‘State 4’. In ‘State 4’, the digital bus d_NoS[5:0] is set to “101101” and the RF-to-DC converter operates with three rectifier stages to improve the PCE performance. The signal $l_{th}$ is low, while $h_{th}$ is high, to configure the higher voltage threshold ${\mathrm{V}}_{\mathrm{th}\_\mathrm{high}}$ of 1.5 V as the voltage reference for the voltage comparator. If the power ${\mathrm{P}}_{\mathrm{RF}}$ falls below −12 dBm while in ‘State 4’, the signal ‘cs’ goes low, and the FSM transitions from ‘State 4’ to ‘State 3’, where the RF-to-DC converter operates with four rectifier stages. The signal $l_{th}$ is high, while $h_{th}$ is low, to configure the lower voltage threshold ${\mathrm{V}}_{\mathrm{th}\_\mathrm{low}}$ of 1.2 V as the voltage reference for the voltage comparator. If the power ${\mathrm{P}}_{\mathrm{RF}}$ falls below −18 dBm while in ‘State 3’, the signal ‘cs’ goes low, and the FSM transitions from ‘State 3’ to ‘State 1’. However, if the power ${\mathrm{P}}_{\mathrm{RF}}$ exceeds −18 dBm, the signal ‘cs’ goes high, and the FSM transitions from ‘State 3’ to ‘State 2’.

3.5. Voltage Reference

The nano-power voltage reference is a fully CMOS voltage reference based on a self-biased topology. The circuit is resistor-less, does not require additional fabrication masks to save area and costs, and consists of only MOSFET devices operating in the subthreshold region. It is based on the well-known technique to generate two voltages with opposite temperature coefficients and add them to provide a temperature-compensated voltage with a near-zero temperature coefficient [22,23,24]. It implements a device in the standard 0.13 µm CMOS technology with overall current consumption of 25 nA and bias operating voltage in the range [1.1–3.3] V. Figure 15 shows the schematic of the circuit that consists of the following main sections:

• The start-up circuit consists of the transistors M18, M19, and an inverter. This circuit prevents the operation at zero current of the self-biasing circuit.
• The triode-based Widlar current reference implements an accurate temperature compensation with temperature coefficient of 100 ppm/°C. This circuit consists of the transistors M1–M6. Functionally, it is a current reference that provides a reference current to the active load.
• The active load consists of transistors M11–M17 and provides the reference voltage, $V_{ref}$ of ≈ 800 mV.

The reference voltage $V_{ref}$ can be written as in (1)

$$V_{ref}=V_{th,n}+\frac{K_B·T}{q}·\eta ·ln\left(24·\frac{K_{12}·K_{14}·K_{16}}{K_{11}·K_{13}·K_{15}}·\frac{K_3·{\eta }^2}{\eta -1}·{ln}^2\left(\frac{K_2}{K_1}\right)·\left[\left(\frac{K_3+K_4}{K_4}\right)+\sqrt{{\left(\frac{K_3+K_4}{K_4}\right)}^2-1}\right]\right)$$

(1)

where

• $\eta$ is the subthreshold slope factor;
• $V_T$ = $\frac{K_B·T}{q}$ is the thermal voltage;
• $K_i=\frac{W_i}{L_i}$ is aspect ratio of transistor $M_i$;
• $W_i$ is width of transistors $M_i$;
• $L_i$ is length of transistors $M_i$;
• $V_{GSi}$ is the gate-source voltage of transistor $M_i$;
• ${\mathsf{\mu }}_n$ is the carrier mobility of the n-type transistor;
• $C_{ox}$ is the gate-oxide capacitance;
• $V_{th,n}$ is threshold voltage of the n-type transistor;
• $K_B$ is the Boltzman constant;
• T is the absolute temperature;
• q is the elementary charge.

Equation (1) is derived as follows.The triode-based Widlar current reference implements a self-biased triode-based Widlar circuit. The transistor M3 is biased in the triode region to work like a resistor and, transistors M1 and M2 are biased in the subthreshold region. Transistors $M_5$ and $M_6$ are matched and biased in strong inversion and, in first-order approximation, their currents are equal to the reference current $I_{ref}$. The reference current is equal to the product of the drain-source voltage $V_{DS3}$ of the transistor M3 and its conductance $G_{M3}$ as given by Equation (2)

$$I_{ref}=V_{DS3}·G_{M3}$$

(2)

$V_{DS3}$ is equal to the gate-source voltage difference of the transistors M1 and M2 as in Equation (3)

$$V_{DS3}=V_{GS1}-V_{GS2}=\eta ·V_T·ln\left(\frac{K_2}{K_1}\right)$$

(3)

$G_{M3}$ is given by Equation (4)

$$G_{M3}={\mathsf{\mu }}_n·C_{ox}·(V_{GS3}-V_{th,n})·K_3$$

(4)

Since transistors M1 and M2 are biased in subthreshold, the drain-source current $I_{DS}$ of these transistors is as expressed in Equations (5) and (6) where, $V_{DS1}$ and $V_{DS2}$ are the respective drain-source voltages of transistors $M_1$ and $M_2$

$$I_{DS1}=·{\mathsf{\mu }}_n·C_{ox}·(\eta -1)·K_1·{V_T}^2·exp\left(\frac{V_{GS1}-V_{th,n}}{\eta ·V_T}\right)·\left[1-exp\left(-\frac{V_{DS1}}{V_T}\right)\right]$$

(5)

$$I_{DS2}=·{\mathsf{\mu }}_n·C_{ox}·(\eta -1)·K_2·{V_T}^2·exp\left(\frac{V_{GS2}-V_{th,n}}{\eta ·V_T}\right)·\left[1-exp\left(-\frac{V_{DS2}}{V_T}\right)\right]$$

(6)

Transistors $M_1$ and $M_2$ are biased with a drain-source voltage higher the $5·V_T$. This bias condition ensures that the term $\left[1-exp\left(-\frac{V_{DS2}}{V_T}\right)\right]$ becomes negligible with a loss of accuracy in the drain-source current below 1%.

Based on this condition Equations (5) and (6) can be simplified as follows:

$$I_{DS1}\approx {\mathsf{\mu }}_n·C_{ox}·(\eta -1)·K_1·{V_T}^2·exp\left(\frac{V_{GS1}-V_{th,n}}{\eta ·V_T}\right)$$

(7)

$$I_{DS2}\approx {\mathsf{\mu }}_n·C_{ox}·(\eta -1)·K_2·{V_T}^2·exp\left(\frac{V_{GS2}-V_{th,n}}{\eta ·V_T}\right)$$

(8)

Since $(I_{DS1}\approx I_{DS2})=I_{ref}$, the reference current $I_{ref}$ can be derived from Equations (2), (4), (7) and (8) as in (9)

$$I_{ref}=\underset{V_{DS3}}{\underbrace{\eta ·V_T·ln\left(\frac{K_2}{K_1}\right)}}·{\mathsf{\mu }}_n·C_{ox}·K_3·(V_{GS3}-V_{th,n})$$

(9)

Equation (10) reports the gate-source voltage $V_{GS3}$ of transistor $M_3$

$$V_{GS3}=V_{DS3}+V_{GS4}$$

(10)

Transistor $M_4$ operates in strong inversion, consequently, its gate-source voltage is given by Equation (11)

$$V_{GS4}=V_{th,n}+\sqrt{\frac{2·I_{ref}}{{\mathsf{\mu }}_n·C_{ox}·K_4}}$$

(11)

By combining (3), (9)–(11), the reference current can be expressed as in (12)

$$I_{ref}^2-2·{\mathsf{\mu }}_n·C_{ox}·V_{DS3}^2·\frac{K_3}{K_4}·\left(K_3+K_4\right)·I_{ref}+{\left({\mathsf{\mu }}_n·C_{ox}·V_{DS3}^2\right)}^2=0$$

(12)

By solving Equation (12), the reference current $I_{ref}$ can be expressed as in (13)

$$I_{ref}={\mathsf{\mu }}_n·C_{ox}·K_3·{\eta }^2·V_T^2·{ln}^2\left(\frac{K_2}{K_1}\right)·\left[\left(\frac{K_3+K_4}{K_4}\right)+\sqrt{{\left(\frac{K_3+K_4}{K_4}\right)}^2-1}\right]$$

(13)

The reference current $I_{ref}$ is mirrored to the transistors $M_7, M_8, M_9, \mathrm{and} M_{10}$ with the ratio of 1. The transistors $M_{11}$, $M_{12}$, $M_{13}$, $M_{14}$, $M_{15}$, $M_{16}$, and $M_{17}$ operate in subthreshold.

The reference voltage $V_{ref}$ is given by Equation (14)

$$V_{ref}=V_{DS11}+V_{DS13}+V_{DS15}+V_{GS17}$$

(14)

where

$$V_{DS11}=V_{GS11}-V_{GS12}=\eta ·V_T·ln\left(4·\frac{K_{12}}{K_{11}}\right)$$

(15)

$$V_{DS13}=V_{GS13}-V_{GS14}=\eta ·V_T·ln\left(3·\frac{K_{14}}{K_{13}}\right)$$

(16)

$$V_{DS15}=V_{GS15}-V_{GS16}=\eta ·V_T·ln\left(2·\frac{K_{16}}{K_{15}}\right)$$

(17)

$$V_{GS17}=V_{th,n}+\eta ·V_T·ln\left(\frac{I_{ref}}{{\mathsf{\mu }}_n·C_{ox}·(\eta -1)·V_T^2·K_{17}}\right)$$

(18)

From equations $Vref$, $V_{DS11}$, $V_{DS13}$, $V_{DS15}$, and $V_{GS17}$, $V_{ref}$ can be expressed as in (19)

$$V_{ref}=V_{th,n}+\eta ·V_T·ln\left(24·\frac{K_{12}·K_{14}·K_{16}}{K_{11}·K_{13}·K_{15}}·\frac{I_{ref}}{{\mathsf{\mu }}_n·C_{ox}·(\eta -1)·V_T^2}\right)$$

(19)

From (13) and (19) the reference voltage $V_{ref}$ can be written as in Equation (1).

3.6. Voltage Comparator

In the proposed MPPT architecture, the ultra-low-power voltage comparator operates continuously and must have a minimum quiescent power consumption. Therefore, a nano-power voltage comparator has been designed based on a common-gate architecture [25]. This design exhibits a simple circuit topology and ultra-low-power consumption, consuming below 10 nW at a bias voltage of 2.4 V. Figure 16 shows the schematic of the voltage comparator.

The core of the circuit consists of the current sources, implemented with transistors MN3 and MN4, and the two pMOS transistors MPL and MPR. Transistors MN2, MN3, and MN4 have all the same aspect ratio that is double that of transistor MN1 ($K_{MN2}=K_{MN3}=K_{MN4}=2·K_{MN1}$). The current $I_{bias}$ flowing through transistor MN1 of $0.5$ nA. The two nMOS transistors MNL and MNR, are connected as source followers so that the voltages $V_a$ and $V_b$, respectively, follow the voltages $V_{INP}$ and $V_{INN}$. When the voltage $V_{INN}$ is lower than $V_{INP}$, the voltage $V_b$ is also lower than $V_a$ and the source-gate voltage of the pMOS transistor MPR is lower than that of MPL. As a consequence, the current $I_{MPR}$, which flows through the transistor MPR, is higher than the current $I_{MN4}$, which flows through the transistor MN4, so that the voltage $V_{CMP}$ goes high and, so the voltage $V_{OUT}$. When instead, $V_{INN}$ is higher than $V_{INP}$, $V_a$ is also higher than $V_b$ and the source-gate voltage of transistor MPR is higher than that of MPL. As a consequence, the current $I_{MPR}$ is lower than $I_{MN4}$ so that $V_{CMP}$ goes low and so $V_{OUT}$. Indeed, the current $I_{MPR}$ determines the voltage $V_{CMP}$ as well as the voltage $V_{OUT}$. The pMOS transistors MPL and MPR are biased in subthreshold with a source-drain voltage always higher than five times the thermal voltage $\frac{K_B·T}{q}$. $K_B$ is the Boltzman constant, T is the absolute temperature, and q is the elementary charge. In this condition, the currents $I_{MPR}$ and $I_{MPL}$ are provided by (20) and (21), respectively. Since transistors MPR, MPL, MN3, and MN4 are biased in subthreshold with a source-drain voltage always higher than five times the thermal voltage $\frac{K_B·T}{q}$, i.e., 150 mv, the minimum voltage of $V_a$ and $V_b$ cannot be lower than 300 mv so that the voltages $V_{INP}$ and $V_{INN}$ must always be higher than 700 mv.

$$I_{MPR}={\mathsf{\mu }}_p·C_{ox}·(\eta -1)·K_{MPR}·V_T^2·exp\left(\frac{V_{SG\_MPR}-\left|V_{th,p}\right|}{\eta ·V_T}\right)$$

(20)

$$I_{MPL}={\mathsf{\mu }}_p·C_{ox}·(\eta -1)·K_{MPL}·V_T^2·exp\left(\frac{V_{SG\_MPL}-\left|V_{th,p}\right|}{\eta ·V_T}\right)$$

(21)

From (21), the source-gate voltage $V_{SG\_MPL}$ of transistor MPL is expressed as in (22)

$$V_{SG\_MPL}=\left|V_{th,p}\right|-\eta ·V_T·ln\left(\frac{2·I_{bias}}{{\mathsf{\mu }}_p·C_{ox}·(\eta -1)·K_{MPR}}\right)$$

(22)

The source-gate voltage of transistor MPR is expressed in (23)

$$V_{SG\_MPR}=V_b-V_{CG}=V_b-V_a+V_{SG\_MPL}$$

(23)

From (20) and (23), being $K_{MPR}=K_{MPL}$, the current through the transistor MPR can be expressed as in (24)

$$I_{MPR}=2·I_{bias}·exp\left(\frac{V_a-V_b}{\eta ·V_T}\right)$$

(24)

Consequently, the current out of the node CMP is given by (25)

$$I_{CMP}=I_{MPR}-2·I_{bias}=2·I_{bias}·\left[exp\left(\frac{V_a-V_b}{\eta ·V_T}\right)-1\right]$$

(25)

When $V_{INP}>V_{INN}$, which implies $V_a>V_b$, the current $I_{CMP}$ is positive and charges the gate capacitance of the transistor MN5 so that the voltage $V_{CMP}$ increases. On the contrary, when $V_{INP}<V_{INN}$, i.e., $V_a<V_b$ the current $I_{CMP}$ becomes negative and $V_{CMP}$ decreases. The voltage $V_{CMP}$ goes from its higher voltage to zero as soon as $V_a=V_b$.

3.7. Power Consumption Distribution

Table 2. Power consumption distribution.

	Voltage Reference	Voltage Comparator	Power Monitoring RF-to-DC Converter
Power Consumption	100 nW	40 nW	50 nW
Relative Power Consumption to ${\mathrm{P}}_{\mathrm{RF}\_\min }$ = 6 µW (−22 dBm)	1.7%	0.66%	1%
Relative Power Consumption to ${\mathrm{P}}_{\mathrm{DC}\_\min }$ = 2.4 µW	4.2%	1.7%	2%

shows the power consumption of the system sub-circuits and the relative power consumption to the specified power sensitivity $P_{RF\_min}$ and the achievable DC power consumption $P_{DC\_min}$. The table does not report the power consumption of the asynchronous FSM because it is asynchronous, so the static power consumption is zero, and only negligible dynamic power consumption should be considered during reconfiguration events.

Table 3. Comparison among experimental results of the proposed RF-to-DC converter with the state-of-the-art solutions.

Reference	[18]	[13]	[21]	[14]	This Work	This Work
CMOS Technology	180 nm	130 nm	130 nm	130 nm	130 nm	130 nm
Operating Frequency (MHz)	1000	915	900	900	868	868
PCE max (%)	33 @ −8 dBm	42.4 @ −16 dBm	34.93 @ −10 dBm	78.4 @ −16 dBm	55 @ −12.5 dBm	45 @ −20 dBm
Sensitivity (dBm)	−20.2	−25.5	−21.7	−18	−22	−22
Reconfigurable RF-to-DC Rectifier	Yes	No	Yes	No	Yes	No
MPPT	No	No	No	No	Yes	No

provides a comparison of the system’s performance with and without the MPPT implementation, as well as other state-of-the-art projects in the literature. The last two columns of the table present the PCE improvement achieved by applying the MPPT technique with the reconfigurable RF-to-DC rectifier, revealing a maximum increase of ≈10% compared to the basic RF-to-DC rectifier without MPPT. It is relevant to note that no additional effort has been made to optimize the external matching network in this work, and a simple LC matching network tuned at 868 MHz has been designed to achieve the optimum sensitivity. Therefore, the PCE improvement obtained with this implementation serves as a reference point for a system that can be further enhanced through a reconfigurable matching network.

3.8. Measurement Setup and Results

Figure 17 and Figure 18 display the layout and microphotograph of the SoC, respectively. The SoC integrates the reconfigurable RF-to-DC converter, the MPPT system, and a RF receiver with Amplitude-Shift-Keying/Frequency-Shift-Keying (ASK/FSK) demodulation to receive data [26].

The system was tested in a real-world application scenario that simulates wireless power transfer in free-space between a RF reader and a power receiver that integrates the RF-to-DC converter. Figure 19 displays the two boards that were designed to implement the RF reader and the RF power receiver.

The reader utilizes STMicroelectronics’ SPIRIT1, a low-power RF sub-GHz transceiver with a power amplifier that can output up to 27 dBm [27]. Both units were equipped with Laird’s half-wave printed dipole antenna, specifically Revie Pro [28]. To perform wireless power transfer in free-space, the two units were placed on a measurement bench, as shown in Figure 20.

The digital multimeter 34410A from Agilent was used to measure the DC output voltage of the RF-to-DC converter, while the received power was measured using the DC power analyzer N6705B from Agilent, Santa Clara, California.

Figure 21 shows the output voltage of the RF-to-DC converter in an application where the system harvests energy into a 78 mF capacitor from a RF power source to supply a WSN. The figure shows how the RF-to-DC converter reconfigures to perform the power transfer with the highest efficiency by adjusting its stages and increasing the charging slope. At the startup, the RF-to-DC converter is configured, by default after the power on reset event, as a 6-stage converter that charges the capacitor with the minimum slope of 29 mV/s and progressively reconfigures to work as a 3-stage converter and increases the PCE, as indirectly shown by the increase of the charging slope from 29 mV/s to 42 mV/s.

This section may be divided by subheadings. It should provide a concise and precise description of the experimental results, their interpretation as well as the experimental conclusions that can be drawn.

4. Discussion

This work presented an innovative MPPT technique based on an ultra-low-power power monitoring circuitry and a reconfigurable RF-to-DC conversion circuit that showed an experimentally measured maximum PCE of 55% at 868 MHz in the input power range from −22 dBm to 0 dBm. Notably, this represents a 10% increase in PCE compared to a conventional RF-to-DC converter. Based on experimental results, the comparison between the PCE performance achieved using the MPPT and a conventional RF-to-DC converter was discussed. Our findings demonstrated how the new conception of the whole power conversion system achieved PCE performance improvement, regardless of the RF-to-DC converter topology, while maintaining the same performance in sensitivity. The ultra-low-power power monitoring circuitry and reconfigurable architecture of the RF-to-DC converter allowed the system to work over a wider input power range and with higher efficiency than a conventional RF-to-DC converter. Finally, this work highlighted the critical point to address in the design of ultra-low-power circuitry. It is worth noting that the same technique can be implemented in other energy sources such as photovoltaic, vibrational, and the like. In these cases, a so-conceived energy transducer would require the extra terminal for power monitoring that leads to a structure with three terminals in contrast with the state-of-the-art solution with only two terminals. This condition, at first sight, could appear as a drawback, but as revealed, this was only apparent as the induced simplicity in the WPT system architecture paid back.