Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

Abstract

This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation.

1. Introduction

The expansion of the Internet of Things has increased the need for ultra-low-power analog-to-digital converters (ADCs). Autonomous applications such as medical devices, wireless sensors, and space instruments must deal with the major issue of power dissipation. However, reducing ADC power consumption is very challenging. Thanks to their simple structure and capacity to take full advantage of process scaling, successive approximations register (SAR) ADCs present a good figure of merit, which makes them a promising choice for low-power applications. However, since the number of clock periods needed for one conversion is proportional to the resolution, this architecture cannot easily reach a high-speed resolution. To achieve a high resolution with SAR ADCs, each energy-consuming element must be carefully considered, along with sources of mismatch, noise, and any other limitations.

Several types of DAC architecture are available for implementation into a SAR ADC: capacitor-based DAC (C-DAC) [1,2,3,4,5,6], switched current DAC [7,8,9], and R-2R ladder DAC [10,11]. To reduce the DC power dissipation, the majority of SAR ADCs are based on charge redistribution algorithms using a sampled array of capacitors. Monotonic architecture [12,13] shows superior power dissipation and linearity compared to the classical algorithm; however, the former shows a non-constant common mode. V_mc-based switching architectures [14,15] also present better power features while keeping a constant common mode.

For high-resolution designs, the power consumption and the total chip area of the capacitor array become an issue in addition to the mismatch. In this work, segmentation in the capacitors array was used as one solution to the chip area issue [6,16]. Nevertheless, a segmented architecture increases sensitivity to the capacitors’ mismatch; thus, an additional digital calibration algorithm is necessary [16,17,18,19,20,21,22]. Many digital calibration architectures are very efficient; however, they increase both the circuit complexity and the total area. For applications based on multiple ADC channels working in parallel, the digital calibration of each channel leads to a very complex design. An effective solution consists of implementing a mismatch compensation technique based on an analog calibration [23,24,25] with a trimming capacitor. The spikes that usually appear in SAR converter full-range non-linearity results could be softened by applying a dynamic element matching (DEM) algorithm [26] to a partially thermometer-coded C-DAC [27]. With comparator power dissipation and noise figure being critical for circuit performance, its architecture must be carefully designed [28,29,30].

In this paper, we present the design methodology that we applied to achieve a high resolution, low power, and low chip area. This article can be considered as a set of guidelines addressing the main mismatch issues and proposing solutions for the design of high-resolution and low-power SAR ADCs. Our contributions include, first, a full model of a high-resolution SAR ADC to determine the best trade-off between the resolution, power dissipation, and chip area. Second, the noise contributors were analyzed individually, along with how they impact the final signal-to-noise ratio (SNR).

The paper is organized as follows. Section 2 describes the development of the ADC architecture and discusses capacitive DAC issues in high-resolution systems. The calibration and DEM algorithm modelization are presented in Section 3. A MATLAB model highlighted their efficiency and limitations. Section 4 focuses on a noise estimation methodology based only on simulations. Finally, in Section 5, we present some conclusions.

2. Proposed ADC Architecture

2.1. Architecture

A differential architecture was used to increase the dynamic range and simplify the charge injection compensation. A segmented capacitive array was also used to reduce the circuit area. C_u, as the unit capacitance; N, as the total number of bits; N_LSB and N_MSB, respectively, as the LSB and MSB numbers of bits; and the total capacitance for non-segmented or segmented architectures are defined by (1).

$$\{\begin{array}{c}{C}_{total\_non\_segmented}=2^N·c_u\\ C_{total\_segmented}=\left(2^{N_{LSB}}+2^{N_{MSB}}\right)·c_u\end{array}$$

(1)

The reduction in area is optimal when both LSB and MSB segments are identical (N_LSB = N_MSB = N/2); in this case, the area reduction is defined by (2). Nevertheless, the larger the MSB segment is, the better the linearity will be.

$$\frac{C_{total\_non\_segmented}}{C_{total\_segmented}}=2^{\frac{N}{2}-1}$$

(2)

Figure 1 shows the proposed SAR ADC as well as the interdependence between blocks. In this paper, a 15-bit SAR ADC was considered as an example. Here, a capacitive digital-to-analog converter (C-DAC) was used, and the MSB and LSB segment sizes were, respectively, 8 and 6 bits, which provided a good trade-off between the chip area and linearity. When one introduces the common mode voltage into the processing, an additional intrinsic bit is found. The unit capacitor C_u is defined as 30 fF according to the kT/C noise requirements. Segmented DACs are well-known as a cause of non-linearities due to their high sensitivity to mismatch and also issues with parasitic capacitors. Hence, high-resolution converters must be calibrated. In this work, an automated calibration algorithm acting on a trimming capacitor was introduced. Additionally, a 3-bit dynamic element matching (DEM) algorithm was introduced to average distortions due to mismatch limitations. A classical comparator was considered. Finally, sampling was provided by a bootstrapped switch, which presented better linearity than a conventional switch.

2.2. Issues with a High-Resolution Capacitive DAC

To achieve a high resolution, classical C-DACs require a large array of capacitors. The size of these arrays increases exponentially with the number of bits, and the total sampling capacitor value of Cs is determined by thermal kT/C noise requirements. For some applications, the kT/C RMS noise ($\sqrt{kT/C}$) must be comparable to the quantization noise (LSB/$\sqrt{12}$). However, for other applications, the final SNR is less critical; hence, in the present design, we considered that a kT/C RMS noise of about LSB/3 should be sufficient. Equation (3) shows the sampling capacitor sizing resulting from this requirement:

$$\sqrt{\frac{k·T}{C_s}}=\frac{LSB}{3}\iff C_s=\frac{k·T}{{\left[LSB/3\right]}^2}$$

(3)

Here, k corresponds to the Boltzmann constant, T is the temperature, and C_s is the sampling capacitor. Targeting a thermal noise of about LSB/3 in a 15-bit SAR ADC, the total sampling capacitor C_s must reach 10 pF. In our design, this requirement corresponds to choosing a unit capacitance, C_u, equal to 30 fF.

Figure 2 shows the simulation results for the noise model when a single-ended DAC architecture is considered. The sampling capacitor was sized to fit the noise distribution presented; thus, the Gaussian 6-sigma rule assumes that the noise level is within +/− 1 LSB, leading to an RMS value of about LSB/3.

In a differential scheme, the dynamic range for the signal doubles, meaning that the unit capacitor could be reduced accordingly without affecting the SNR.

For a high-resolution design, after determining the total capacitor value following the kT/C noise rules, it is possible to calculate the value of the unit capacitor in the array. This value may be lower than the smallest capacitor available in the process design kits. One solution to this issue is to design specific MOM capacitors, which are smaller than those in process design kits [31]. In our design, we considered a segmented DAC scheme where the total number of capacitors in the DAC array was reduced.

Figure 2 shows the total DAC array capacitance that is necessary according to the kT/C thermal noise requirements (in green). Considering a unit capacitor of C_u = 5 fF, the blue curve shows the resultant value of the total capacitor for a classical non-segmented design. The red curve shows the total capacitor value considering a segmented DAC scheme with the same unit capacitor. In the segmented case, it appears that the value for the unit capacitor must be increased to reach the theoretical noise requirement (green curve).

Unfortunately, segmentation in the capacitor array leads to an extreme sensitivity to mismatch and parasitic capacitors. Due to its fractional value, the optimum for the bridge capacitor is not easily achievable. Consequently, the linearity in this architecture is very sensitive to capacitor mismatch. It is, therefore, necessary to compensate for these limitations by applying a calibration method. Some studies have proposed the use of a distinct digital foreground or background algorithm to perform this calibration, but this increases the digital complexity. In this study, we used an analog self-tuning technique.

3. Circuit Modelization

3.1. Capacitive C-DAC

The segmented architecture proposed in Figure 3 based on the V_mc switching architecture was divided into two segments: MSB on the right going to the output, and LSB on the left, separated by the bridge capacitor C_a. For improved linearity, we used more digits for the 8-bit MSB segment (from C to 128 C) than in the 6-bit LSB segment (from C to 32 C). The input signal was sampled on the top of these capacitors. The SAR voltage levels were generated by switching the reference voltages (V_refP, V_refN, and V_mc) over the bottom plate of these capacitors. A differential architecture was considered, but only one DAC is shown. In this scheme, an additional trimming capacitor C_c was considered to compensate for the mismatch error.

In Figure 4, we consider a simplified 4-bit converter as an example and describe the first steps of a V_mc-based switching algorithm [14,15]. The conversion process works as follows. During the sampling phase, the top plates of the capacitors were all connected to the input signal V_in while the bottom sides were connected to V_cm, as illustrated in Figure 4a. During the first conversion step illustrated in Figure 4b, if the comparison result was high (V_p > V_n), then the MSB capacitor 2C of the upper P-DAC performed a down transition (the level change operation was performed by switching the bottom plate from V_mc to V_refN). Symmetrically, the MSB capacitor 2C of the lower N-DAC performed an up transition (the bottom plate was switched from V_mc to V_refP), as shown in Figure 4c. Conversely, if the comparison result was low (V_p < V_n), the MSB capacitor of the P-DAC could be connected to V_refP, and the MSB capacitor of the N-DAC could be connected to V_refN, as illustrated in Figure 4d. Finally, the result of the comparison defines the MSB bit of the output digital code.

3.2. Mismatch Calibration

In a high-resolution segmented capacitor array, the non-binary value of the segmentation capacitor was a source of important non-linearity; hence, a mismatch compensation concept was required. Instead of using a fixed value for the capacitor C_c, we produced one that was variable and programmable. This trimming strategy was realized in order to compensate for the mismatch effect due to the bridge capacitor C_a. This concept is made consistent by oversizing the segmentation capacitor C_a and then linearly tuning the trimming capacitor C_c until the contribution from the LSB segment is equal to that of the MSB segment’s unit capacitor C. This trimming process was automated in our design.

Based on the notations illustrated in Figure 5, Equations (4) and (5) describe the two phases of charge redistribution. Here, the LSB equivalent capacitance is noted as C_L, and the first seven MSB capacitances as C_M. C_a is the bridge capacitor, and C_u is the unit capacitor.

$$\Delta V_{out}\left(C_a+C_u+C_M\right)=\Delta V_L·C_a+\Delta V_x·C_u$$

(4)

$$\Delta V_L\left(C_c+C_L+C_a\right)=\Delta V_{out}·C_a-\Delta V_x·C_L$$

(5)

The trimming capacitor Cc was calculated so that the output remained stable ($\Delta V_{out}=0$). Equation (6) details the outcome result. The value chosen here for the unit capacitor C_u was 30 fF in order to fit the thermal noise limitations.

$$C_c=\left(2^{N_{LSB}}-1\right)·C_a-2^{N_{LSB}}·C_u$$

(6)

Figure 6 presents the set of trimming capacitors’ C_c architecture. This one is made up of a k-multiple capacitor C_trim in parallel, which can be connected, or not, to the DAC network (node called V_L in Figure 5) in order to modify the value of C_c. The digital tuning signal V_{control_Cc} was determined by the calibration algorithm. After the calibration, the tuning capacitor C_c was determined through Equation (7).

$$C_c={{\displaystyle \sum }}_{i=0}^{k-1}{V}_{contro{l}_{Cc}}\langle i\rangle ·C_{trim}$$

(7)

Ideally, good matching means that the LSB segment presents the same contribution as the unit capacitor C_u in the MSB segment. However, if the bridge capacitor is oversized, the contribution of the LSB segment is greater than that of the unit capacitor. The progressive tuning of C_c can then be used to re-optimize matching in the circuit. This trimming process was automated in our design following the algorithm explained in reference [22]. The simplicity of this trimming method, along with the low surface that is consumed, is a major advantage compared to some other digital calibration methods.

The calibration process was developed with a MATLAB model. The segmented DAC was assumed to be almost ideal; then, an additional random mismatch coefficient was applied to the segmentation capacitor alone. According to Monte Carlo simulations, the random coefficient follows a Gaussian distribution with a process-dependent standard deviation. The efficiency of the trimming can be observed through the strong reduction in integral non-linearity (INL) after calibration (Figure 7). The INL after calibration is equal to 1 LSB (INL of ideal ADC), and the mismatch of the bridge capacitor is fully balanced.

3.3. Partially Thermometer-Coded Capacitive Array

Thermometer coding was partially applied to our C-DAC array. Instead of binary elements, the DAC included some identical unary capacitors on the MSB side, with each bit split into identical parallel unit capacitors. The optimal result for the INL occurred for a fully thermometer-coded C-DAC. However, that would significantly increase the number of switches and, consequently, the decoder’s complexity, leading to a drastic increase in the circuit area. A possible compromise would be to include thermometer coding only for some of the first MSB bits. Figure 8 shows the ADC linearity versus the number of thermometer bits. One can observe that a 3-bit thermometer provides a good trade-off between the circuit area and linearity performance.

Figure 9 shows a 15-bit SAR ADC with a 3-bit thermometer-coded C-DAC. For this architecture, the SAR logic stands for a classic dichotomy logic circuit [32] before a thermometer decoder is added for the demultiplexing of the switch control [d₀ d₁ d₃]. Figure 10 shows the modeled efficiency of a thermometer-coded C-DAC compared to a classical binary C-DAC when a significant mismatch effect following Pelgrom’s law [33] is included.

3.4. Dynamic Element Matching (DEM) Algorithm

A DEM is implemented over the thermometer-coded capacitive array. The algorithm exploits the non-uniform mismatch distribution to randomize the capacitor’s attribution [26]. In other words, bit b_i is not always connected to the same capacitor but is instead connected to a random group of capacitors selected among the full arrays. For each conversion phase, the mismatch configuration is different. Therefore, the outcome INL is correlated to the mean value of a series of mismatches, and non-linearity gaps are reduced.

Ideally, DEM requires a random number generator. However, a digital pseudo-random number generator with a long-enough random cyclic sequence provides an adequate compromise. We used such a system, designed as shown in Figure 11. A linear feedback shift register (LFSR) was considered to generate the pseudo-random sequence, as illustrated in Figure 12. The polynomial order determines the sequence length, with the function applied based on (8). The technical efficiency could be observed through the strong reduction in INL after the application of DEM, considering a 2% mismatch for each unit capacitor, as shown in Figure 13 and

Table 1. ADC performance summary considering a 2% mismatch for each unit capacitor.

Architecture	INL
Binary C-DAC	±28 LSB
Thermometer C-DAC	±18 LSB
Thermometer C-DAC + DEM	±6 LSB

.

$$G\left(X\right)={{\displaystyle \sum }}_{i=0}^N g_i·X^i$$

(8)

Unfortunately, DEM suffers from the same limitations as a thermometer-coded DAC. The complexity and circuit area of these systems both increase strongly in line with the resolution. Hence, similar to the thermometer-coded DAC trade-off, in our design, the DEM was applied only over the first three MSB bits.

4. Noise Estimation

Usually, the SNR is calculated from the FFT measurement over several sinus periods. The SNR can be easily measured when the circuit is produced and tested. Unfortunately, when considering only simulation results, the data quantity needed for FFT calculation presents a critical issue. The following point can develop a faster SNR estimation methodology.

A second method consists of summing the various noise power contributions independently and then estimating the overall converter performance. The main limitation that was examined derived from the comparator input’s referred noise$\overline{n_{comp}}$, the capacitive array’s kT/C thermal noise $\overline{n_{th}}$ and noise from the reference buffers $\overline{n_{refP}}$ and $\overline{n_{refN}}$ (for the purposes of this study, the contribution of the power supply to the noise was not examined). The first noise estimation comes from the mathematical Equation (9). Each of these noise contributions was considered to follow a Gaussian distribution. To add all the noise contributions, the root sum square method was used.

$$\overline{n_{tot}}=\sqrt{n_{comp}^2+n_{th}^2+n_{refP}^2+n_{refN}^2}$$

(9)

A third method for estimating the total noise is to consider the output code dispersion while processing a constant input signal in a transient noise domain. The standard deviation of the output codes’ dispersion that was obtained directly correlates with the total noise. Knowing the total noise level, the SNR was then obtained using mathematical calculus (10):

$$SN{R}_{dB}=20·lo{g}_{10}\left(\frac{Input RMS signal}{\overline{n_{tot}}}\right)$$

(10)

As an example, the comparator noise can be considered around 0.82 LSB, the kT/C noise around 0.22 LSB, and other noise contributions to be null. The conversion of a sine wave and FFT calculation regarding our MATLAB model provided an SNR of 82.98 dB, which corresponds to a total noise of about 0.822 LSB. The second method, using Equation (9), allowed a mathematical estimation of about 0.849 LSB. Finally, Figure 14 displays the simulated output code dispersion for a 600.03 mV constant input. The standard deviation of the output code dispersion was about 0.83 LSB, whereas, considering Equation (9), $\overline{n_{tot}}$ was about 0.85 LSB.

These three methods have been simulated over different noise configurations, and the results converge to the same noise estimation for each test. Thus, the second and third methods allowed for a simple and fast noise estimation during the design phase without resorting to the FFT calculation, which requires a large number of samples.

5. Conclusions

In this paper, we propose a methodology for a high-resolution differential SAR ADC based on a segmented C-DAC. The method we present combines an automated mismatch calibration technique based on a trimming capacitor and a DEM algorithm that is applicable on thermometer-coded C-DAC to achieve a high resolution and compensate for mismatch errors while, at the same time, reducing the chip area. In addition, a MATLAB model was presented to illustrate the efficiency of the proposed algorithms. Thus, embedding these two algorithms simultaneously allows for a reduction in the worst-case INL from 28 LSB to 6 LSB when a mismatch of 2% is applied to each unit capacitor.

Secondly, a simple method for estimating the noise is presented. It is based on two fast simulations, owing to a mathematical equation applied to each noise source or the consideration of the output codes’ dispersion after a limited amount of simulation data. These two methods were in good agreement with the usual FFT method when applied to a MATLAB model. These methods make it possible to quickly estimate the SNR for an ADC during the design simulation phase without FFT processing, which, for a high-resolution converter, would require a significant amount of data.

Finally,

Table 2. ADC performance summary and comparison.

Reference	Technology (nm)	Resolution (bits)	Sampling Rate (MS/s)	SNDR (dB)	Total Power (µW)	FOM (fJ/Conv-step)
[35]	180	17	0.006	86.7	0.468	4.4
[36]	65	14	75	70.8	24,900	116.8
[37]	180	10	20	56.9	1230	107.2
[38]	40	13	40	69	591	6.4
[39]	40	8	900	33.4	700	20.3
[40]	40	10	100	56.3	1400	26.1
[41]	40	12	12	59.6	472	50.2
[42]	180	10	0.001	57.7	0.204	324.2
[43]	8	12	250	62	560	2.2
[44]	65	12	25	67.5	547	11.2
This work	65	15	0.2	(SNR *)79.9	30	18.5

* This SNR comes from simulations, following the method explained in Section 4.

presents the performance of SAR ADCs published in ISSCC and VLSI between 2017 and 2022. This represents so far the state of the art as described in [34]. In comparison to our ADC simulation results, the table firstly highlights the low power consumption results where we expect a total power dissipation of 30µW, including all contributing sources (DAC, comparators, switches, reference voltage, digital control, etc.). Secondly, from the SNR point of view, we listed the SNR as expected by front-end simulation using the method explained in Section 4. In terms of FOM, the expected performance for our ADC closely gets to the state of the art measurement results for a comparable resolution and technology node, except for [35]. At last, although not presented in the table, the differentiating feature for our ADC solution arises from die area occupation, which is expected to be intrinsically very small due to the use of a segmented DAC architecture.