Functional Converter for Intelligent Sensor and Its Layout Design ^†

Abstract

Recently, the number of cyber-physical systems and systems with embedded sensors has been increasing. In order to minimize the amount of information transmitted, a new paradigm is being developed that involves moving data processing as close as possible to the point of its generation. At the same time, there is a need to create devices that will provide computations near the sensors. The article considers an approach to the primary processing of a quasi-digital sensor signal. The authors show a variant of the organization of calculations in pulse form, based on the method of small increments. The method is focused on the usage of simple logical elements with the realization of a transfer function in the base of increment/decrement operations. The solution proposed by the authors is effective in terms of simplicity of hardware implementation and can be used to connect sensors with pulse output to digital processing systems. The considered circuit solutions can be used for the implementation in programmable logic device of different levels of complexity, as well as for the manufacture of the transducer in the form of a custom circuit.

1. Introduction

Recently, the number of cyber-physical systems and systems with embedded sensors is increasing. This leads to an increased load on the means of communication between such systems. To minimize the amount of information transferred, a new paradigm of edge computing is being developed. It implies moving data processing as close as possible to the point where it is received [1,2]. In the context of this paradigm, there is a need to develop special devices that provide computations near sensors. These should be compact, energy-efficient and fault-tolerant modules, which can be manufactured as separate chips or integrated with sensing elements in a single chip [3,4]. Hardware implementation of simple functional signal conversions is available in analog, digital, pulse, and mixed formats. Obviously, performing calculations in the formats of signals obtained at the outputs of sensitive elements will allow us to avoid additional operations related to format conversions. Sensors often generate a frequency output signal [5,6]. Also, analog-to-frequency converters can be installed in chips of sensors with an analog output [7,8]. The frequency output signal can be represented as a stream of pulses [9] or pulse-width modulated (PWM) signals [10]. In a pulse stream, the carrier of information is the number of pulses per unit time. In a PWM signal, the information is associated with the relative duration of the pulses. In both cases, the amplitude of the signals is the same and can be considered as logic level “1”. The considered pulse forms of signal representation, also called bit-stream, allow the application of digital logic elements for primary data processing. In this case, programmable logic-integrated circuits of various levels of complexity can be used as the element base for the implementation of near-sensor computing modules [11,12]. In some cases, it is economically justified to manufacture the sensor signal primary converters in the form of application-specific integrated circuits (ASICs) [13]. If silicon technology allows, the sensing element, analog-to-frequency converter and modules for primary computation can be integrated in a single silicon chip. In both the FPGA basis and the ASIC implementation, various functional transformations can be performed. This can be realized by integrating various signal processing circuits for data reception, primary converters, digital signal processing circuits, memory, and nodes for wired or wireless communication. As a result of this integration, there will be a sensor-on-chip system, such as [14]. Based on the above facts, we can conclude that the development of digital hardware modules that process pulse signals and provide a connection between the pulse output of the sensor and the input of the digital information processing system is factual. In this paper, we focus on a new approach to the organization of calculations in a digital PWM signal converter. The traditional approach to signal processing implies conversion of analog or pulse signal into digital form with subsequent calculations using traditional units (adders, multipliers, dividers, etc.) or using a microcontroller, as shown in [15]. In the proposed transducer, all operations are performed in pulse form on the basis of simple logic elements, binary counters and registers, and the multiplication and division operation of pulse signals is implemented in the basis of operations “+1” and “−1”. The proposed solution is effective in terms of simplicity of hardware implementation and can be used to connect sensors with pulse output to digital processing systems.

2. Design of the Converter

Transformations of pulse signals from sensors can be performed in different ways. Let us consider the implementation of the converter, for example, for a temperature sensor, which forms a signal in PWM form. This signal is formed by a semiconductor sensing element and is digitized with a first-order sigma–delta modulator. The output signal is a periodic signal represented by time intervals $T_1$ (high level) and $T_2$ (low level). The conversion function of the temperature sensor is as follows:

$${\displaystyle T\left({}^{\circ }\mathrm{C}\right)=a_1+a_2\frac{T_1}{T_2}.}$$

(1)

where $a_1$ and $a_2$ are constants determined by the sensor model.

2.1. Implementation Based on Traditional Calculations

The sensor output signal is quasi-digital and can be processed by digital elements. Sensor manufacturers recommend two approaches to temperature calculation based on the parameters of the output signal [15]. Firstly, it can be a software implementation oriented to the usage of the microcontrollers. Most microcontrollers allow direct connection of sensitive elements, forming a quasi-digital output signal, to the input ports. Using a microcontroller allows you to implement simple, inexpensive solutions, but errors in the result may occur. The source of such errors is software-dependent effects. The analysis and options for compensating such effects are given in [16]. Secondly, the transformations can be performed by hardware using typical computing units. The schematic recommended by the manufacturer of a temperature sensor with output characteristic (1) is given in [15]. The circuit measures the duration of the output single signals from the sensor with a resolution of ±1 µs. For this purpose, a cascade connection of 8-bit counters is used. The counters start with the rising edge of the sensor signal and count clock pulses from an external 1 MHz oscillator. The counting results are stored in the output registers. The falling edge of the signal from the sensor forms the reset signal for the counters. After that, they start counting the next output phase—the duration of the zero value of the sensor output signal. The calculated value at the beginning of the new period is also stored in the registers. Then, the obtained values $T_1$ and $T_2$ are used to calculate the temperature by hardware or to transmit it to the software computing core.

2.2. Implementation Based on the Method of Small Increments

Consider the pulse stream implementation of expression (1). A schematic of the n-digit device realizing this operation is shown in Figure 1a. A reference pulse stream is sent to the input F and the generator G forms n reference pulse streams based on the F. Generation of reference pulse streams is performed as follows (Figure 1b). Each pulse of the F stream increases the value of the CT counter by one. At the same time, one of the outputs of this counter switches from the state “0” to “1”. The only exception is the counter change from the state “all ones” to the state “all zeros”, when none of the outputs switch from “0” to “1”. The output signals of the counter are used as clock signals for the triggers T. In these triggers, a one is written when a rising edge occurs at the counter output. Obviously, for every F-flow pulse a one is written to no more than one trigger. After the falling edge of the F-flow pulse all triggers are reset. Thus, the sum of pulses in all generated streams is equal to $2^n-1$ during the device operation period.

The average frequencies of $P_i$ streams over the period of device operation are determined as follows:

$$P_i=\frac{F}{2^n}{2}^{n-i-1}$$

where i∈ [0 : n – 1].

Logic elements ${\&}_0$ – ${\&}_{n-1}$, connected to the outputs of generator G, implement the function of multiplication of streams $P_i$ by bits of binary code N. The resulting streams are summed by the OR logic element. The logic expression for the output of this element is as follows:

$$F_{OR1}=L_0\vee L_1\vee L_2\cdots L_{n-1}.$$

The function L in the general case for each i-th input of element OR1 is formed on the corresponding elements of ${\&}_i$:

$$L_i=N_{1_{n-i-1}}{P}_i{2}^{-n},$$

where $N_{1_{n-i-1}}$ is the logical state of the n-i-1 digit of the code $N_1$; $P_i$ is the pulse stream from the generator G output.

The pulse streams at the outputs of elements ${\&}_0$ – ${\&}_{n-1}$ have the following frequencies:

$$L_0=N_{1_{n-1}}{P}_0,L_1=N_{1_{n-2}}{P}_1,L_2=N_{1_{n-3}}{P}_2,\dots ,L_{n-1}=N_{1_0}{P}_{n-1}.$$

The total value of the frequency $F_{OR1}$ at the output of the OR1 element is determined as follows:

$$\begin{array}{c}{F}_{OR1}=N_{1_{n-1}}{P}_0+N_{1_{n-2}}{P}_1+N_{1_{n-3}}{P}_2+\cdots +N_{1_0}{P}_{n-1}=\hfill \\ F_2^{-n}\left(N_{1_{n-1}}{2}^{n-1}+N_{1_{n-2}}{2}^{n-2}+N_{1_{n-3}}{2}^{n-3}+\cdots +N_{1_0}{2}^0\right).\hfill \end{array}$$

In this expression, the sum of the products of the current code bit $N_{1_i}$ by the weight of the n-bit code bit is the binary code $N_1$. Thus, the average frequency of the pulse stream at the output of the OR1 logic element can be written as follows:

$$F_{OR1}=\frac{F}{2^n}{N}_1$$

Similarly, the value of frequencies $F_{OR2}$ and $F_{OR3}$ at the outputs of elements OR2 and OR3, respectively, is determined as:

$$F_{OR2}=\frac{F}{2^n}{N}_2\mathrm{and}{F}_{OR3}=\frac{F}{2^n}{N}_{out}$$

Consider the operation of the converter shown in Figure 1a. Let the initial moment of time zero code be stored in the counter and register, i.e., $N_{out}=0$. At digital inputs $N_1$ and $N_2$, the binary codes corresponding to constants $a_1$ and $a_2$ of Equation (1) are set. The reference pulse stream is supplied to input F; the PWM signal from the sensor output is received at input $T_1$. Elements $1_1$ and $1_2$, under the influence of codes $N_1$ and $N_2$, form the streams $F_{OR1}$ and $F_{OR2}$. During the first period, as long as the input $T_1$ holds signal value “1”, the stream $F_{OR2}$ passes through the element ${\&}_{2_2}$ and $1_4$ to the counter input marked as “−”. When the value at input $T_1$ becomes zero, the stream $F_{OR2}$ is blocked. At this time, the stream $F_{OR1}$ starts flowing through element ${\&}_{2_1}$ to the counter input marked “+”. The stream $F_{OR3}$ is not generated because of the zero code $N_{out}$. When the signal “1” appears on the input of $T_1$ again, the counted number of pulses from the counter CT is rewritten into the register RG. While $T_1=1$ at the counter input “−” the stream $F_{OR2}$ passes, when $T_1$ = 0 at the counter input “+” the stream $F_{OR1}$ passes, and at the counter input “−” the $F_{OR3}$ stream is formed on the basis of the zero code $N_{out}=0$. Negative feedback is used in the device, and as a result, the dynamic equilibrium mode is reached. In this mode, the number of pulses coming to the adding $N_{+}$ and subtracting $N_{-}$ inputs of the counter CT during the period T is the same, i.e.,

$$N_{-}=N_{+}\mathrm{or}{\overline{F}}_{-}={\overline{F}}_{+}$$

(2)

where ${\overline{F}}_{+}$ and ${\overline{F}}_{-}$ are the average values of pulse flux frequencies at the counter inputs “−” and “+”, respectively.

The “+” counter input receives pulses during the device’s operating period T. The number of pulses is determined by the following expression:

$$F_{+}=F_{OR1}{T}_2=\frac{F}{2^n}{N}_1{T}_2.$$

(3)

The number of pulses that come to the input of the counter “−” during the period of operation of the device T is calculated as follows:

$$F_{-}=T_1{F}_{OR2}+T_2{F}_{OR3}=\frac{F}{2^n}\left(T_1{N}_2+T_2{N}_{out}\right)$$

(4)

In the dynamic equilibrium mode, the characteristic (2) with regard to (3) and (4) will have the following form:

$$\frac{F}{2^n}{N}_1{T}_2=\frac{F}{2^n}\left(T_1{N}_2+T_2{N}_{out}\right)$$

From the last expression, we get the equation:

$$N_{out}=N_1-N_2\frac{T_1}{T_2}$$

That is, the characteristic of the device corresponds to the function of the sensor.

3. Converter Implementation

To study the functioning of the proposed circuit, we developed a description of the device in VerilogHDL.

3.1. Simulation of the Converter

The input signals for the program are the reference frequency signal F and the input signal T consisting of two parts: $T_1$ and $T_2$. For the correct operation of the model, an additional reset signal is used to ensure that the counters and registers are set to a zero state. However, given that the device has a steady state and always tends to it, it can start from any random state, so the reset signal is optional. The input signals for the program are the reference frequency signal F and the input signal T, consisting of two parts: $T_1$ and $T_2$. For the correct operation of the model, an additional reset signal is used to ensure that the counters and registers are set to a zero state. However, given that the device has a steady state and always tends to it, it can start from any random state, so the reset signal is optional. The constants in the implemented expression are set at the stage of synthesis; in the program, they are described as parameters. When creating a universal device, additional digital inputs can be provided for these constants. Figure 2 shows the operation of the device configured to process the signal from the AD TMP03 temperature sensor.

The diagram shows the transient process, during which the transducer reaches the equilibrium mode. Starting from the fifth period of the input signal $T_1$, the transducer keeps the output code unchanged. This code is the result of the execution of transformations. At the moment of 14.243 ns, an interference occurs, which leads to a shortening of the signal duration $T_1$. After three periods, the converter returns to the equilibrium mode, compensating for the failure by triggering the feedback.

3.2. Custom Circuit Design

Despite the fact that the layout design of elements such as registers, counters, or logic primitives is quite well developed, research on topology optimization continues. This research is related to the search for original solutions in order to optimize the chip area, power and speed [17,18]. When minimizing the circuit layout design, we are looking for solutions that minimize the main component of pulse stream information processing devices—the binary counter. Solutions based on the principle of “first-zero search” are proposed. The circuit diagram of the counter cell based on the “first zero search” principle is shown in Figure 3. Its current–discharge inversion control circuit is built on pass-through keys (as in Manchester adder transfer circuits). The cells are combined into four-digit sections with an inverter at the input and at the output. At the input of each i-th bit from the previous one comes the $INV\_IN\_i$ signal to invert the value of the current bit. If the inversion control signal is changed, the pass-through key in the circuit is opened. This cuts off the low-order bits and generates a new $INV\_OUT\_i$ control signal value (cancelling the inversion of the current bit) in the cell. This value is sent to the next (high) counter digit.

The considered circuit solution provides not only high speed and low hardware costs, but also a linear dependence of the delay time and on-chip area on the bit resolution of the device. Moreover, if necessary, the proposed circuit solution can significantly increase the speed of circuits with a relatively small increase in the area on the chip. Figure 4 shows an example of topological implementation of the converter considered above (Figure 1) for 4-bit data. Matrixing of the presented topology along the ordinate axis with an appropriate matrixing coefficient makes it possible to obtain a device of the required digit capacity (a multiple of four). The topology was developed using the original computer-aided design tools [19] in a technologically invariant concept, which allows the design to be adjusted to the design and technological requirements of the chosen manufacturing enterprise.

From the presented material, we can see that the implementation of such calculators in the form of independent fragments of integrated circuits is compact and simple. In addition, it has greater speed than devices based on universal computing units.

4. Conclusions

A large number of sensors provide information in pulse form. This is due to the simplicity of obtaining a pulse signal at the output of the sensing element, as well as the following advantages of the pulse form:

• Energy efficiency of the presence of pauses between pulses, which reduces the average power consumption;
• High reliability of information transmission by a stream of pulses, since the loss of one pulse when transmitting a number of pulses is equivalent to the loss of one low-order bit of the binary code, while the loss of a pulse when transmitting a binary code, even in sequential format, is equivalent to the loss of a value with the weight $2^k$, where k is a bit number in the binary code.

In this paper, we proposed a new method of functional processing of pulse streams based on elementary logical and arithmetic operations (increment/decrement) and implemented using simple digital elements: logic primitives, counters and registers without using an adder, multiplier, divider or other complex nodes. The considered device provides division of PWM signals directly in pulse form without additional conversion into digital binary codes. This device can be implemented based on PLD and used as an interface for sensors that generate PWM output signal and require multiplying and dividing operations. Small corrections will allow the proposed structure to be used to process signals of a large number of existing quasi-digital sensors with frequency and pulse-width modulated outputs, which are available at the moment.