Microarchitectural Malware Detection via Translation Lookaside Buffer (TLB) Events
Abstract
1. Introduction
- A methodology for integrating both benign and malicious programs into a controlled experimental environment for capturing relevant microarchitectural data.
- A data collection and analysis process that excludes traditional timing based techniques, such as memory access latency or task execution duration.
- A TLB-only approach that applies statistical learning models and neural networks to classify benign and malicious activity, achieving classification accuracies of up to 81% for setup (1), 72% for setup (2), and 61% for setup (3).
2. Background
2.1. TLB Operation Overview
2.2. Traditional Time-Based TLB Techniques
2.3. Models Approach
2.3.1. Statistical Learning Models
2.3.2. Neural Networks
2.3.3. eXtreme Gradient-Boosting (XGBoost)
2.3.4. Light Gradient-Boosting Machine (LightGBM)
2.3.5. Voting Classifier
2.4. Related Work
2.4.1. Hyper-Threading, HPC Based Malware Detection, and Co-Residency Classification
2.4.2. Prior Work on TLB Attacks
2.4.3. Prior Work on TLB Defense
2.5. Additional Related Work
2.5.1. TLB Coalescing with a Range-Compressed Page Table for Embedded I/O Devices
2.5.2. HyPer-Early Detection of a Ransomware Attack Using Hardware Performance Counters
2.5.3. RanStop: A Hardware-Assisted Runtime Crypto-Ransomware Detection Technique
2.5.4. Intelligent Malware Detection Based on Hardware Performance Counters: A Comprehensive Survey
2.5.5. Redefining Trust: Assessing the Reliability of Machine Learning Algorithms in Intrusion Detection Systems
2.5.6. Cyber-Immunity at the Core: Securing Biomedical Devices Through Hardware-Level Machine Learning Defense
2.5.7. Stochastic-HMD: Adversarial-Resilient Hardware Malware Detector via Undervolting
2.5.8. Obfuscation-Resistant Hardware Malware Detection: A Stacked Denoising Autoencoder Approach
3. Methodology
3.1. Materials and Instrumentation
3.1.1. Experimental Design
3.1.2. Data Description
3.1.3. Workflow
3.2. Implementation Details: Python and C Programs, and Shell Scripts
3.3. Augmented Framework
3.3.1. data_tlb.py
3.3.2. cryptominer.py
3.3.3. infector.py
3.3.4. network_scanner.py
3.3.5. ransomware.py
3.3.6. rootkit.py
3.4. Preprocessing and Analysis
- Task: the program to be classified, either one of the five benign benchmarks or one of the five malware scripts.
- Configuration: the core configuration and sensor combination used during execution.
- Run: identification of each of the 500 runs per configuration-task combination.
- Time: time steps at 5 ms intervals over a 0.5 s duration.
- Counts: The number of counts recorded per HPC event.
- Events: The four TLB events measured.
- T0–T3: timestamps for key events, T0 (task start), T1 (counter start), T2 (task end), T3 (counter end).
3.5. Augmented Prior Learning Models
- Logistic Regression—implemented in Python, 80/20 train–validation split, evaluated on all 15 combinations of four performance counters.
- Random Forest (RF)—same setup as logistic regression.
- Artificial Neural Network (ANN)—three hidden layers (128, 64, 16 ReLU units), softmax output, multi-class classification.
- Convolutional Neural Network (CNN)—three-dimensional reshaped inputs, kernel (2, 3, 1), global average pooling, dense layers, padding by duplicating final row.
- XGBoost (Appendix A.8).
- LightGBM (Appendix A.9).
- Voting Classifier (Appendix A.10).
3.6. Limitations
- TLB Mapping Functions: The manner in which virtual addresses are mapped to TLB sets and ways differs across Instruction Set Architectures (ISAs) and microarchitectures. This impacts both the observability and interpretability of TLB behavior, and thus affects feature extraction and side-channel signal quality.
- HPC Event Semantics: The availability and definition of TLB related HPC events vary across vendors. Events that are effective for classification on Intel processors may be absent, renamed, or behave differently on AMD, ARM, or RISC-V architectures.
- Access Restrictions: Some operating systems impose restrictions on user-level access to HPCs, limiting data collection. These access policies can vary across platforms and distributions, which further complicates methodology portability.
4. Results
4.1. Statistical Learning Model Performance
4.1.1. Binary Classifier
4.1.2. Multi-Task Four-Way Classifier
4.1.3. Multi-Task 10-Way Classifier
4.2. Comparing Classifiers
- : Cohen’s Kappa.
- : Observed accuracy.
- : Expected (baseline).
4.3. Comparison with Related Work
5. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Acknowledgments
Conflicts of Interest
Appendix A. Listings
Appendix A.1. experiment.py Program
- Listing A1. Changes to experiment.py.
Appendix A.2. Data TLB Linear Mapping C Program
- Listing A1. Data TLB Linear Mapping C program [10].
Appendix A.3. Simulated cryptominer.py Program
- Listing A3. Simulated cryptominer.py.
Appendix A.4. Simulated infector.py Program
- Listing A4. simulated infector.py.
Appendix A.5. Simulated network_scanner.py Program
- Listing A5. Simulated network_scanner.py.
Appendix A.6. Simulated ransomware.py Program
- Listing A6. Simulated ransomware.py.
Appendix A.7. Simulated rootkit.py Program
- Listing A7. Simulated rootkit.py.
Appendix A.8. XGBoost Program
- Listing A8. XGBoost.
Appendix A.9. LightGBM Program
- Listing A9. lightGBM.
Appendix A.10. Voting Classifier Program
- Listing A10. Voting Classifier.
References
- Hennessy, J.L.; Patterson, D.A. Computer Architecture: A Quantitative Approach, 6th ed.; Morgan Kaufmann Publishers Inc.: San Francisco, CA, USA, 2017. [Google Scholar]
- Disselkoen, C.; Kohlbrenner, D.; Porter, L.; Tullsen, D. Prime+Abort: A Timer-Free High-Precision L3 Cache Attack Using Intel TSX. In Proceedings of the 26th USENIX Security Symposium (USENIX Security 17), Vancouver, BC, Canada, 16–18 August 2017. [Google Scholar]
- Kocher, P.; Genkin, D.; Gruss, D.; Haas, W.; Hamburg, M.; Lipp, M.; Mangard, S.; Prescher, T.; Schwarz, M.; Yarom, Y. Spectre attacks: Exploiting speculative execution. Commun. ACM 2020, 63, 93–101. [Google Scholar] [CrossRef]
- Lipp, M.; Schwarz, M.; Gruss, D.; Prescher, T.; Haas, W.; Horn, J.; Mangard, S.; Kocher, P.; Genkin, D.; Yarom, Y.; et al. Meltdown: Reading kernel memory from user space. Commun. ACM 2020, 63, 46–56. [Google Scholar] [CrossRef]
- Liu, F.; Yarom, Y.; Ge, Q.; Heiser, G.; Lee, R.B. Last-level cache side-channel attacks are practical. In Proceedings of the 2015 IEEE Symposium on Security and Privacy (SP), San Jose, CA, USA, 17–21 May 2015; pp. 605–622. [Google Scholar]
- Yarom, Y.; Falkner, K. Flush+ Reload: A High Resolution, Low Noise, L3 Cache Side-Channel Attack. In Proceedings of the USENIX Security Symposium, San Diego, CA, USA, 20–22 August 2014; pp. 719–732. [Google Scholar]
- Percival, C. Cache missing for fun and profit. In Proceedings of the Free BSD Presentations and Papers (2005), Ottawa, ON, Canada, 13–14 May 2005. [Google Scholar]
- Osvik, D.A.; Shamir, A.; Tromer, E. Cache Attacks and Countermeasures: The Case of AES. In Topics in Cryptology—CT-RSA 2006; Hutchison, D., Kanade, T., Kittler, J., Kleinberg, J.M., Mattern, F., Mitchell, J.C., Naor, M., Nierstrasz, O., Pandu Rangan, C., Steffen, B., et al., Eds.; Springer: Berlin/Heidelberg, Germany, 2006; Volume 3860, pp. 1–20. [Google Scholar] [CrossRef]
- Gullasch, D.; Bangerter, E.; Krenn, S. Cache Games–Bringing Access-Based Cache Attacks on AES to Practice. In Proceedings of the Security and Privacy (SP), 2011 IEEE Symposium On, Oakland, CA, USA, 22–25 May 2011; pp. 490–505. [Google Scholar]
- Agredo, C.; Koranek, D.F.; Kabban, C.M.S.; Arroyo, J.A.G.D.; Langehaug, T.J.; Graham, S.R. Exploring the Translation Lookaside Buffer (TLB) for Low-Level Task Differentiation and Classification. IEEE Access 2025, 13, 111199–111216. [Google Scholar] [CrossRef]
- Braun, B.A.; Jana, S.; Boneh, D. Robust and efficient elimination of cache and timing side channels. arXiv 2015, arXiv:1506.00189. [Google Scholar] [CrossRef]
- Gruss, D.; Schuster, F.; Ohrimenko, O.; Haller, I.; Lettner, J.; Costa, M. Strong and efficient cache side-channel protection using hardware transactional memory. In Proceedings of the 26th USENIX Security Symposium (USENIX Security 17), Vancouver, BC, Canada, 16–18 August 2017. [Google Scholar]
- Liu, F.; Ge, Q.; Yarom, Y.; Mckeen, F.; Rozas, C.; Heiser, G.; Lee, R.B. Catalyst: Defeating last-level cache side channel attacks in cloud computing. In Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), Barcelona, Spain, 12–16 March 2016; pp. 406–418. [Google Scholar]
- Sprabery, R.; Evchenko, K.; Raj, A.; Bobba, R.B.; Mohan, S.; Campbell, R.H. A novel scheduling framework leveraging hardware cache partitioning for cache-side-channel elimination in clouds. arXiv 2017, arXiv:1708.09538. [Google Scholar]
- Gras, B.; Razavi, K.; Bos, H.; Giuffrida, C. Translation Leak-aside Buffer: Defeating Cache Side-channel Protections with TLB Attacks. In Proceedings of the USENIX Security Symposium, USENIX, Baltimore, MD, USA, 15–17 August 2018; pp. 955–972. [Google Scholar]
- Holmes, N. Not Lost in Translation: Implementing Side Channel Attacks Through the Translation Lookaside Buffer. Master’s Thesis, Department of Computer Science, University of Warwick, Coventry, UK, 2023. [Google Scholar]
- Hill, J.E.; Walker, T.O., III; Blanco, J.A.; Ives, R.W.; Rakvic, R.; Jacob, B. Ransomware Classification Using Hardware Performance Counters on a Non-Virtualized System. IEEE Access 2024, 12, 63865–63878. [Google Scholar] [CrossRef]
- Anand, P.M.; Charan, P.V.S.; Shukla, S.K. HiPeR—Early Detection of a Ransomware Attack using Hardware Performance Counters. Digit. Threat. Res. Pract. 2023, 4, 43. [Google Scholar] [CrossRef]
- Pundir, N.; Tehranipoor, M.; Rahman, F. RanStop: A Hardware-assisted Runtime Crypto-Ransomware Detection Technique. arXiv 2020, arXiv:2011.12248. [Google Scholar]
- Sayadi, H.; He, Z.; Makrani, H.M.; Homayoun, H. Intelligent Malware Detection based on Hardware Performance Counters: A Comprehensive Survey. In Proceedings of the 25th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 3–5 April 2024. [Google Scholar] [CrossRef]
- Langehaug, T.; Borghetti, B.; Graham, S. Classifying Co-resident Computer Programs Using Information Revealed by Resource Contention. Digit. Threat. Res. Pract. 2023, 4, 1–29. [Google Scholar] [CrossRef]
- Stallings, W. Operating Systems: Internals and Design Principles; Pearson: San Antonio, TX, USA, 2014. [Google Scholar]
- Agredo, C.; Langehaug, T.J.; Graham, S.R. Inferring TLB Configuration with Performance Tools. J. Cybersecur. Priv. 2024, 4, 951–971. [Google Scholar] [CrossRef]
- Chollet, F. Deep Learning with Python; Manning Publications Co.: Shelter Island, NY, USA, 2018; p. 4. [Google Scholar]
- Shrivastava, A. COMP 642—Machine Learning Lecture 5: Deep Learning: Logistic Regression. Online, 2022. Scribed by Kristina Sanclemente, James Kafer, Tess Houlette, and Sarah McDonnell. Available online: https://www.cs.rice.edu/~as143/COMP642Spring22/Scribes/Lect5 (accessed on 9 January 2025).
- Breiman, L. Random Forests. Mach. Learn. 2001, 45, 5–32. [Google Scholar] [CrossRef]
- Rumelhart, D.E.; Hinton, G.E.; Williams, R.J. Learning Representations by Back-Propagating Errors. Nature 1986, 323, 533–536. [Google Scholar] [CrossRef]
- Cireșan, D.C.; Meier, U.; Masci, J.; Gambardella, L.M.; Schmidhuber, J. Flexible, High Performance Convolutional Neural Networks for Image Classification. In Proceedings of the Twenty-Second International Joint Conference on Artificial Intelligence (IJCAI), Barcelona, Spain, 16–22 July 2011; pp. 1237–1242. [Google Scholar]
- Wiesel, T.N.; Hubel, D.H. Receptive fields of single neurones in the cat’s striate cortex. J. Physiol. 1959, 148, 574–591. [Google Scholar] [CrossRef]
- Chen, T.; Guestrin, C. XGBoost: A Scalable Tree Boosting System. In Proceedings of the 22nd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining (KDD), San Francisco, CA, USA, 13–17 August 2016; pp. 785–794. [Google Scholar] [CrossRef]
- Ke, G.; Meng, Q.; Finley, T.; Wang, T.; Chen, W.; Ma, W.; Ye, Q.; Liu, T.Y. LightGBM: A Highly Efficient Gradient Boosting Decision Tree. In Proceedings of the 31st International Conference on Neural Information Processing Systems (NeurIPS), Long Beach, CA, USA, 4–9 December 2017; pp. 3146–3154. [Google Scholar]
- Marr, D.T.; Hinton, G.; Koufaty, D.A.; Miller, J.A. Hyper-Threading Technology Architecture and Microarchitecture. Intel Technol. J. 2002, 6, 1. [Google Scholar]
- Das, S.; Werner, J.; Antonakakis, M.; Polychronakis, M.; Monrose, F. SoK: The Challenges, Pitfalls, and Perils of Using Hardware Performance Counters for Security. In Proceedings of the 2019 IEEE Symposium on Security and Privacy (SP), San Francisco, CA, USA, 19–23 May 2019; pp. 20–38. [Google Scholar] [CrossRef]
- Zeraatkar, A.A.; Kamran, P.S.; Kaur, I.; Ramu, N.; Sheaves, T.; Al-Asaad, H. On the Performance of Malware Detection Classifiers Using Hardware Performance Counters. In Proceedings of the 2024 International Conference on Smart Applications, Communications and Networking (SmartNets), Harrisonburg, VA, USA, 28–30 May 2024; pp. 1–6. [Google Scholar]
- Tatar, A.; Trujillo, D.; Giuffrida, C.; Bos, H. TLB;DR: Enhancing TLB-based Attacks with TLB Desynchronized Reverse Engineering. In Proceedings of the 2020 IEEE Symposium on Security and Privacy (SP), San Francisco, CA, USA, 18–21 May 2020; DR, 21 May 2020; pp. 1273–1290. [Google Scholar]
- Dutta, S.B.; Naghibijouybari, H.; Gupta, A.; Abu-Ghazaleh, N.; Marquez, A.; Barker, K. Spy in the GPU-box: Covert and Side Channel Attacks on Multi-GPU Systems. In Proceedings of the 50th Annual International Symposium on Computer Architecture, Orlando, FL, USA, 17–21 June 2023; pp. 1–13. [Google Scholar]
- Nayak, A.; Ganapathy, V.; Basu, A. (Mis) Managed: A Novel TLB-based Covert Channel on GPUs. In Proceedings of the 2021 ACM Asia Conference on Computer and Communications Security, Hong Kong, 7–11 June 2021; pp. 872–885. [Google Scholar]
- Deng, S.; Xiong, W.; Szefer, J. Secure TLBs. In Proceedings of the 46th International Symposium on Computer Architecture, Phoenix, AZ, USA, 22–26 June 2019; pp. 346–359. [Google Scholar]
- Costan, V.; Lebedev, I.A.; Devadas, S. Sanctum: Minimal Hardware Extensions for Strong Software Isolation. In Proceedings of the USENIX Security Symposium, Austin, TX, USA, 10–12 August 2016; pp. 857–874. [Google Scholar]
- Intel. IA-32 Architectures Software Developer’s Manual. Syst. Program. Guide 2016, 64, 64. [Google Scholar]
- Stolz, F.; Thoma, J.P.; Güneysu, T.; Sasdrich, P. Risky Translations: Securing TLBs against Timing Side Channels. In Proceedings of the Conference on Computer and Communications Security; Horst Görtz Institute for IT Security, Ruhr University Bochum: Bochum, Germany, 2024. [Google Scholar]
- Duong, T.D.; Kim, Y.S.; Hur, J.Y. TLB Coalescing with Range Compressed Page Table for Embedded I/O Devices. IEEE Access 2025, 13, 12623–12633. [Google Scholar] [CrossRef]
- Sayadi, H.; He, Z.; Miari, T.; Aliasgari, M. Redefining Trust: Assessing Reliability of Machine Learning Algorithms in Intrusion Detection Systems. In Proceedings of the 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, 19–22 May 2024. [Google Scholar] [CrossRef]
- Islam, M.S.; Alouani, I.; Khasawneh, K.N. Stochastic-HMDs: Adversarial-Resilient Hardware Malware Detectors via Undervolting. In Proceedings of the 2023 60th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 9–13 July 2023. [Google Scholar] [CrossRef]
- Luk, C.K.; Cohn, R.; Muth, R.; Patil, H.; Klauser, A.; Lowney, G.; Wallace, S.; Reddi, V.J.; Hazelwood, K. Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Chicago, IL, USA, 12–15 June 2005; ACM SIGPLAN Notices. Volume 40, pp. 190–200. [Google Scholar] [CrossRef]
- He, Z.; Fernandes, C.W.; Sayadi, H. Obfuscation-Resistant Hardware Malware Detection: A Stacked Denoising Autoencoder Approach. In Proceedings of the 2025 Research Gate. IEEE; 2025. Available online: https://www.researchgate.net/publication/390842933 (accessed on 10 September 2025).
- Linux Kernel Organization. Perf—A Performance Counting Tool. 2024. Available online: https://perf.wiki.kernel.org/index.php/Main_Page (accessed on 11 January 2024).
- EEMBC. CoreMark-Pro. GitHub Repository. 2025. Available online: https://github.com/eembc/coremark-pro (accessed on 10 September 2025).
- PerfWiki. Counting with Perf Stat. Available online: https://perfwiki.github.io/main/tutorial/#counting-with-perf-stat (accessed on 5 January 2025).
- Weaver, V.M.; Terpstra, D.; Moore, S. Non-Determinism and Overcount on Modern Hardware Performance Counter Implementations. In Proceedings of the 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX, USA, 21–23 April 2013; pp. 215–224. [Google Scholar]
Core Configurations | Programs (Sensors) | |||
---|---|---|---|---|
Only Counters | Benign | TLB Active | Both | |
Same Logical | A1 | B1 | C1 | D1 |
SMT | A2 | B2 | C2 | D2 |
Different Physical | A3 | B3 | C3 | D3 |
Hybrid | A4 | B4 | C4 | D4 |
Counter1 | Counter2 | Counter3 | Counter4 | ANN | Voting Classifier |
---|---|---|---|---|---|
x | x | x | x | 0.7468 | 0.8108 |
x | x | x | 0.7475 | 0.7957 | |
x | x | x | 0.7636 | 0.7987 | |
x | x | x | 0.7477 | 0.7859 | |
x | x | x | 0.7753 | 0.8023 | |
x | x | 0.7313 | 0.7893 | ||
x | x | 0.7204 | 0.7793 | ||
x | x | 0.7342 | 0.7735 | ||
x | x | 0.7314 | 0.7862 | ||
x | x | 0.7583 | 0.7904 | ||
x | x | 0.7281 | 0.7888 | ||
x | 0.6971 | 0.7476 | |||
x | 0.7306 | 0.7518 | |||
x | 0.6759 | 0.7336 | |||
x | 0.7081 | 0.7642 |
Counter1 | Counter2 | Counter3 | Counter4 | ANN | Voting Classifier |
---|---|---|---|---|---|
x | x | x | x | 0.6324 | 0.7236 |
x | x | x | 0.6084 | 0.7138 | |
x | x | x | 0.6628 | 0.7061 | |
x | x | x | 0.6148 | 0.7003 | |
x | x | x | 0.6509 | 0.721 | |
x | x | 0.5974 | 0.6912 | ||
x | x | 0.5784 | 0.6723 | ||
x | x | 0.6288 | 0.6724 | ||
x | x | 0.645 | 0.7106 | ||
x | x | 0.6359 | 0.7063 | ||
x | x | 0.6112 | 0.6948 | ||
x | 0.5827 | 0.6493 | |||
x | 0.6154 | 0.665 | |||
x | 0.5154 | 0.6163 | |||
x | 0.5700 | 0.6559 |
Counter1 | Counter2 | Counter3 | Counter4 | ANN | Voting Classifier |
---|---|---|---|---|---|
x | x | x | x | 0.5079 | 0.6103 |
x | x | x | 0.4934 | 0.59222 | |
x | x | x | 0.4714 | 0.5917 | |
x | x | x | 0.4693 | 0.5785 | |
x | x | x | 0.5051 | 0.6048 | |
x | x | 0.4594 | 0.5666 | ||
x | x | 0.3897 | 0.5169 | ||
x | x | 0.4458 | 0.5429 | ||
x | x | 0.4899 | 0.5844 | ||
x | x | 0.4861 | 0.5846 | ||
x | x | 0.4467 | 0.5594 | ||
x | 0.4059 | 0.5166 | |||
x | 0.4531 | 0.5224 | |||
x | 0.3573 | 0.4428 | |||
x | 0.3799 | 0.4836 |
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Share and Cite
Agredo, C.; Koranek, D.F.; Kabban, C.M.S.; Arroyo, J.A.G.d.; Graham, S.R. Microarchitectural Malware Detection via Translation Lookaside Buffer (TLB) Events. J. Cybersecur. Priv. 2025, 5, 75. https://doi.org/10.3390/jcp5030075
Agredo C, Koranek DF, Kabban CMS, Arroyo JAGd, Graham SR. Microarchitectural Malware Detection via Translation Lookaside Buffer (TLB) Events. Journal of Cybersecurity and Privacy. 2025; 5(3):75. https://doi.org/10.3390/jcp5030075
Chicago/Turabian StyleAgredo, Cristian, Daniel F. Koranek, Christine M. Schubert Kabban, Jose A. Gutierrez del Arroyo, and Scott R. Graham. 2025. "Microarchitectural Malware Detection via Translation Lookaside Buffer (TLB) Events" Journal of Cybersecurity and Privacy 5, no. 3: 75. https://doi.org/10.3390/jcp5030075
APA StyleAgredo, C., Koranek, D. F., Kabban, C. M. S., Arroyo, J. A. G. d., & Graham, S. R. (2025). Microarchitectural Malware Detection via Translation Lookaside Buffer (TLB) Events. Journal of Cybersecurity and Privacy, 5(3), 75. https://doi.org/10.3390/jcp5030075