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Proceeding Paper

Low-Power Pedestrian Detection System on FPGA †

Department of Microelectronics and Electronic Systems, School of Engineering, Autonomous University of Barcelona, 08193 Bellaterra, Spain
Author to whom correspondence should be addressed.
Presented at the 13th International Conference on Ubiquitous Computing and Ambient Intelligence UCAmI 2019, Toledo, Spain, 2–5 December 2019.
Proceedings 2019, 31(1), 35;
Published: 20 November 2019


Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection. Many research works focused on accelerating HOG algorithm on FPGA (Field-Programmable Gate Array) due to its low-power and high-throughput characteristics. In this paper, we present an energy-efficient HOG-based implementation for pedestrian detection system on a low-cost FPGA system-on-chip platform. The hardware accelerator implements the HOG computation and the Support Vector Machine classifier, the rest of the algorithm is mapped to software in the embedded processor. The hardware runs at 50 Mhz (lower frequency than previous works), thus achieving the best pixels processed per clock and the lower power design.
Keywords: FPGA; HOG extractor; pedestrian detection; accelerator; low power FPGA; HOG extractor; pedestrian detection; accelerator; low power

Share and Cite

MDPI and ACS Style

Ngo, V.; Castells-Rufas, D.; Casadevall, A.; Codina, M.; Carrabina, J. Low-Power Pedestrian Detection System on FPGA. Proceedings 2019, 31, 35.

AMA Style

Ngo V, Castells-Rufas D, Casadevall A, Codina M, Carrabina J. Low-Power Pedestrian Detection System on FPGA. Proceedings. 2019; 31(1):35.

Chicago/Turabian Style

Ngo, Vinh, David Castells-Rufas, Arnau Casadevall, Marc Codina, and Jordi Carrabina. 2019. "Low-Power Pedestrian Detection System on FPGA" Proceedings 31, no. 1: 35.

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