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Journal: Designs, 2020
Volume: 4
Number: 31

Article: Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages
Authors: by Ashish Alape Vivekananda and Eduard Enoiu
Link: https://www.mdpi.com/2411-9660/4/3/31

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