The Security Evaluation of an Efficient Lightweight AES Accelerator^†

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

1 Most of the space (Section 1-4) is devoted to introducing existing work and methods. The implementation scheme of the efficient lightweight AES accelerator is not given. 

2 It is mentioned in the conclusion that the propsed version of DOM  occupies a smaller area compared to the conventional DOM, but no results are provided to compare the hardware area. 

Author Response

Thank you for taking the time to review my paper. Your insightful comments and constructive feedback are greatly appreciated and have been addressed, and they will be added to the revised version. Below, you will find my responses to each of your comments, illustrating how they have been addressed. Thank you once again for your invaluable contribution to refining the quality and depth of my work.

 

Thank you for addressing this matter. I included an entire subsection that provides an explanation of the specifics of the optimization strategies that were utilized in the lightweight implementation and the lightweight DOM architecture.

In addition to that, I addressed the issue of comparing the areas. Regarding the information, it can be found in Table 1. For further analysis, I would like to refer the reviewer to the original published work that I have attached.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This work evaluated the security of optimized design of the AES algorithm against side channel analysis, notable for its low power consumption and compact area while delivering high performance.

The research materials are valuable and described scientifically while there is some suggestions for the authors.

 

1. There is no detail information for the process of the ASCI, only TSMC 40nm but no layout related.

2. There is also no detail information for the FPGA environments, only Artix 7 but not BRAM/rom related. No luts consumption or logic unit used.

Author Response

Thank you for taking the time to review my paper. Your insightful comments and constructive feedback are greatly appreciated and have been addressed, and they will be added to the revised version. Below, you will find my responses to each of your comments, illustrating how they have been addressed. Thank you once again for your invaluable contribution to refining the quality and depth of my work.

In the revised version, I have included two tables (Tables 2 and 3) that detail the implementations of both ASIC and FPGA for unprotected lightweight and DOM-based protection. These tables provide information on the area utilized and the maximum frequency. I hope that these tables contain all of the requested details.  You can also check out the original published work attached here.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

This paper proposes a security evaluation of two of the author’s previously proposed lightweight AES implementations using both profiled and non-profiled attacks.

 I begin by congratulating the author on this generally well-written, well-structured, and easy-to-understand article.

After the state-of-the-art study, the major work consists of describing the proposed methodology. Then, present the security analysis and discuss the results.

The work is exhaustive and self-contained.  However, the implementation results and a comparison with previous works are not given. The following are the two major suggestions:

1.      The authors evaluated the security of their previously optimized design of the algorithm against side-channel analysis. This part of the work is well explained and the experimental results are given, but there is no comparison with other works to discuss the pertinence of this work. Therefore, I suggest adding a paragraph dedicated to this important part to valorize the work.

2.      The authors used FPGA devices to analyze the security of the proposed design, but they did not give any information about the hardware implementation in terms of logic resources (Slices, DSP, Memory…) and timing performances (maximum frequency, throughput, …) and they did not give a comparison with the exiting lightweight AES implementations. I think it is important to add this study to the paper when using FPGA implementation.  

Best regards

Comments on the Quality of English Language

no comments

Author Response

Thank you for taking the time to review my paper. Your insightful comments and constructive feedback are greatly appreciated and have been addressed, and they will be added to the revised version. Below, you will find my responses to each of your comments, illustrating how they have been addressed. Thank you once again for your invaluable contribution to refining the quality and depth of my work.

 

1. It is not entirely clear what kind of comparison the reviewer is looking for; if you mean the comparison between the original DOM and the lightweight ones, then these comparisons have already been presented in the original work. Nevertheless, I also included the table in this revised version of the paper to demonstrate that the lightweight has a smaller area than the original DOM. In terms of the level of security they offer, there is no difference between the two DOMs.

 

2. I am grateful that you brought that to my attention.  I included two tables (Tables 2 and 3) that provide details on the implementations of both ASIC and FPGA for both unprotected lightweight and DOM-based protection.

Please find the original published work attached.

Author Response File: Author Response.pdf

Round 2

Reviewer 3 Report

Comments and Suggestions for Authors

I begin by thanking the author for his efforts in making the suggested corrections and explanatory responses to the remarks made. 

I have no other comments or suggestions about the paper as it is. 

In the end, I congratulate the author for this well-written, well-structured and easy-to-understand article.