Next Article in Journal
Object Recognition in Aerial Images Using Convolutional Neural Networks
Previous Article in Journal
A Multi-Projector Calibration Method for Virtual Reality Simulators with Analytically Defined Screens
Open AccessArticle

Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

1
CSIR—Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani 333031, Rajasthan, India; Academy of Scientific & Innovative Research (AcSIR), India
2
Electronic Science Department, Kurukshetra University, Kurukshetra 136119, Haryana, India
*
Author to whom correspondence should be addressed.
Academic Editor: Gonzalo Pajares Martinsanz
J. Imaging 2017, 3(2), 20; https://doi.org/10.3390/jimaging3020020
Received: 25 February 2017 / Revised: 3 June 2017 / Accepted: 5 June 2017 / Published: 7 June 2017
Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds) in real-time for standard PAL (720 × 576) size color video. View Full-Text
Keywords: real-time motion detection; VLSI architecture; FPGA implementation; video surveillance system; smart camera system real-time motion detection; VLSI architecture; FPGA implementation; video surveillance system; smart camera system
Show Figures

Figure 1

MDPI and ACS Style

Singh, S.; Mandal, A.S.; Shekhar, C.; Vohra, A. Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform. J. Imaging 2017, 3, 20.

Show more citation formats Show less citations formats
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map

1
Back to TopTop