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Article

A Switch-Reduced Multicell-to-Multicell Battery Equalizer Based on Full-Bridge Bipolar-Resonant LC Converter

1
New Energy Research Center, School of Electric Power, South China University of Technology, Guangzhou 510640, China
2
Guangdong Hynn Technology Co., Ltd., Dongguan 518109, China
*
Author to whom correspondence should be addressed.
Batteries 2022, 8(6), 53; https://doi.org/10.3390/batteries8060053
Submission received: 17 April 2022 / Revised: 31 May 2022 / Accepted: 1 June 2022 / Published: 3 June 2022

Abstract

:
Many battery equalizers have been proposed to achieve voltage consistency between series connected battery cells. Among them, the multicell-to-multicell (MC2MC) equalizers, which can directly transfer energy from consecutive more-charged cells to less-charged cells, can enable fast balancing and a high efficiency. However, due to the limitations of the equalizers, it is not possible to achieve fast equalization and reduce the size of the circuit at the same time. Therefore, a MC2MC equalizer based on a full-bridge bipolar-resonant LC Converter (FBBRLCC) is proposed in this paper, which not only implements MC2MC equalization, but also greatly reduces the circuit size by reducing the number of switches by nearly half. A mathematical model and simulation comparison with conventional equalizers are used to illustrate the high-speed equalization performance of the proposed equalizer and excellent balancing efficiency. An experimental prototype for eight cells is built to verify the performance of the proposed FBBRLCC equalizer and the balancing efficiencies in different operating modes are from 85.19% to 88.77% with the average power from 1.888 W to 14.227 W.

1. Introduction

With the global climate warming and the exhaustion of fossil fuels, the electrification of the powertrain in vehicles has gradually become a core concern of countries, automobile manufacturers and consumers [1,2,3]. As a core component of electric vehicles, the energy storage systems (ESSs) largely determine the performance, safety, and manufacturing cost of electric vehicles (EVs) [4,5,6]. At present, there are mainly two types of renewable energy storage components in electric vehicles: lithium batteries and ultracapacitors (UCs). Lithium batteries have the advantages of high energy density, low self-discharge rate, and no memory effect, and are widely used in electric vehicles (EVs), hybrid electric vehicles (HEVs), and other energy storage systems (ESSs) [7,8,9]. However, the application of lithium batteries in electric vehicles and new energy power generation is facing challenges because the voltage and capacity of a single lithium battery cannot meet the requirements of high voltage and capacity of these applications, so it must be connected in series and in parallel to improve the voltage and capacity, and finally form a battery pack [10,11,12].
However, due to the limitation of the battery manufacturing process and different environments, the battery voltage in the battery string will be imbalanced [13,14,15]. This inconsistency will become more and more serious with increasing cycle charge and discharge times, which will significantly reduce the available capacity and life of the battery pack, and even cause serious safety problems [16]. As a key technology of battery management systems (BMS), voltage equalization techniques can effectively improve the voltage inconsistency between cells [17]. Hence, it is very important to study voltage equalization techniques.
Various voltage equalization techniques have been proposed and developed. These techniques can be divided into dissipative types and non-dissipative types [18,19]. Dissipative voltage equalizers have a simple structure and are easy to implement [20]. However, they consume a lot of energy in the balancing process, which is their fatal disadvantage [21]. Compared with dissipative voltage equalizers, non-dissipative voltage equalizers transfer the energy from the strong cells to the weak cells by using energy storage elements, so the imbalanced energy will not be wasted, and the capacity of the pack can be improved [21,22,23]. According to equalization paths, non-dissipative voltage equalizers can be divided into adjacent cell-to-cell (AC2C) equalizers [24,25,26], direct cell-to-cell (DC2C) equalizers [27,28,29], cell-to-pack (C2P) equalizers [30], pack-to-cell (P2C) equalizers [31], and multicell-to-multicell (MC2MC) equalizers [21,32].
The AC2C equalizers can achieve equalization between adjacent two cells, but energy can only be transferred between two adjacent cells, which will lead to a slow balancing speed and low balancing efficiency when the number of batteries increases, for example, in equalizers based on quasi-resonant switched-capacitor converters (QRSSC) [24] and automatic buck-boost converters based on coupled inductors (CI) [26].
Compared to the AC2C equalizers, the DC2C equalizers achieve direct equalization of the more-charged battery and the less-charged battery by using common energy storage units such as LC resonators [27], inductors [28], or capacitors [29], which reduces the path of energy transmission. However, only one pair of batteries can be balanced at a time and the other batteries have to wait, which results in a slow balancing speed when the number of unbalanced batteries is very large, such as in equalizers based on full-bridge LC converters (FBLCC) [27].
The C2P equalizers deliver the excess energy of a single more-charged cell to the whole pack and can realize fast equalization when a few cells are more charged than other cells [30]. However, when only a few batteries in the battery pack are less charged than the other cells, this will lead to slow equalization and low efficiency. Contrary to the C2P equalizers, the P2C equalizers deliver the excess energy of the whole pack to a single less-charged cell and can realize fast equalization when a few cells are less charged than other cells [31]. However, in an opposite case when only a few batteries in the battery pack are more charged than the other cells, the P2C equalizers will be like the C2P equalizers, having slow equalization and low efficiency.
Considering the advantages and limitations of the above equalizers, a multicell-to-multicell (MC2MC) equalizer was proposed in [32] that can transfer energy from consecutive more-charged cells to less-charged cells. However, the half-bridge LC converter (HBLCC) in [32] cannot realize step-up conversion, which will slow down the balancing speed. Based on HBLCC, a novel bipolar-resonant LC converter (BRLCC) was proposed in [21] that can realize resonant tank-to-resonant LC in a bipolar way and thus improve balancing speeding and power. However, due to its symmetric switch matrix structure, the number of switches increases dramatically as the number of batteries increases, which results in large circuit size with low reliability.
Consequently, to improve the balancing speed and reduce the circuit size, this paper proposes a full-bridge bipolar-resonant LC converter (FBBRLCC) equalizer, as shown in Figure 1. Compared to HBLCC and BRLCC, the proposed FBBRLCC equalizer can realize fast balancing by transferring energy from consecutive odd number of more-charged cells to consecutive odd number of less-charged cells and reduce the number of switches by nearly half, which greatly reduces circuit cost and size and improves reliability. In Section 2, the circuit structure, operation principle, mathematical model, and mathematical analysis of the proposed FBBRLCC equalizer are provided. Section 3 shows a simulation comparison between the proposed FBBRLCC equalizer and several typical equalizers. Section 4 introduces the experimental prototype for eight cells, verifies its fast-balancing performance and presents a comprehensive evaluation. Section 5 shows a comprehensive discussion, and Section 6 provides a conclusion.

2. Proposed Equalizer

2.1. Circuit Structure

As shown in Figure 1, the proposed FBBRLCC equalizer has a cell access switch matrix, a full-bridge LC resonant tank, and a diode protection network. The cell access switch matrix consists of N + 1 bidirectional switches (S1SN+1). The full-bridge LC resonant tank consists of a resonant tank and a full-bridge switch structure (QR1, QR2, QL1, QL2). The diode protection network consists of four free-wheeling diodes (D1D4).
The resonant tank collects energy from the consecutive odd number of more-charged cells (release group) through the cell access switch matrix and the full-bridge switches (QR1, QR2, QL1, QL2), and then releases the energy to the consecutive odd number of less-charged cells (collect group).
Figure 2 presents four potential operation modes including one-cell-to-one-cell mode (1-1 mode), one-cell-to-three-cell mode (1-3 mode), three-cell-to-one-cell mode (3-1 mode), and three-cell-to-three-cell mode (3-3 mode). Due to the circuit’s resonant nature, the driving signals’ switching frequency and duty cycle are fixed. As a result, it is possible to make a simple control. Meanwhile, all switches are controlled to work with zero-current switching (ZCS), which can reduce the switching loss and the electromagnetic interference (EMI) and help reduce circuit size by increasing switching frequency.

2.2. Operation Principle

Figure 3 presents the operating states along with the current flow of the proposed equalizer. To facilitate the analysis, the balancing loop and the protection loop are analyzed separately, and it is assumed that the battery pack has eight cells with VB8 = VB7 = VB6 > VB5 > VB4 > VB3 > VB2 > VB1, which is arranged to illustrate the 3-1 mode equalization. The voltage of release group and collect group are VBR = VB8 + VB7 + VB6 and VBC = VB1, respectively.
In Figure 4a, an equivalent input of the full-bridge LC resonant converter is given. Figure 4b shows the theoretical waveforms of the proposed equalizer at VBR ≈ 3VBC. In Figure 4a, the Req represents the total parasitic resistance and can be expressed as Req = RLC + 8RON, where RLC is the total resistance of the LC resonant tank and RON is the ON-resistance of a MOSFET.
The proposed equalizer has a similar equivalent input to the bipolar-resonant LC converter (BRLCC) equalizer presented in [21]. However, compared with the symmetrical switch matrix in [21], the proposed equalizer achieves a change in the polarity of the input terminal through a full-bridge switch structure, which can reduce the number of switches by nearly half. As a result, the proposed equalizer not only achieves MC2MC equalization, but also greatly reduces the size of the circuit and improves the reliability of the circuit.
Figure 4b shows the waveforms including driving signals, inductor current iLC, and capacitor voltage uC of the equalizer, which shows the inductor current iLC achieves ZCS by resonance, and the capacitor voltage uC is charged/discharged to different voltage values at the end of each switching state. More details are described in Section 2.3.

2.3. Mathematical Model

Based on the equivalent input of the full-bridge LC resonant converter and according to Kirchhoff’s voltage law, uC and iLC meet:
L d i LC t d t + i L t R eq + u C t = V in i LC t = C d u C t d t
where L is the inductance, C is the capacitance, Req is the total parasitic resistance.
In positive collect state I [t0t1]: during this state, switches S6 and S9 connect the release group (VBR = VB8 + VB7 + VB6) to the full-bridge LC resonant tank. The LC resonant tank is charged positively using QL2 and QR1. Since UC(0) is a remnant uC from the previous period and is lower than VBR, uC increases from UC(0) to UC(1), and the peak value of iLC is ILC(1). According to (1), uC and iLC can be given by:
u C t = V BR + U C ( 0 ) V BR e ξ ω n t t 0   cos ω n 1 ξ 2 t t 0 + ξ 1 ξ 2 sin ω n 1 ξ 2 t t 0
i LC t = V BR U C 0 Z r 1 ζ 2 e ζ ω n t t 0 sin ω n 1 ζ 2 t t 0
where ω n = 1 / L C , Z r = L / C , and ξ = R eq / 2 Z r . The positive collect state ends when iLC reaches zero at t = t1, and the duration of this state is:
Δ t = t 1 t 0 = π ω n × 1 ξ 2
At the end of this state, uC is positively charged to UC(1):
U C ( 1 ) = V BR + ( V BR U C ( 0 ) ) e ξ π 1 ξ 2
In positive release state Ⅱ [t1t2]: during this state, switches S1 and S2 connect the collect group (VBC = VB1) to the full-bridge LC resonant tank. The LC resonant tank positively releases charges to VBC using QL1 and QR2. Since UC(1) is higher than VBC, uC discharges from UC(1) to UC(2), and the peak value of iLC is ILC(2). In this state, uC and iLC can be given by:
u C t = V BC + U C ( 1 ) V BC e ξ ω n t t 1 cos ω n 1 ξ 2 t t 1 + ξ 1 ξ 2 sin ω n 1 ξ 2 t t 1
i LC t = V BC U C 1 Z r 1 ξ 2 e ξ ω n t t 1 sin ω n 1 ξ 2 t t 1
At the end of this state, iLC reaches zero at t = t2 = t1 + Δt, uC is positively charged to UC(2):
U C ( 2 ) = V BC + ( V BC U C ( 1 ) ) e ξ π 1 ξ 2
In negative collect state Ⅲ [t2t3]: during this state, switches S6 and S9 connect the release group (VBR = VB8 + VB7 + VB6) to the full-bridge LC resonant tank. The LC resonant tank is charged negatively using QL1 and QR2. Since UC(2) is negatively lower than −VBR, uC is negatively charged from UC(2) to UC(3), and the peak value of iLC is ILC(3). In this state, uC and iLC can be given by:
u C t = V BC + U C ( 1 ) V BC e ξ ω n t t 2 cos ω n 1 ξ 2 t t 2 + ξ 1 ξ 2 sin ω n 1 ξ 2 t t 2
i LC t = V BR U C 2 Z r 1 ξ 2 e ξ ω n t t 2 sin ω n 1 ξ 2 t t 2
At the end of this state, iLC reaches zero at t = t3 = t1 + 2Δt, uC is negatively charged to UC(3):
U C ( 3 ) = V BR + ( U C ( 2 ) V BR ) e ξ π 1 ξ 2
By substituting t into Equations (9) and (10), it can be found that the waveforms in Equations (9) and (10) are identical to those in Equations (2) and (3) except for the polarity.
In negative release state Ⅳ [t3t4]: during this state, switches S1 and S2 connect the collect group (VBC = VB1) to the full-bridge LC resonant tank. The LC resonant tank negatively releases charges to VBC using QL2 and QR1. Since UC(3) is negatively higher than −VBC, uC negatively discharges from UC(3) to UC(4), and the peak value of iLC is ILC(4). In this state, uC and iLC can be given by:
u C t = V BC + U C ( 3 ) + V BC e ξ ω n t t 3 cos ω n 1 ξ 2 t t 3 + ξ 1 ξ 2 sin ω n 1 ξ 2 t t 3
i LC t = V BR U C 3 Z r 1 ξ 2 e ξ ω n t t 3 sin ω n 1 ξ 2 t t 3
At the end of this state, iLC reaches zero at t = t4 = t2 + 2Δt, uC negatively discharges to UC(4):
U C ( 4 ) = V BC + ( U C ( 3 ) V BC ) e ξ π 1 ξ 2
By substituting t into Equations (12) and (13), it can be found that the waveforms in Equations (12) and (13) are identical to those in Equations (6) and (7) except for the polarity.
Based on Equations (5), (8), (11) and (14), the capacitor voltage uC and peak inductor current iL in each state can be calculated by combining UC(0) = UC(4):
U C 0 U C 1 = U C 2 U C 3 = k V BR V BC V BR + k V BC × 1 + k 1 + k 2
I LC 1 I LC 2 = I LC 3 I LC 4 = V BR U C 0 V BC U C 1 × k Z r 1 ξ 2
where
k = e ξ π 1 ξ 2
According to the analysis above, the release group will charge the capacitor in positive collect state I and in negative collect state Ⅲ. As a result, uC rises from UC(0) to UC(1) positively and rises negatively from UC(2) to UC(3). According to (15), it also should be noticed that UC(0)–UC(1) and UC(2)–UC(3) are equal. As the total duration of one switching period is 4Δt, the average power released by the release group can be expressed as:
P R = V BR 1 ξ 2 2 π Z r 1 k 2 V BR + 1 + k 2 V BC 1 + k 2
Similarly, the capacitor will charge the collect group in positive release state II and in negative release state IV. As a result, uC falls from UC(1) to UC(2) positively and falls negatively from UC(3) to UC(4). Therefore, the average power received by the collect group can be expressed as:
P C = V BR 1 ξ 2 2 π Z r 1 k 2 V BR + 1 + k 2 V BC 1 + k 2
Based on (18) and (19), the balancing efficiency ηFBBRLCC can be calculated as:
η FBBRLCC = P C P R = V BC V BR × 1 + k V BR 1 k V BC 1 k V BR + 1 + k V BC
Based on Equations (18) and (20), Figure 5a presents the average power PR versus Zr and Req and Figure 5b presents the balancing efficiency ηFBBRLCC versus Zr and Req when VBR = 12 V and VBC = 3.9 V. From Figure 5, we can observe that, as the total parasitic resistance Req decreases, both the balancing efficiency ηFBBRLCC and the average power PR increase. As a result, the total parasitic resistance Req should be minimized to achieve a maximum average power PR and a maximum balancing efficiency ηFBBRLCC. It can also be observed that, when the total parasitic resistance Req is determined, a larger Zr will result in a higher ηFBBRLCC, while a smaller Zr will result in a higher PR, which can be used to adjust the average power and the balancing efficiency by changing Zr.

3. Simulation Comparison with Conventional Equalizers

In this section, we use the PSIM9.1.3 simulation software to simulate the proposed equalizer and several classic equalizers. The objects of the simulation are the proposed full-bridge bipolar-resonant LC converter (FBBRLCC) equalizer, quasi-resonant switched-capacitor converter (QRSSC) equalizer [24], the half-bridge LC converter (HBLCC) equalizer [32], and the bipolar-resonant LC converter (BRLCC) equalizer [21]. To reduce the simulation time, we used eight 0.01 F capacitors instead of the batteries for the simulation [21]. All simulation models have the same parameters of L = 10 µH, C = 1 µF.
At the same time, due to the different structures of different equalizers, the values of the total parasitic resistance Req in different equalizers are different. Suppose the total resistance RLC of the LC resonant is 0.16 Ω and the ON-resistance of a MOSFET is 0.01 Ω. As a result, the total parasitic resistance Req of the equalizers above are 0.24 Ω, 0.18 Ω, 0.2 Ω, and 0.2 Ω, respectively.
Figure 6 shows the flowchart for the control strategy of the proposed FBBRLCC equalizer. The balancing process will start when the maximum voltage difference VBmaxVBmin is more than 10 mV.
To compare the four equalizers above, two voltage distributions are set, namely initial voltage #1 and initial voltage #2. The initial voltage #1 of VB1 = 3.75 V, VB2 = 4.20 V, VB3 = 4.10 V, VB4 = 4.00 V, VB5 = 3.85 V, VB6 = 3.74 V, VB7 = 3.72 V, and VB8 = 3.70 V is used to simulate the emergency discharge of B2, B3 and B4, which are close to full-charged. The initial voltage #2 of VB1 = 3.50 V, VB2 = 3.48 V, VB3 = 3.46 V, VB4 = 3.44 V, VB5 = 3.42 V, VB6 = 3.10 V, VB7 = 3.05 V, and VB8 = 3.00 V is used to simulate the emergency charge of B6, B7 and B8, which are close to full-discharged. The simulation results are shown in Figure 7 and are summarized in Table 1.
Based on the results in Table 1, it can be seen that, for both the initial voltages #1 and the initial voltages #2, the proposed FBBRLCC equalizer takes the shortest time to achieve equalization. Meanwhile, at the initial voltages #1, the balancing speed of the FBBRLCC equalizer is 23 times that of the QRSCC equalizer, 6.8 times that of the HBLCC equalizer, 1.1 times that of the BRLCC equalizer, and at the initial voltages #2, the balancing speed of the FBBRLCC equalizer is 25 times that of the QRSCC equalizer, 7.8 times that of the HBLCC equalizer, 1.01 times that of the BRLCC equalizer. The energy transfer efficiencies of the proposed FBBRLCC equalizer are 86.23% and 88.68%, at the initial voltages #1 and the initial voltages #2, respectively. It is worth mentioning that, in the two voltage distributions, the balancing speed of the proposed equalizer is slightly faster than that of the BRLCC equalizer, and the efficiencies of the two equalizers are very close, and are slightly lower than the other two equalizers. It is reasonable that faster balancing speed means higher balancing current, which will incur more losses and lead to a slight decrease in efficiency. Compared with the decrease in balancing efficiency, the increase in balancing speed is significant. In addition, compared to the BRLCC equalizer, the proposed FBBRLCC equalizer reduces the number of switches by nearly half, which means fewer MOSFET drivers and higher reliability. As a result, it is worthwhile taking such a trade-off.
To figure out how the balancing time scales with cell capacity, Table 2 and Table 3 respectively show the influence of different cell capacities on balancing time under the initial voltages #1 and the initial voltages #2. According to the results in Table 2 and Table 3, under the two voltage distributions, the increase of cell capacity of simulation makes the time for all equalizers to achieve equalization longer, but the order of equalizers’ balancing speed does not change.

4. Experiment

In this section, an experimental prototype for eight cells is built to verify the performance of the proposed FBBRLCC equalizer, as shown in Figure 8. An STM32 (STM32F103VET6) is used as the controller for the FBBRLCC equalizer and gives the driving signals to the FBBRLCC equalizer through the gate driver board. The parameters of the prototype are present in Table 4.
Figure 9 shows the experimental waveforms of the proposed FBBRLCC equalizer in different operating modes. The inductor current iLC waveforms indicates that, at the end of each state, the inductor current iLC will drop to zero and ZCS is realized.
To verify the accuracy of the mathematical model analysis in Section 2.3, the measured data and the theoretical values are compared in Table 5. The voltages are measured using a BQ76PL455 16-cell battery monitor, and the currents ILC (1) and ILC (2) are measured by a CYBERTEK CP8030H current probe. In the 1-1 mode, when VBR and VBC are set to 3.903 V and 3.871 V, respectively, the average power PC is about 1.888 W and the balancing efficiency is 88.77%. In the 1-3 mode, when VBR and VBC are set to 3.995 V and 11.583 V, respectively, the average power PC is about 5.150 W and the balancing efficiency is 85.19%. In the 3-1 mode, when VBR and VBC are set to 11.487 V and 3.929 V, respectively, the average power PC is about 5.049 W and the balancing efficiency is 86.75%. In the 3-3 mode, when VBR and VBC are set to 11.287 V and 11.750 V, respectively, the average power PC is about 14.227 W and the balancing efficiency is 87.28%. The above experimental results prove that the average power of the proposed FBBRLCC equalizer in the four operating modes are from 1.888 W to 14.227 W with the balancing efficiencies from 85.19% to 88.77%.
Figure 10 shows the balancing experiments for eight cells with initial voltages #1 and #2. Since we let the equalizer equalize for 20 s and then rest for 10 s, the voltage curve is cyclical [21,32]. With the initial voltage #1, the balancing voltage waveform of the proposed FBBRLCC equalizer is shown in Figure 10a, and the proposed FBBRLCC equalizer takes about 149 min to realize equalization. With the initial voltage #2, the balancing voltage waveform of the proposed FBBRLCC equalizer is shown in Figure 10b, and the proposed FBBRLCC equalizer takes about 46 min to realize equalization. These two experiments with initial voltages #1 and #2 prove that the proposed FBBRLCC equalizer has the ability to equalize quickly.
It can be seen from the above experimental results, compared with the experimental results of the equalizer in [21], both of them have excellent balancing speed and efficiency, and the proposed equalizer has a great advantage in terms of size.

5. Discussion

For a comprehensive evaluation of the proposed FBBRLCC equalizer, Table 6 compares it with several traditional equalizers in terms of size, efficiency, balancing speed, and type in the case of n cells. Table 7 gives the costs of different experimental prototypes under the assumption that the battery pack has 96 series-connected cells and is divided into 12 battery modules [21]. Each module manages eight cells, and the pack manages twelve modules. Taking the proposed FBBRLCC equalizer as an example: each module needs 2 × (9 + 4) = 26 MOSFETs, and the pack needs 2 × (13 + 4) = 34 MOSFETs, so the total number of MOSFETs is 26 × 12 + 52 = 346. The component prices per unit are approximated as: MOSFET ($0.2), MOSFET Driver ($0.8), Inductor ($0.6), Capacitor ($0.2), Diode ($0.15) [21].
The AC2C equalizers based on quasi-resonant switched-capacitor converters (QRSSC) in [24] and based on coupled inductors (CI) in [26] can only transfer energy between adjacent batteries, which results in large size and slow balancing speed. Compared with the CI, the QRSSC realizes ZCS; as a result, it has higher balancing efficiency.
The DC2C equalizer based on a full-bridge LC converter (FBLCC) in [27] achieves direct equalization of the more-charged battery and the less-charged battery by using a common energy storage unit, so it has small size. However, only one pair of batteries can be balanced at a time, and the other batteries have to wait, which reduces the balancing speed. Meanwhile, the QRSSC realizes ZCS, so its balancing efficiency is high.
The MC2MC equalizer based on half-bridge LC converter (HBLCC) in [32] and bipolar-resonant LC converter (BRLCC) in [21] can transfer the energy from consecutive more-charged cells to consecutive less-charged cells. As a result, both have a high balancing speed, but the HBLCC cannot realize step-up conversion, which will slow down the balancing speed. At the same time, both realize ZCS, so they have a high balancing efficiency. Thus, the BRLCC has a better performance. However, due to its symmetric switch matrix structure, the number of switches will increase dramatically as the number of batteries increases, which makes circuit size large with low reliability. The proposed FBBRLCC equalizer not only achieves faster balancing speed by transferring energy from consecutive odd numbers of more-charged cells to consecutive odd numbers of less-charged cells, but also greatly reduces the size of the circuit by reducing the number of switches. Due to the structure of the proposed FBBRLCC equalizer, it could only achieve an equalization between consecutive odd number of cells and consecutive odd number of cells, as a result, it has fewer operation modes than the BRLCC equalizer. Compared with the increase in balancing speed and the reduction in circuit size, the decrease in balancing efficiency is insignificant and can still be maintained at a high level.

6. Conclusions

In this paper, a full-bridge bipolar-resonant LC converter (FBBRLCC) equalizer is proposed and an experimental prototype for eight cells is built to verify the performance of the proposed FBBRLCC equalizer. The circuit structure, operation principle, and mathematical model are presented. Simulation comparison with the traditional equalizer is done to prove that the proposed equalizer can achieve fast equalization while maintaining high equalization efficiency and small size. The final experimental results present that the proposed FBBRLCC equalizer can transfer energy from consecutive odd more-charged cells to consecutive odd less-charged cells, which increases the balancing speed but requires a small sacrifice in balancing efficiency. While the balancing efficiencies of the proposed FBBRLCC equalizer in the different operating modes still could keep from 85.19% to 88.77% with the average power from 1.888 W to 14.227 W. Meanwhile, compared with the two MC2MC equalizers HBLCC and BRLCC, the proposed FBBRCC not only implements MC2MC equalization, but also greatly reduces the circuit size by reducing the number of switches by nearly half, as well as the circuit reliability.

Author Contributions

Conceptualization, P.X.; data curation, P.X., X.L., H.L.; formal analysis, P.X.; funding acquisition, L.K.; project administration, D.X.; software, P.X.; supervision, L.K.; validation, P.X.; writing—original draft, P.X.; writing—review and editing, X.L. and H.L. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by Research and Industrialization of High-Precision Health Prediction Technology for Power Battery Pack, grant number D8221430.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Proposed FBBRLCC equalizer for N cells.
Figure 1. Proposed FBBRLCC equalizer for N cells.
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Figure 2. Possible operation modes of the proposed equalizer. (a) 1-1 mode. (b) 1-3 mode. (c) 3-1 mode. (d) 3-3 mode.
Figure 2. Possible operation modes of the proposed equalizer. (a) 1-1 mode. (b) 1-3 mode. (c) 3-1 mode. (d) 3-3 mode.
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Figure 3. Operating states and current flow of the proposed equalizer at VBR = VB8 + VB7 + VB6 and VBC = VB1. (a) State I: positive collect. (b) State II: positive release. (c) State III: negative collect. (d) State IV: negative release. (e) Positive afterproduction. (f) Negative afterproduction.
Figure 3. Operating states and current flow of the proposed equalizer at VBR = VB8 + VB7 + VB6 and VBC = VB1. (a) State I: positive collect. (b) State II: positive release. (c) State III: negative collect. (d) State IV: negative release. (e) Positive afterproduction. (f) Negative afterproduction.
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Figure 4. Theoretical waveforms of the proposed equalizer at VBR ≈ 3VBC. (a) Equivalent input of the FBBELCC. (b) Waveforms including driving signals, inductor current iLC, and capacitor voltage uC of the equalizer.
Figure 4. Theoretical waveforms of the proposed equalizer at VBR ≈ 3VBC. (a) Equivalent input of the FBBELCC. (b) Waveforms including driving signals, inductor current iLC, and capacitor voltage uC of the equalizer.
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Figure 5. The influence of Zr and Req on balancing efficiency and average power of the proposed FBBRLCC equalizer at VBR = 12 V and VBC =3.9 V. (a) PR versus Zr and Req. (b) ηFBBRLCC versus Zr and Req.
Figure 5. The influence of Zr and Req on balancing efficiency and average power of the proposed FBBRLCC equalizer at VBR = 12 V and VBC =3.9 V. (a) PR versus Zr and Req. (b) ηFBBRLCC versus Zr and Req.
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Figure 6. Control algorithm of the proposed FBBRLCC equalizer.
Figure 6. Control algorithm of the proposed FBBRLCC equalizer.
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Figure 7. Voltage trajectories of different equalizers with initial voltages #1 and #2. (a,b) QRSCC. (c,d) BRLCC. (e,f) HBLCC. (g,h) Proposed FBBRLCC.
Figure 7. Voltage trajectories of different equalizers with initial voltages #1 and #2. (a,b) QRSCC. (c,d) BRLCC. (e,f) HBLCC. (g,h) Proposed FBBRLCC.
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Figure 8. Experimental prototype for eight cells.
Figure 8. Experimental prototype for eight cells.
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Figure 9. Experimental waveforms of the proposed FBBRLCC in different operation modes. (a) 1-1 mode. (b) 1-3 mode. (c) 3-1 mode. (d) 3-3 mode.
Figure 9. Experimental waveforms of the proposed FBBRLCC in different operation modes. (a) 1-1 mode. (b) 1-3 mode. (c) 3-1 mode. (d) 3-3 mode.
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Figure 10. Experimental voltage trajectories of the proposed FBBRLCC equalizer with initial voltage #1 and #2. (a) Initial voltage #1; (b) initial voltage #2.
Figure 10. Experimental voltage trajectories of the proposed FBBRLCC equalizer with initial voltage #1 and #2. (a) Initial voltage #1; (b) initial voltage #2.
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Table 1. Simulation comparison of different equalizers with initial voltages #1 and #2.
Table 1. Simulation comparison of different equalizers with initial voltages #1 and #2.
EqualizerInitial Voltage #1Initial Voltage #2
TimeEfficiencyTimeEfficiency
QRSCC [24]0.20640 s94.21%0.23240 s93.55%
HBLCC [32]0.06448 s95.76%0.06877 s93.46%
BRLCC [21]0.00835 s86.86%0.01064 s89.15%
Proposed FBBRLCC0.00826 s86.23%0.01006 s88.68%
Table 2. Simulation comparison of the influence of different cell capacities on balancing time under the initial voltages #1.
Table 2. Simulation comparison of the influence of different cell capacities on balancing time under the initial voltages #1.
EqualizerCell Capacity of Simulation
0.001 F0.005 F0.01 F0.02 F0.05 F
QRSCC [24]0.02282 s0.11544 s0.20640 s0.46157 s1.15661 s
HBLCC [32]0.00634 s0.03321 s0.06448 s0.13291 s0.33239 s
BRLCC [21]0.00089 s0.00430 s0.00835 s0.01690 s0.04258 s
Proposed FBBRLCC0.00088 s0.00419 s0.00826 s0.01568 s0.03934 s
Table 3. Simulation comparison of the influence of different cell capacities on balancing time under the initial voltages #2.
Table 3. Simulation comparison of the influence of different cell capacities on balancing time under the initial voltages #2.
EqualizerCell Capacity of Simulation
0.001 F0.005 F0.01 F0.02 F0.05 F
QRSCC [24]0.02323 s0.11571 s0.23240 s0.46367 s1.15756 s
HBLCC [32]0.00681 s0.03360 s0.06877 s0.15016 s0.37573 s
BRLCC [21]0.00108 s0.00531 s0.01064 s0.02051 s0.05334 s
Proposed FBBRLCC0.00102 s0.00504 s0.01006 s0.01994 s0.05315 s
Table 4. The parameters of the prototype.
Table 4. The parameters of the prototype.
ComponentsParameters
Inductor LFerrite inductance10 µH
Capacitor CCBB1 µF
SwitchesnMOSFETIRF3205PBF
Gate DriversMOSFET driver1EDI20N12AFXUMA1
Free-wheeling DiodesSchottky diodeMBRS360BT3G
Battery PackLithium-ion batteryICR18650-22F (2200 mAh)
Table 5. Experimentally measured data of the proposed FBBRLCC equalizer in different operating modes.
Table 5. Experimentally measured data of the proposed FBBRLCC equalizer in different operating modes.
ModeVBR/VVBC/VILC (1) /AILC (2) /APR/WPC/WηFBBRLCC/%
Exp.ModelExp.ModelError
1-13.9033.8711.521.361.8881.6761.43788.7790.54−1.80
1-33.99511.5834.051.195.1504.3884.64285.1983.14−2.05
3-111.4873.9291.383.505.0464.3774.44786.7585.221.52
3-311.28711.7503.963.3214.22712.41712.58487.2890.06−3.32
Table 6. Comparison of equalizers for n cells in terms of size, efficiency, balancing speed, and type.
Table 6. Comparison of equalizers for n cells in terms of size, efficiency, balancing speed, and type.
EqualizerComponent NumberSizeEfficiencySpeedType
MOSFETMOSFET Driver InductorCapacitorDiode
QRSCC [24]2n2nn − 1n − 10LargeHighSlowAC2C
CI [26]4(n − 1)4(n − 1)2(n − 1)00LargeMediumSlowAC2C
FBLCC [27]2n + 10n + 5114SmallHighMediumDC2C
HBLCC [32]4n2n114MediumHighMediumMC2MC
BRLCC [21]4(n + 1)2(n + 1)114MediumHighFastMC2MC
Proposed FBBRLCC2n + 10n + 5114SmallHighFastMC2MC
Table 7. Costs of different experimental prototypes.
Table 7. Costs of different experimental prototypes.
EqualizerComponent NumberCosts ($)Type
MOSFETMOSFET Driver InductorCapacitorDiode
QRSCC [24]21621695950292.0AC2C
CI [26]38038019000494.0AC2C
FBLCC [27]34617313134225.8DC2C
HBLCC [32]432216131352277.4MC2MC
BRLCC [21]484242131352308.6MC2MC
Proposed FBBRLCC346173131352225.8MC2MC
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Xu, P.; Kang, L.; Xie, D.; Luo, X.; Lin, H. A Switch-Reduced Multicell-to-Multicell Battery Equalizer Based on Full-Bridge Bipolar-Resonant LC Converter. Batteries 2022, 8, 53. https://doi.org/10.3390/batteries8060053

AMA Style

Xu P, Kang L, Xie D, Luo X, Lin H. A Switch-Reduced Multicell-to-Multicell Battery Equalizer Based on Full-Bridge Bipolar-Resonant LC Converter. Batteries. 2022; 8(6):53. https://doi.org/10.3390/batteries8060053

Chicago/Turabian Style

Xu, Peng, Longyun Kang, Di Xie, Xuan Luo, and Hongye Lin. 2022. "A Switch-Reduced Multicell-to-Multicell Battery Equalizer Based on Full-Bridge Bipolar-Resonant LC Converter" Batteries 8, no. 6: 53. https://doi.org/10.3390/batteries8060053

APA Style

Xu, P., Kang, L., Xie, D., Luo, X., & Lin, H. (2022). A Switch-Reduced Multicell-to-Multicell Battery Equalizer Based on Full-Bridge Bipolar-Resonant LC Converter. Batteries, 8(6), 53. https://doi.org/10.3390/batteries8060053

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