DES-Based Synchronization Algorithm Optimization for EtherCAT Master–Slave System

Abstract

EtherCAT, known for its exceptional real-time performance and synchronization capabilities, is widely used in industrial multi-axis control systems. In these systems, the synchronization status of slave axes plays a critical role in determining the precision of the end-effector. While the distributed clock synchronization technology in EtherCAT achieves effective overall synchronization for the master–slave system, notable synchronization errors persist between non-reference slaves and the reference slave. To address this issue, this paper proposes an improved EtherCAT master–slave synchronization method based on the Double Exponential Smoothing (DES) algorithm. The proposed method begins by measuring the transmission delay between the master and the reference slave. Using this delay, the exponential moving average technique is applied to periodically adjust and compensate for synchronization errors between the master and the reference slave. Subsequently, the DES algorithm is employed to periodically calculate the clock drift of non-reference slave clocks relative to the reference clock, enabling corresponding compensation for the slave clocks. To validate the feasibility of the proposed method, an EtherCAT master–slave experimental platform was established using the Xenomai real-time operating system, and synchronization performance was evaluated. Experimental results show that the proposed method controls synchronization errors within ±90 ns in a six-slave experimental setup. Compared with synchronization error ranges achieved using only exponential moving average (EMA) for clock drift compensation, the proposed method reduces the synchronization error by approximately 16.36%, thereby validating its effectiveness.

1. Introduction

With the increasing demand for synchronization performance in industrial control, the limitations of traditional fieldbus systems are becoming more evident [1]. Consequently, research efforts have shifted towards industrial Ethernet [2], which provides notable advantages, including openness and a simplified architecture [3]. Among real-time industrial Ethernet technologies, EtherCAT stands out as a prominent representative, gaining significant recognition and attention for its flexible topology [4], exceptional real-time performance [5,6], and high-precision synchronization capabilities [7]. Its distinctive distributed clock synchronization technology allows the entire master–slave system to achieve synchronization accuracy at the nanosecond level [8,9]. In industrial multi-axis control systems, synchronized control of each motor plays a critical role in determining control precision [10,11]. Therefore, investigating the synchronization mechanisms between EtherCAT master and slave system holds considerable practical importance.

To further enhance the synchronization accuracy of EtherCAT, numerous researchers have proposed improvements to its Distributed Clock (DC) mechanism and optimized conventional synchronization methods. For instance, Rong Feng et al. addressed the transmission delay between the master and the reference slave during the clock synchronization process. By compensating for this delay, they optimized the traditional synchronization approach and significantly improved clock synchronization accuracy [12]. However, when addressing clock drift, their method remained reliant on adjusting the clock rate. Sung-Mun Park et al. introduced the Exponential Moving Average (EMA) technique to filter clock drift and compensate for synchronization errors while minimizing memory usage [13]. Their improvements to the DC distributed clock mechanism enhanced synchronization performance. Nonetheless, relying solely on the EMA method to compensate for clock drift still results in significant synchronization errors in systems with multiple slaves. Sun Jihao from Huazhong University of Science and Technology proposed a fractional-order proportional-integral (FOPI) control-based drift compensation method to reduce synchronization errors among slaves [14]. However, this approach did not consider the transmission delay between the master and the reference slave, potentially resulting in an underestimation of the calculated delay. In contrast, Hyoung-Woo Kim et al. addressed this issue by measuring the transmission delay between the master and the reference slave. They compensated for the delay by averaging 1000 measurements, thereby improving the accuracy of delay estimation. They also employed the EMA method to compensate for clock drift; however, the synchronization error remained relatively large [15]. Ganz Davide et al. integrated the Precision Time Protocol (PTP) into EtherCAT frames, leveraging this protocol to reduce synchronization errors among slaves [16]. Bong Jun Choi et al. proposed a distributed asynchronous clock synchronization protocol that enables global clock synchronization among mobile nodes in the network, even under asynchronous conditions, long latency, or intermittent connections [17]. Reinhard Exel et al. proposed a solution based on line switching and high-precision timestamps to address the issue of asymmetric transmission delays. However, the algorithm is relatively complex and requires hardware support [18]. The existing research methods have two major shortcomings. First, studies [12,13,14,15,16,17] inadequately address the significant increasing trend of clock drift observed in slaves when clock drift compensation is not applied [14]. Second, these studies [13,14,16,17] fail to consider the transmission delay between the master and the reference slave, leaving a critical factor unexamined.

To address the aforementioned issues, this paper introduces an improved DES clock compensation method that incorporates clock drift trend terms and transmission delay compensation strategies, significantly enhancing synchronization accuracy among EtherCAT slaves. The main contributions of this paper are summarized as follows:

(1)

An improved DES clock compensation method is proposed, integrating a clock drift trend term to effectively reduce synchronization errors. In addition, the master–slave transmission delay compensation strategy mitigates the adverse effects of transmission delays on synchronization performance. The synergy of these techniques substantially enhances synchronization among EtherCAT slaves.

(2)

An EtherCAT master–slave system was constructed to experimentally validate the effectiveness and superiority of the proposed method. Compared with using only the exponential moving average (EMA) for clock drift compensation, the proposed method reduced the synchronization error range by approximately 16.36%.

2. EtherCAT DC Distributed Clock Synchronization Mechanism

The IEEE 1588 Precision Time Protocol (PTP) achieves sub-microsecond clock synchronization in a distributed network by utilizing a master–slave hierarchy and hardware-based timestamping to precisely measure and compensate for packet delay. In accordance with the IEEE1588 standard, EtherCAT uses a distributed clock synchronization mechanism that allows all masters and slaves to have the same system time in order to control the execution of the synchronization tasks of the individual slaves. EtherCAT utilizes a Distributed Clocks (DC) synchronization mechanism, which allows slaves within the network to share a unified system time, thereby ensuring precise synchronization among the individual slave clocks [19]. Nevertheless, variations in clock sources can occur due to differences in the crystal oscillators used in each slave, discrepancies in power-up times, and environmental factors such as temperature [20,21].

To synchronize clock times among the slaves, the EtherCAT master designates the first connected slave with a DC clock as the reference slave [22], whereas all other connected slaves are categorized as non-reference slaves [23]. Non-reference slaves use the reference slave’s time as the reference_time to achieve synchronization [24]. The time of the remaining slaves with DC clocks is referred to as the local_time. The offset between the local clock time and the reference clock is called the clock offset. After clock offset compensation, the local clock time is referred to as the system_time of the slave [25]. Assume that reference_time is greater than local_time, then

$$systemtime=localtime+offset$$

(1)

As shown in Figure 1, the clock error among slave clocks arises primarily from three factors: transmission delay, initial clock offset, and clock drift [26]. During the initialization of the DC distributed clock, the master sends a data frame. Upon receiving the frame, each slave records the time at which it was received at each of its ports [27]. Assume that when the data frame arrives at the reference clock slave, the reference time is $T_1$, and when it arrives at slave i, the local clock time of slave i is $T_2$. The transmission delay from the reference clock slave to slave i is $T{D}_i$ [28]. The following relationship can be established:

$$offset=T_2-T_1-T{D}_i$$

(2)

When the data frame returns after passing through all the slaves, the local clock time at slave i upon arrival is $T_3$, and the time when it reaches the reference clock slave is $T_4$. The transmission delay from slave i to the reference clock slave can be obtained by the following equation:

$$T{D}_i={\displaystyle \frac{(T_4-T_1)-(T_3-T_2)}{2}}$$

(3)

During system operation, factors such as the use of different crystal oscillators in the reference clock and other slave clocks cause drift in their timing cycles, leading to asynchronous clock operation. This phenomenon, known as clock drift, results in the misalignment of the slave clocks [29].

When the EtherCAT master calculates clock drift, it sends ARMW or FRMW command data frames to each slave [30]. The slaves return their system time and transmission delay to the master [31]. The master can obtain the clock drift either by reading the slave registers or by using the clock drift formula. The formula for calculating the clock drift $\Delta t$ is as follows:

$$\Delta t=systemtime-(referencetime+TD)$$

(4)

The existing clock rate adjustment method (ACR) regulates the speed of the slave’s local clock by adjusting the ESC (EtherCAT Slave Controller) based on the sign of $\Delta t$, determining whether it is positive or negative [32,33]. When $\Delta t$ = 0, the local time increases by 10 units every 10 ns. When $\Delta t$ is positive, it indicates that the local clock speed is greater than the reference clock speed and needs to be decreased, causing the local time to increase by 9 units every 10 ns. When $\Delta t$ is negative, it indicates that the local clock speed is slower than the reference clock speed and needs to be increased, so the local time increases by 11 units every 10 ns [34].

This method has two main shortcomings. First, it does not consider the transmission delay between the master and the reference slave. Instead, this delay is attributed to the clock offset among the master and the non-reference slaves, leading to an overestimation of the clock offset for these slaves [12]. Consequently, the calculated clock drift is also overestimated. Second, clock drift compensation is only performed based on the sign (positive or negative) of the clock drift [15]. Even with real-time compensation data frames sent to the slaves, significant clock drift still persists. It is essential to compensate for the transmission delay between the master and the reference slave, as well as to consider both the magnitude and sign of the clock drift to maximize the effectiveness of the compensation, thereby reducing the clock drift for each slave.

3. Improved EtherCAT Synchronization Method

3.1. Clock Drift Compensation

To achieve more precise compensation for clock drift errors, the exponential smoothing forecasting method can be applied to estimate the clock drift among slaves. Based on this estimation, the clock offset can be adjusted, effectively reducing clock drift errors.

It should be noted that the main robustness of the proposed method to these phenomena of temperature variation or oscillator aging stems from its core design as a closed-loop, model-independent compensator. Because the algorithm continuously estimates and corrects for instantaneous clock drift (the derivative of the phase error) in real time, it inherently compensates for the net effect of any underlying cause of coherence drift, whether it be temperature change or oscillator aging.

3.1.1. Exponential Smoothing Forecasting

The exponential smoothing method is a time series forecasting method developed from the moving average method. Based on the number of smoothing iterations, the exponential smoothing method can be categorized into Exponential Moving Average (EMA), Double Exponential Smoothing (DES), and Triple Exponential Smoothing (TES). The Exponential Moving Average is suitable for forecasting data without significant trends or seasonal patterns. The Double Exponential Smoothing incorporates a trend component into the EMA, making it ideal for data with pronounced trend changes [14]. The Triple Exponential Smoothing (TES) extends the Exponential Moving Average (EMA) by incorporating both trend and seasonal components, making it well-suited for data with pronounced trends and seasonal variations.

In the absence of an EtherCAT slave synchronization mechanism, synchronization errors will gradually increase without compensation, exhibiting a clear upward trend [35], and no seasonal variations. Therefore, DES is chosen from the exponential smoothing methods.

3.1.2. Improved Clock Drift Compensation Method

The following are the steps for calculating the compensated clock drift:

Initialization:

level: $L_1=\Delta t_1$, trend: $T_1=\Delta t_2-\Delta t_1$. Here, $\Delta t_1$ is the clock drift value calculated during the first iteration using the clock drift formula, and $\Delta t_2$ is the value calculated during the second iteration.

Forecasting, level update:

$$L_k=\alpha \Delta t_k+(1-\alpha )(L_{k-1}+T_{k-1})$$

(5)

Trend update:

$$T_k=\beta (L_k-L_{k-1})+(1-\beta )T_{k-1}$$

(6)

Compensated clock drift:

$$\Delta C{t}_{i,k}=L_k+T_k$$

(7)

where $L_k$ is the level at the k-th iteration, $T_k$ is the trend at the k-th iteration, $\Delta C{t}_{i,k}$ is the clock drift compensation for slave i at the k-th iteration, and $\alpha$ and $\beta$ are the attenuation factors, with values ranging from 0 to 1.

After obtaining the compensated clock drift, subtract it from the clock offset $offset$ to obtain the new clock offset $newoffset$. Finally, write the $newoffset$ to the slave register for compensation.

$$newoffse{t}_i=offset-\Delta C{t}_{i,k}$$

(8)

3.2. Transmission Delay

When calculating the transmission delay between slaves, the ESC chip in EtherCAT slave devices adheres to the “0-3-1-2” port sequence for network transmission [36], as illustrated in Figure 2. Furthermore, the chip records only the timestamp corresponding to the reception of a data frame at each port. Therefore, determining the transmission delay of a slave involves utilizing the port latch times and the specified port sequence.

In the clock synchronization initialization phase, the master sends a data frame and records the number of slaves, the port of each slave that first receives the data frame, and the active ports of the slaves. Based on the number of connected slaves and the port transmission sequence of the slave chips, the master determines the parent slave and the parent port for each slave.

The transmission delay in the EtherCAT master–slave system primarily comprises the delay between the master station and the reference slave station, as well as the delay between non-reference slaves and the reference slave station.

3.2.1. Transmission Delay Between the Master and the Reference Slave

As shown in Figure 3, the transmission delay between the master and the reference slave is calculated by first recording the time when the master sends and receives the data frame, as well as the times when the reference slave receives the data frame at ports 0 and 1. The transmission delay $t{d}_m$ between the master and the reference slave is calculated using Equation (9) as follows [12]:

$$t{d}_m={\displaystyle \frac{(t_{m,1}-t_{m,0})-(t_{r,1}-t_{r,0})}{2}}$$

(9)

In the formula, $t_{m,0}$ represents the time when the master sends the data frame, $t_{m,1}$ represents the time when the master receives the returned data frame, $t_{r,0}$ represents the time when the data frame arrives at port 0 of the reference slave, and $t_{r,1}$ represents the time when the data frame arrives at port 1 of the reference slave.

Due to the jitter of the master clock, the transmission delays were uncertain and varied. Since the transmission delay exhibited no significant trend or seasonal variation, this study employed the EMA to calculate the compensated transmission delay between the master and the reference slave. The results were then written into the reference slave’s register for compensation. The calculation formula is as follows:

$$T{D}_{m,k}=\lambda ·t{d}_{m,k}+(1-\lambda )T{D}_{m,k-1}$$

(10)

In the formula, $T{D}_{m,k}$ represents the compensated transmission delay between the master and the reference slave at the k-th compensation. $\lambda$ is the smoothing factor, which ranges from 0 to 1. $t{d}_{m,k}$ is the uncompensated transmission delay between the master and the reference slave, and $T{D}_{m,k-1}$ is the transmission delay obtained from the previous compensation.

3.2.2. The Transmission Delay of Non-Reference Slaves

After calculating the transmission delay between the master and the reference slave, it is necessary to further compute the transmission delays between the reference slave and the other non-reference slaves. This involves calculating the time for a data frame to travel from the parent of slave i to the parent port of slave i.

$$R_{i,parent}=t_{i,parent}+p{d}_{i,parent}$$

(11)

$R_{i,parent}$ represents the time required for a data frame to travel from the parent of slave i to the parent port of slave i. $t_{i,parent}$ is the time at which the parent port of slave i receives the data frame, and $p{d}_{i,parent}$ is the time at which the previous active port of $t_{i,parent}$ receives the data frame.

If the number of slaves connected to slave i is greater than 1, the transmission time for the subsequent slaves of slave i must be calculated:

$$D_{i,follow}=p{t}_{i,first}+t_{i,first}$$

(12)

$D_{i,follow}$ represents the transmission time for the subsequent slaves of slave i, $t_{i,first}$ is the time at which the first port of slave i receives the data frame, and $p{t}_{i,first}$ is the time at which the previous active port of $t_{i,first}$ receives the data frame.

The formula used to calculate the transmission delay $T{D}_i$ of slave i is

$$T{D}_i={\displaystyle \frac{R_{i,parent}-D_{i,follow}}{2}}+T{D}_{parent}$$

(13)

In the formula, $T{D}_i$ represents the transmission delay of slave i, and $T{D}_{parent}$ represents the transmission delay of the parent slave of slave i.

3.3. Initial Clock Offset

To achieve time synchronization between the master and the slaves, the time of the master clock $syste{m}_m$ is typically used as the reference to calibrate the initial clock time of each slave when calculating their initial clock offsets. After the master clock calibrates the clock of the reference slave, the local clock of the reference slave is then used as the reference clock.

3.3.1. Clock Offset Between the Master and the Reference Slave

Due to the clock offset $offse{t}_r$ between the master and the reference clock, as well as the transmission delay $T{D}_{m,k}$ (with the master clock experiencing jitter, the compensated transmission delay $T{D}_{m,k}$ is used), the following equation holds:

$$syste{m}_m-T_{r,recv}=offse{t}_r+T{D}_{m,k}$$

(14)

Thus, the offset $offse{t}_r$ of the reference clock relative to the master clock can be calculated as follows:

$$offse{t}_r=syste{m}_m-T_{r,recv}-T{D}_{m,k}$$

(15)

3.3.2. Clock Offset of the Non-Reference Slave

When the data frame reaches the data processing unit of slave i, the local clock time $loca{l}_{t}ime$ of the slave, denoted as $T_{i,recv}$, is recorded. The transmission delay from the reference clock slave to slave i is denoted as $T{D}_i$. The clock offset $offse{t}_i$ between the slave and the reference clock can be calculated using the following formula:

$$offse{t}_i=syste{m}_m-T_{i,recv}-T{D}_{m,k}-T{D}_i$$

(16)

3.4. Implementation of Master–Slave Clock Synchronization

In EtherCAT master–slave clock synchronization, synchronization primarily relies on the master’s manipulation of the registers in the slave’s control chip, the ESC. The flow of the master–slave synchronization method is shown in Figure 4.

First, the master sends a data frame to obtain the number of slaves and port information, followed by determining the topology of the slaves. Using the port information, the master identifies the parent slave and the parent port for each slave. Next, the master records the time of sending and receiving data frames, along with the time when reference slave ports 0 and 1 receive the data frames. The transmission delay $t{d}_m$ between the master and the reference slave is then calculated. This initial transmission delay is recorded in the reference slave’s register. When the EMA is applied for the first time, $T{D}_{m,1}=t{d}_m$. Subsequently, the transmission delay of the slave is calculated based on the time for the data frame to leave the parent of the non-reference slave i and return to the parent port, the transmission time of the subsequent slaves, and the transmission delay of the parent slave. Then, the DES algorithm is applied to calculate the compensated clock drift $\Delta C{t}_{i,k}$, verify whether it falls below the threshold value (to prevent potential over-compensation), and derive the final compensation value. Finally, the new clock offset $newoffset$ is computed by subtracting the compensation value from the clock offset $offset$. This new offset is then written to the slave to perform clock error compensation. The compensation function flowchart is shown in Figure 5. This function periodically uses the EMA and DES to compensate for the transmission delay and clock drift between the master and the reference slave, based on the configured cycle. This helps to reduce clock synchronization errors among the slaves and improve synchronization performance.

4. Synchronization Test

In terms of software, a dual-kernel setup using Linux 4.9.69 and Xenomai 3.0.11 is employed to ensure real-time performance [37]. The open-source master SOME is used as the EtherCAT master [38]. In terms of hardware, the system is based on the Siasun SR4C industrial robot platform. Each Panasonic MINAS A6N servo drive used in this experiment integrates an EtherCAT Slave Controller (ESC) module compliant with the EtherCAT standard. Therefore, these drives function as standard EtherCAT slave devices at the hardware level. Compared with using independent ESC chipset-based boards, employing industrial servo drives provides a more practical validation scenario, as it better reflects real-world applications in multi-axis robotic systems. The controller uses the TL437x-EasyEVM ARM board [39] from Tronlong as the master controller, featuring an AM4379 ARM Cortex-A9 processor. The slaves consist of six Panasonic MINAS A6N series servo drives. The PC communicates with the master controller via a serial port to issue commands and acquire data.

The optimized EtherCAT master–slave synchronization method was applied to modify the open-source master SOME. The test platform, as shown in Figure 6, is a linear topology with one master and six slaves, configured for the EtherCAT master–slave synchronization test.

4.1. Testing Method

The SOME master implements the EtherCAT distributed clock synchronization mechanism, periodically sending synchronization error compensation data frames. During operation, the master sends an FPRD command to read the clock synchronization error from the last slave’s register.

To ensure the accuracy of the experiment, a cold reset is performed before each test to eliminate any influence from previous experiments on the current one.

To visually observe the control effect of synchronization errors after the system stabilizes, synchronization error data is collected every 1 ms. The system waits for the master to enter the operational state, and then 8000 samples are taken after the synchronization error has stabilized. The 8000 sample points are plotted into a histogram using MATLAB R2022b, with a fitted normal distribution curve superimposed. Additionally, the root mean square (RMS) and mean value curves are plotted against the number of samples. The master cycle is set to 1 ms for all experiments.

EtherCAT ensures real-time performance in industrial control through a strict time-deterministic mechanism. Operating on a fixed communication cycle (e.g., 1 ms), its core performance metrics, cycle time and communication jitter, directly dictate the system’s response speed and stability. Utilizing the Distributed Clock mechanism enables nanosecond-level synchronization between master and slave devices, guaranteeing precise timing for message transmission. The real-time communication performance of the master station can be effectively evaluated by measuring the data transmission delay.

To validate the effectiveness of the proposed method, comparative experiments were conducted under identical hardware conditions using the open-source SOME master. Four synchronization methods were tested: clock rate adjustment (ACR), EMA, the proposed DES method, and the improved method. These experiments were conducted in environments with two slaves and six slaves, respectively.

The clock rate adjustment method (ACR) controls the slave’s clock rate by determining the sign of the clock drift. When this method is used to control synchronization error, the resulting clock synchronization error histograms are shown in Figure 7a and Figure 8a.

The method described in Reference [13], which uses only the EMA to compensate for the clock drift of each slave, was implemented. The smoothing factor $\lambda =0.5$. The synchronization error histograms obtained using this method are shown in Figure 7b and Figure 8b.

The DES described in Section 3.1 was used to compensate for the clock drift of each slave. During this process, the decay factors $\alpha$ and $\beta$ were set to 0.9 and 0.5, respectively, while the threshold is set to 5000 ns. The synchronization error histograms obtained using the DES are shown in Figure 7c and Figure 8c.

Additionally, the proposed improved method combines the EMA to compensate for the transmission delay between the master and the reference slave with the DES to compensate for the clock drift of each slave. In this improved method, the smoothing factor for the EMA is set to $\lambda =0.3$, while the decay factors for the DES, $\alpha$ and $\beta$, are set to 0.9 and 0.5, respectively. The synchronization error histograms obtained using the improved method are shown in Figure 7d and Figure 8d.

Figure 9 and Figure 10 show the comparison of the Mean and RMS curves for each method in the 2-slave and 6-slave experimental groups, respectively. The root mean square (RMS) is a key indicator for measuring data dispersion. A smaller RMS value indicates lower data dispersion [40,41].

The synchronization error statistical results for the two-slave and six-slave experimental groups are shown in

Table 1. Synchronization error for 2 slaves.

	ACR	EMA	DES	Imp Meth
Mean (ns)	−16	−3	−4	−3
Max (ns)	27	31	48	34
Min (ns)	−47	−43	−45	−45

and

Table 2. Synchronization error for 6 slaves.

	ACR	EMA	DES	Imp Meth
Mean (ns)	18	−2	−5	−1
Max (ns)	123	101	99	89
Min (ns)	−96	−113	−99	−90

.

4.2. Results Analysis

By combining Table 1 with the synchronization error histograms for the two-slave methods, it is evident that the clock rate adjustment method (ACR) in the two-slave experimental group exhibits the largest absolute average synchronization error, while the improved method demonstrates the smallest such error. However, by observing the comparison of the mean value curves for each method in Figure 9a, it can be seen that as the number of sampling points increases, the mean values of the improved method and EMA exhibit greater stability, clearly outperforming the other methods. The comparison of the RMS curves in Figure 10a further confirms this observation. The improved method and EMA have smaller RMS values. In the two-slave group, the RMS value of EMA consistently remains the smallest, indicating that this method exhibits the lowest synchronization error dispersion. Therefore, under the experimental conditions with two slaves, both the improved method and EMA demonstrate advantages in terms of mean value stability and synchronization error dispersion.

Based on Table 2 and the synchronization error histograms for each method in the six-slave group, it is evident that the improved method in the six-slave group exhibits the smallest absolute average synchronization error and the narrowest synchronization error range. The EMA method ranks second in terms of absolute average synchronization error. At the same time, the synchronization error range of DES is relatively small compared to the other methods, except for the improved method. Further analysis of the mean and RMS curves in Figure 9b and Figure 10b reveals that, as the sample size increases, DES exhibits lower synchronization error dispersion. Moreover, the RMS curve of the improved method, which includes transmission delay compensation, remains more stable than the other methods, indicating that the improved method has better robustness. Therefore, in the six-slave experimental scenario, DES also exhibits relatively low synchronization error dispersion. The improved method demonstrates certain advantages in synchronization error control. In addition, preliminary results indicate that the proposed method maintains robust synchronization performance as the number of slaves increases, consistently achieving stable timing accuracy in expanded network configurations. Although the current experiments involve six slaves, the proposed synchronization framework is inherently scalable. When extended to large-scale systems with over 100 synchronized motor drives, the approach can maintain precise timing through distributed delay compensation and DES-based clock drift correction. Each slave can perform local synchronization using DES while remaining globally aligned with the master, ensuring stable performance under higher network loads.

5. Conclusions

This paper conducts an in-depth study and analysis of the distributed clock synchronization principle and synchronization mechanism of the EtherCAT master–slave system, focusing on the shortcomings in synchronization accuracy. Building upon the EMA clock drift compensation method and the master–slave transmission delay compensation method, this paper proposes an improved EtherCAT master–slave synchronization optimization method based on DES. In the initial stage of synchronization, the transmission delay between the master and the reference slave is calculated and written into the register for compensation. During the synchronization process, each non-reference slave experiences clock drift, which is compensated for using the DES. Additionally, due to significant clock jitter at the EtherCAT master during operation, this paper also employs the EMA method to compensate for the transmission delay between the master and the reference slave. Experimental results show that the proposed improved method achieves high synchronization performance in a six-slave experimental scenario. Synchronization errors were controlled within a range of ±90 ns, with the average synchronization error stabilizing around zero. Compared to using only the EMA for clock drift compensation, the proposed method reduced the synchronization error range by approximately 16.36%, significantly improving synchronization accuracy among EtherCAT slaves.

In future work, we plan to significantly enhance the robustness and practical applicability of our delay estimation and compensation framework. Firstly, we will extend our investigation to model and compensate for the combined effects of dynamic network load, data packet loss, and delay jitter, which are critical factors in real-world industrial networks. This will involve conducting comprehensive uncertainty and sensitivity analyses to rigorously quantify the impact of these stochastic factors on synchronization performance. Secondly, to firmly establish the statistical significance of any performance improvements resulting from these advanced models, we will employ rigorous statistical testing methodologies [42,43], including Analysis of Variance (ANOVA) and t-tests, on data from extensive repeated experiments. These steps will provide a more robust validation of our method and strengthen its foundation for industrial deployment. Furthermore, we plan to validate the proposed algorithm in large-scale EtherCAT networks comprising more than 100 synchronized slave nodes to comprehensively evaluate its scalability and robustness under high communication loads. Future research will also focus on integrating adaptive parameter tuning and distributed delay estimation mechanisms to further enhance real-time performance and synchronization stability in complex industrial environments.