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Article

Two-Degree-of-Freedom Proportional Integral Controllers for Stability Enhancement of Power Electronic Converters in Weak Grids: Inverter and Rectifier Operating Modes

by
Ricardo Vidal-Albalate
*,
José Jesús Tejedor Bomboi
,
Carlos Díaz-Sanahuja
and
Ignacio Peñarrocha-Alós
Department of Industrial Systems Engineering and Design, Universitat Jaume I, 12071 Castelló de la Plana, Spain
*
Author to whom correspondence should be addressed.
Electronics 2025, 14(8), 1565; https://doi.org/10.3390/electronics14081565
Submission received: 28 February 2025 / Revised: 29 March 2025 / Accepted: 9 April 2025 / Published: 12 April 2025

Abstract

:
Future power generation plants will be largely based on renewable energy sources such as wind or photovoltaic power. These plants are connected to the grid through power electronic converters, which may present stability problems, specifically in weak grids. Consequently, numerous stabilities studies have been conducted. In these studies, converters work as inverters; however, in power electronic interfaced loads, energy storage systems or High-Voltage Direct Current (HVDC) links, power converters can also function as a rectifier. Stability studies focusing on the rectifier operation have received little attention in previous research. In this paper, the Voltage Source Converter (VSC) stability is analysed for both the inverter and rectifier modes, with particular focus on the influence of the Phase-Locked Loop (PLL) and the current controllers’ bandwidths. Additionally, a Two-Degree-of-Freedom Proportional Integral (2DOF-PI) controller is proposed to expand the stable operating range. The stability study is carried out using a small-signal model validated through PSCAD simulations. The results show that for inverter operations, a slow PLL and fast current controllers yield better performance, whereas for rectifier operation, a fast PLL and slow current controllers are recommended. Finally, a robustness study based on the H -norm is carried out to provide some tuning recommendations for the controller parameters, confirming the different behaviour in inverter and rectifier operation.

1. Introduction

The European Union (EU) aims to attain a minimum share of 42.5% of renewable energy in total energy consumption by 2030 [1]. Meeting this objective will heavily rely on electric power systems given their capacity to integrate renewable energy sources. For instance, the Spanish National Integrated Plan of Energy and Climate (PNIEC) has set an objective of 81% for the renewable energy generation in the Spanish power system by 2030 [2]. In this context, generation is shifting from conventional power plants based on synchronous generators to renewable power plants driven by power electronics.
Future power systems will, therefore, be dominated by inverter-based generation (IBG). However, this transition introduces some challenges, as identified by the Transmission System Operators (TSOs), including a reduction in the system inertia, lower transient stability margins, subsynchronous and harmonic resonances and synchronisation of the IBGs with the main grid [3,4]. These stability issues can be classified at the converter level, multiple converter level and system level [5]. Among the converter-level stability problems, weak grid-connected instability is emerging in grids with little or no synchronous generation, which reduces the short circuit ratio (SCR) [6,7].
Although grid-forming (GFM) converters are envisaged as a promising solution for future power grids to overcome some stability challenges [8], at present, Voltage Source Converters (VSCs) are still equipped with grid-following (GFL) controls, typically PI controllers in a synchronous reference frame (SRF) to regulate the active and reactive power [9]. However, GFL converters are more prone than GFM converters to present instability problems in weak grids [10]. Several studies have already analysed the main factors affecting the stability [11,12,13], highlighting that reduced active power, lower Phase-Locked Loop (PLL) bandwidths, reactive power injection or smaller electrical distances are beneficial for system stability. Simultaneously, various instability mitigation methods such as passive filters, active damping, increase in the grid strength, set-point adjustment or controller parameterisation have been proposed [14]. Among them, most of the research proposals are mainly focused on controller tuning since it is the easiest and most affordable solution.
The authors of [11] analysed the impact of system resistances on stability, finding that line resistances can provide positive damping, thereby improving the system stability, whereas converter resistances worsen it. The interactions among the PLL, inner current and outer power controllers are examined in [15], highlighting that, in weak grids, the controllers cannot be designed independently due to their interdependencies. Additionally, the study defines a stability region for tuning the controller parameters to ensure safe operation.
When injecting current, the voltage at the point of common coupling (PCC) is unintentionally manipulated, affecting both the PLL measurements and the power control loop, resulting in an unintended positive feedback loop that deteriorates the converter stability in weak grids [16], especially when the integral time constants of the current controllers are small (i.e., for fast inner current controllers) [17]. This feedback loop, driven by the dependence of the current reference on the PCC voltage when computed from the power references, makes the system sensitive to voltage deviations. Although its impact can be mitigated through control strategies such as V/Q control strategies in high-voltage grids, it negatively affects the converter stability. A virtual impedance for enhancing the stability of VSC in weak grids is proposed in [18]. The authors of [19] compared the stable operating zones of vector current control (VCC) and power synchronisation control (PSC), concluding that power synchronisation control is superior when the VSC is connected to weak grids.
The PLL, needed to obtain the voltage angle in GFL converters, is identified as one of the main destabilising factors, requiring lower PLL bandwidths as the SCR decreases [13,20,21]. In [16], several instability sources are analysed, and a design methodology using a PLL-free strategy for minimising the SCR level at which the VSC can operate is presented. Similarly, the PSC utilises an internal synchronisation mechanism similar to the operation of a synchronous machine to avoid PLL-induced instability in weak grids [22]. To enhance stability, a variable virtual impedance to increase the damping ratio of the PLL and an adaptive coefficient control is proposed in [23]. An adaptive PLL where the parameters of the PI controller are adjusted online according to the measured grid impedance is proposed in [24]. Reducing the PLL bandwidth as the grid strength decreases helps ensure stability but slows the transient response.
Power electronic-based loads are gaining importance in power systems, where the power converters operate as rectifiers rather than inverters. Other applications, such as battery energy storage systems or embedded modular multilevel converter (MMC)-based HVDC links, which require bidirectional power flow, will also become more prevalent in future power systems. In these cases, power converters can work in both modes, that is, rectifier and inverter modes [25,26].
At present, since most power converters are associated with renewable power plants, previous studies typically consider the inverter operation but not the rectifier operation. In this paper, the VSC stability when operating as a rectifier is analysed and compared to its operation as an inverter, highlighting the different impacts that the current and PLL controller bandwidths in both operating modes have on the stability. For the current controllers, the influence of the weighting factor used in Two-Degree-of-Freedom Proportional Integral (2DOF-PI) controllers is also analysed for both operating modes. These controllers enhance performance by decoupling control of the reference and plant dynamics, leading to better stability, faster responses, and enhanced robustness [27]. Additionally, a robustness study based on the H -norm of the sensitivity transfer function matrix is proposed to determine those combinations of PLL and current controller bandwidths that ensure not only a stable operation but also an appropriate dynamic response. The results of this work show that the design rules for the current and PLL controllers are entirely dependent on the operating mode. While in the inverter operation, a slow PLL and fast current controllers provide a better dynamic response, in rectifier operation, a fast PLL and slow current controllers are required. Regarding the weighting factor of 2DOF-PIs, it is found to have a negligible impact on inverter operation. However, in inverter operation, it significantly affects stability, with a low value being beneficial.
The rest of the paper is organised as follows: Section 2 describes the system, which consists of a VSC connected to a weak grid, and Section 3 develops the small-signal state-space model used for the stability studies. A stability analysis of both rectifier and inverter operation is conducted in Section 4, highlighting the differences in terms of stability between both operating modes. A robustness study based on the H -norm is carried out in Section 5. Finally, some concluding remarks including some tuning recommendations for the controller parameters are provided in Section 6.

2. System Description

Figure 1 shows the system under study, which consists of an 8 MW VSC converter, an output LC filter ( L 1 , R 1 , R f , C f ), a 9.2 MVA step-up 0.690/66 kV transformer ( R T , L T ) and a 66 kV ac grid modeled by its Thévenin impedance ( L g and R g ). Considering a two-level converter with a switching frequency of 2500 Hz, the filter is designed to reduce the current ripple below 2% of the rated current, with a resonant frequency at 769.5 Hz. Further details can be found in [28]. The system parameters are presented in Table 1.
A standard grid-following control based on vector current control in the synchronous reference frame is used. The active and reactive power references are converted into d and q axis current references, respectively, and two 2DOF-PI controllers along with feed-forward terms determine the voltage to be generated by the converter.
The angle of the PCC voltage ( V c p ) is obtained by means of a PLL based on the synchronous reference frame, shown in Figure 2. It determines the grid angle by controlling the q-axis voltage to zero ( V c p q = 0 ). Thus, the PCC voltage is aligned with the d-axis of the SRF. The closed-loop transfer function of the PLL is
G p = k p p s + k i p s 2 + k p p s + k i p
where k p p and k i p are the proportional and integral gains of the controller. These values can be calculated by comparing (1) with the transfer function of a second-order system, as carried out in [15,20]:
k p p = 2 ξ p ω n p
k i p = ω n p 2
where ξ p is the damping factor and ω n p is the natural frequency.
Figure 3 shows the current control loop, which employs 2DOF-PIs. The closed-loop transfer function is
G c = 1 L 1 ( b k p c s + k i c ) s 2 + k p c + R 1 L 1 s + k i c L 1
where k p c and k i c are the proportional and integral gains of the current controllers and b is the reference weighting factor.
To tune the current controllers, the methodology employed in this work is analogous to that used for the PLL, in which the closed-loop transfer function in (4) is compared with a standard second-order form. If the zeros in the numerator are neglected, the settling time at 98% t s 98 can be expressed approximately as
t s 98 4 ξ c ω n c
where ξ c and ω n c are the damping factor and the natural frequency of (4), respectively. Hence, by specifying a desired settling time and ξ c c , it is possible to determine the proportional and integral gains that achieve the target response as
k p c = 2 ξ c ω n c L 1 R 1
k i c = ω n c 2 L 1

3. Small-Signal Model

In this section, the small-signal model is presented, which is then validated against EMT-PSCAD simulations.

3.1. State-Space Representation

The eigenvalue method is used in this paper to study the stability of the system. The state-space representation of the system is carried out in the synchronous reference frame dq, with the following state variables:
x = [ I 1 d , I 1 q , x c d , x c q , θ , x p l l , I 2 d , I 2 q , V c d , V c q ] T
where I 1 d and I 1 q are the d- and q-axis VSC output currents, respectively; I 2 d and I 2 q are the transformer currents; V c d and V c q are the capacitor voltages. x c d , x c q and x p are the integral terms of the current and PLL PIs, respectively. θ is the angular difference between the SRF determined by the PLL and a reference frame rotating at the grid frequency:
θ = ( ω p l l ω g ) d t
where ω p l l is the angular frequency determined by the PLL and ω g is the grid frequency (see Figure 2).
The equations of the transformer and the grid, as a function of the states, are
I . 2 d = R 2 L 2 I 2 d + ω I 2 q V g d L 2 + V c d + R f ( I 1 d I 2 d ) L 2 I . 2 q = R 2 L 2 I 2 q ω I 2 d V g q L 2 + V c q + R f ( I 1 q I 2 q ) L 2
where R 2 = R T + R g , L 2 = L T + L g and ω is the angular speed of the dq frame. Note that the last terms of Equation (9) refer to the d- and q-axis PCC voltages, respectively:
V c p d = V c d + R f ( I 1 d I 2 d ) V c p q = V c q + R f ( I 1 q I 2 q )
The equations of the filter capacitor are
V . c d = 1 C f ( I 1 d I 2 d ) + ω V c q V . c q = 1 C f ( I 1 q I 2 q ) ω V c d
The equations of the series filter branch, expressed in terms of the states, are
I . 1 d = R 1 L 1 I 1 d + ω I 1 q + V v d L 1 V c d + R f ( I 1 d I 2 d ) L 1 I . 1 q = R 1 L 1 I 1 q ω I 1 d + V v q L 1 V c q + R f ( I 1 q I 2 q ) L 1
where V v d and V v q are the d- and q-axis voltages generated by the VSC, respectively.
Neglecting delays, the output VSC voltage can be considered to be equal to its reference, that is, V v d = V v d * and V v q = V v q * , where V v d * and V v q * are determined by the current PI controllers and the feed-forward terms (see Figure 1). In practice, short delays arise from sampling, control computation, and the discrete update of the PWM signals. However, these delays typically lie in the microsecond range, much smaller than the dominant dynamic time constants considered here, and can therefore be neglected in the small-signal analysis. Therefore, the output voltages of the VSC can be expressed in terms of the state variables as
V v d = k p c ( b I 1 d * I 1 d ) + k i c x c d ω L 1 I 1 q + V c d + R f ( I 1 d I 2 d ) V v q = k p c ( b I 1 q * I 1 q ) + k i c x c q + ω L 1 I 1 d + V c q + R f ( I 1 q I 2 q )
x . c d = I 1 d * I 1 d x . c q = I 1 q * I 1 q
where I 1 d * and I 1 q * are the VSC current references in the d- and q-axis.
Replacing (13) in (12),
I . 1 d = R 1 L 1 I 1 d + k p c L 1 ( b I 1 d * I 1 d ) + k i c L 1 x c d I . 1 q = R 1 L 1 I 1 q + k p c L 1 ( b I 1 q * I 1 q ) + k i c L 1 x c q
The PLL equations, with the d-axis aligned on the PCC voltage, can be expressed as a function of the states as
θ . = k p p V c q + R f ( I 1 q I 2 q ) + k i p x p x . p = V c q + R f ( I 1 q I 2 q )
where θ . = Δ ω is the angular frequency deviation with respect to the grid frequency ω g .
Even though the grid frequency ω g is constant, ω in (9) and (11) cannot be regarded as constant during transients since Δ ω = θ . = k p p l l V c q + R f ( I 1 q I 2 q ) + k i p l l x p l l . Therefore, the system is not linear. In the literature, two dq reference frames are commonly used, one rotating at a constant speed determined by the grid frequency ( ω g ) and another one rotating at the frequency obtained from the PLL ( ω p l l ), which is not constant during transients [11,17,20]. Equations (9) and (11) are expressed in the synchronous reference frame rotating at ω g so the equations are linear. Equations (14)–(16) are written in the PLL frame rotating at a variable speed; however, ω is not involved, so the equations are also linear. Nonetheless, this methodology requires a frame transformation of the state variables between both frames.
In this paper, only one frame rotating at the speed determined by the PLL is used ( ω p l l ), so Equations (9) and (11) must linearise at an operating point denoted by subscript 0. Therefore, ω = ω p l l in Equations (9) and (11) and the angular frequency at the operating point where the system is linearised, ω 0 , is ω g .
The non-linear terms ω I 2 d and ω I 2 q of Equation (9) are linearised as
Δ ( ω I 2 q ) ( ω I 2 q ) ω | ω 0 , I 2 q 0 Δ ω + ( ω I 2 q ) I 2 d | ω 0 , I 2 q 0 Δ I 2 d = I 2 q 0 Δ ω + ω 0 Δ I 2 q Δ ( ω I 2 d ) ( ω I 2 d ) ω | ω 0 , I 2 d 0 Δ ω + ( ω I 2 d ) I 2 q | ω 0 , I 2 d 0 Δ I 2 q = I 2 d 0 Δ ω + ω 0 Δ I 2 d
Therefore, Equation (9) is rewritten as
Δ I . 2 d = R 2 L 2 + R f L 2 Δ I 2 d + I 2 q 0 Δ ω + ω 0 Δ I 2 q 1 L 2 Δ V g d + 1 L 2 Δ V c d + R f L 2 Δ I 1 d Δ I . 2 q = R 2 L 2 + R f L 2 Δ I 2 q I 2 d 0 Δ ω ω 0 Δ I 2 d 1 L 2 Δ V g q + 1 L 2 Δ V c q + R f L 2 Δ I 1 q
The PLL aligns the d-axis of the SRF with the PCC voltage, so V c p q = 0 . The grid voltages can be written as (see Figure 4)
V g d = V g c o s ( δ ) V g q = V g s i n ( δ )
where V g is the line-to-ground value of the grid voltage and δ is the angle difference between the PCC and the grid voltages. Linearising Equation (19),
Δ V g d V g d V g | V g 0 , δ 0 Δ V g + V g d δ | V g 0 , δ 0 Δ δ = cos δ 0 Δ V g V g 0 sin δ 0 Δ δ = cos δ 0 Δ V g + V g q 0 Δ δ Δ V g q V g q V g | V g 0 , δ 0 Δ V g + V g q δ | V g 0 , δ 0 Δ δ = sin δ 0 Δ V g V g 0 cos δ 0 Δ δ = sin δ 0 Δ V g V g d 0 Δ δ
The increase in the voltage angle difference Δ δ (Figure 4) is the same as that measured by the PLL ( Δ θ = θ θ 0 ). Moreover, assuming that the grid voltage amplitude does not change, Equation (20) can be simplified as
Δ V g d = V g q 0 Δ θ Δ V g q = V g d 0 Δ θ
Taking into account that Δ ω = Δ θ . , and replacing (16) and (20) in (18), the expression for the transformer current is obtained:
Δ I . 2 d = R 2 L 2 + R f L 2 Δ I 2 d + k p p I 2 q 0 Δ V c q + ω 0 k p p R f I 2 q 0 Δ I 2 q + k p p R f I 2 q 0 Δ I 1 q + k i p I 2 q 0 Δ x p V g q 0 L 2 Δ θ + 1 L 2 Δ V c d + R f L 2 Δ I 1 d Δ I . 2 q = R 2 L 2 R f L 2 + k p p R f I 2 d 0 Δ I 2 q + 1 L 2 k p p I 2 d 0 Δ V c q + R f L 2 k p p R f I 2 d 0 Δ I 1 q k i p I 2 d 0 Δ x p ω 0 Δ I 2 d + V g q 0 L 2 Δ θ
Similarly, the non-linear terms ω V c q and ω V c d of Equation (11) are linearised as
Δ ( ω V c q ) ( ω V c q ) ω | ω 0 , V c q 0 Δ ω + ( ω V c q ) V c q | ω 0 , V c q 0 Δ V c q = V c q 0 Δ ω + ω 0 Δ V c q Δ ( ω V c d ) ( ω V c d ) ω | ω 0 , V c d 0 Δ ω + ( ω V c d ) V c d | ω 0 , V c d 0 Δ V c d = V c d 0 Δ ω + ω 0 Δ V c d
Replacing (16) and (23) in (11),
Δ V . c d = 1 C f Δ I 1 d 1 C f Δ I 2 d + V c q 0 k p p R f Δ I 1 q V c q 0 k p p R f Δ I 2 q + V c q 0 k i p Δ x c p + ω 0 + V c q 0 k p p Δ V c q Δ V . c q = 1 C f V c d 0 k p p R f Δ I 1 q + 1 C f + V c d 0 k p p R f Δ I 2 q V c d 0 k p p Δ V c q V c d 0 k i p Δ x c p ω 0 Δ V c d
In (14) and (15), the d- and q-axis current references are computed from the active and reactive power references, which can be expressed as a function of the states as
I 1 d * = P * 3 V c p d = P * 3 ( V c d + R f ( I 1 d I 2 d ) ) I 1 q * = Q * 3 V c p d = Q * 3 ( V c d + R f ( I 1 d I 2 d ) )
Linearising Equation (25),
Δ I 1 d * = I 1 d * P * Δ P * + I 1 d * V c p d Δ V c p d = 1 3 V c p d 0 Δ P * P 0 3 V c p d 0 2 Δ V c d + R f Δ I 1 d R f Δ I 2 d Δ I 1 q * = I 1 q * Q * Δ Q * + I 1 q * V c p d Δ V c p d = 1 3 V c p d 0 Δ Q * + Q 0 3 V c p d 0 2 Δ V c d + R f Δ I 1 d R f Δ I 2 d
Replacing (26) in (14), we obtain the linearised equation in terms of the power references:
Δ x . c d = 1 3 V c p d 0 Δ P * P 0 3 V c p d 0 2 Δ V c d P 0 3 V c p d 0 2 R f + 1 Δ I 1 d + P 0 3 V c p d 0 2 R f Δ I 2 d Δ x . c q = 1 3 V c p d 0 Δ Q * + Q 0 3 V c p d 0 2 Δ V c d + Q 0 3 V c p d 0 2 R f Δ I 1 d Q 0 3 V c p d 0 2 R f Δ I 2 d Δ I 1 q
Finally, replacing (26) in (15), the linearised equations are
Δ I . 1 d = R 1 L 1 + k p c L 1 + P 0 R f k p c b 3 V c p d 0 2 L 1 Δ I 1 d + P 0 R f k p c b 3 V c p d 0 2 L 1 Δ I 2 d P 0 k p c b 3 V c p d 0 2 L 1 Δ V c d + k i c L 1 Δ x c d + k p c b 3 V c p d 0 2 L 1 Δ P * Δ I . 1 q = Q 0 R f k p c b 3 V c p d 0 2 L 1 Δ I 1 d R 1 L 1 + k p c L 1 Δ I 1 q Q 0 R f k p c b 3 V c p d 0 2 L 1 Δ I 2 d + Q 0 k p c b 3 V c p d 0 2 L 1 Δ V c d + k i c L 1 Δ x c q k p c b 3 V c p d 0 2 L 1 Δ Q *
The whole linearised system is described by Equations (16), (22), (24), (27) and (28). The state-space representation is
x . = A x + B u
where the state (A) and input (B) matrices are
A = R 1 + k p c L 1 k p c L 1 b P 0 R f 3 V c p d 0 2 0 k i c L 1 0 0 0 k p c L 1 b P 0 R f 3 V c p d 0 2 0 k p c L 1 b P 0 3 V c p d 0 2 0 k p c L 1 b Q 0 R f 3 V c p d 0 2 R 1 + k p c L 1 0 k i c L 1 0 0 k p c L 1 b Q 0 R f 3 V c p d 0 2 0 k p c L 1 b Q 0 3 V c p d 0 2 0 1 P 0 R f 3 V c p d 0 2 0 0 0 0 0 P 0 R f 3 V c p d 0 2 0 P 0 3 V c p d 0 2 0 Q 0 R f 3 V c p d 0 2 1 0 0 0 0 Q 0 R f 3 V c p d 0 2 0 Q 0 3 V c p d 0 2 0 0 R f k p p 0 0 0 k i p 0 R f k p p 0 k p p 0 R f 0 0 0 0 0 R f 0 1 R f L 2 R f k p p I 2 q 0 0 0 V g q 0 L 2 k i p I 2 q 0 R 2 + R f L 2 ω 0 R f k p p I 2 q 0 1 L 2 k p p I 2 q 0 0 R f L 2 R f k p p I 2 d 0 0 0 V g d 0 L 2 k i p I 2 d 0 ω 0 R 2 + R f L 2 + R f k p p I 2 d 0 0 1 L 2 k p p I 2 d 0 1 C f R f k p p V c p q 0 0 0 0 k i p V c p q 0 1 C f R f k p p V c p q 0 0 ω 0 + k p p V c p q 0 0 1 C f R f k p p V c p q 0 0 0 0 k i p V c p d 0 0 1 C f + R f k p p V c p d 0 ω 0 k p p V c p d 0
B = k p c L 1 b 3 V c p d 0 0 0 k p c L 1 b 3 V c p d 0 1 3 V c p d 0 0 0 1 3 V c p d 0 0 0 0 0 0 0 0 0 0 0 0 0
The input vector u is
u = Δ P * Δ Q *

3.2. Model Validation

To validate the state-space representation, the results of the small-signal model are compared with those obtained from PSCAD simulations (Figure 5). With the parameters presented in Table 2, the current controllers have a settling time of 20 ms and an overshoot lower than 4.3%. The bandwidth of the PLL is approximately 25 Hz.
Initially, the converter generates P 0 = 6 MW (0.75 pu) and Q 0 = 2 MVAr capacitive (0.25 pu), and at t = 2 ms, the active power is changed to 6.16 MW (0.02 pu step change). The values of the currents ( I 1 d 0 , I 1 q 0 , I 2 d 0 , I 2 q 0 ), PCC voltage ( V c p d 0 ) and angle θ 0 at the initial operating point are obtained by solving Equations (9), (10), (19) and (25), assuming that the derivative terms are zero (see Table 3).
Figure 5a,b show the d- and q-axis components of the output VSC and grid currents, respectively ( I 1 and I 2 in Figure 1). It can be seen that the d-axis current increases while the q-axis current remains unchanged since the d-axis of the synchronous reference frame is aligned with the PCC voltage. Figure 5c displays the d- and q-axis components of the PCC voltage. The q-axis component returns to zero due to the PLL control while the d-axis component is negative, meaning that the voltage at the PPC decreases due to a higher voltage drop caused by a higher current. The angle increase measured by the PLL is shown in Figure 5d. Finally, the active and reactive powers are depicted in Figure 5e. It can be noted that the results obtained from both models are superimposed during the whole transient, thereby validating the small-signal model.

4. System Stability

This section analyses the different impacts of the PLL and current controller design on the stability when the VSC operates as an inverter (injecting power) and rectifier (absorbing power).

4.1. PLL Bandwidth

Next, the effect of the PLL natural frequency, and by extension its bandwidth, on the stability is studied. The PLL damping ratio is fixed at ξ = 1 , while the PLL natural frequency is changed. The parameters of the current controllers, unless otherwise stated, are those presented in Table 2.

4.1.1. Inverter Mode

Considering that the VSC generates P = 1 pu and Q = 0 pu, Figure 6 shows the root locus plot for different PLL natural frequencies (10, 15, 20, 25 and 30 Hz) when the VSC is connected to a grid with an SCR of 2. It can be seen that as the PLL bandwidth increases, a pair of complex poles moves towards the positive plane, thereby destabilising the system. Hence, a high PLL bandwidth may destabilise the system when injecting power into the grid ( P > 0 ) as identified in other studies [11,20].
A zoomed-in view of the root locus is shown in Figure 7, indicating system instability when the PLL natural frequency exceeds 21 Hz. For that value, the pair of complex poles is 1.8 ± 813.7 j , that is, highly undamped poles ( ξ = 0.0022 ) with an oscillating frequency of 129.5 Hz.
The same findings are obtained from the PSCAD model for two PLL designs with two different natural frequencies close to the stability limit, namely 20 and 21 Hz (Figure 8). The active power is changed from 0.99 to 1 pu at t = 0.5 s, resulting in a very undamped but stable response for both PLL designs. When the power is increased to 1.01 pu at t = 2 s, the system becomes unstable when the PLL natural frequency is 21 Hz with an oscillating frequency of 129.6 Hz. However, it is stable when the PLL natural frequency is 20 Hz. Therefore, both the small-signal model and PSCAD simulations consistently highlight the beneficial impact of a slower PLL on the system stability. Note that these simulations deliberately explore the limits of stability and are not intended to comply with interconnection standards (e.g., IEEE 1547 [29] or IEEE 2800 [30]). Therefore, neither of these controller designs would be acceptable in a real system. The goal here is to demonstrate the different behaviours of the rectifier and inverter that may make the system unstable rather than offer a fully compliant controller solution.

4.1.2. Rectifier Mode

The same analysis is repeated for the VSC rectifier operation. The VSC absorbs P = −1 pu and Q = 0 pu. Figure 9 shows the root locus plot for different PLL natural frequencies (10, 15, 20, 25 and 30 Hz) when the VSC is connected to a grid with an SCR of 3. Note that a pair of complex poles shifts from the positive plane to the negative plane when the PLL natural frequency increases, thereby stabilising the system. Hence, when the VSC operates as a rectifier ( P < 0 ), a low PLL bandwidth may destabilise the system, in contrast to the behaviour observed in the inverter mode.
Figure 10 shows a zoomed-in view of the root locus, revealing system instability when the PLL natural frequency is below 22.25 Hz. For that value, the pair of complex poles is 0.1 ± 1033.1 j , that is, highly undamped poles ( ξ = 0.0001 ) with an oscillating frequency of 164.4 Hz.
The same results are obtained from the PSCAD model for two PLL designs with two different natural frequencies close to the stability limit, namely 22.25 Hz and 25.25 Hz (Figure 11). The active power is changed from −0.99 to −1 pu at t = 0.5 s, with both PLL designs being very undamped but stable. When the power is increased to −1.01 pu at t = 2 s, the system becomes unstable when the PLL natural frequency is 22.25 Hz, with an oscillating frequency around 164 Hz. Conversely, it remains stable when the PLL natural frequency is 25.25 Hz. Therefore, both the small-signal model and PSCAD simulations consistently highlight the beneficial impact of a faster PLL on the system stability.
Figure 8 and Figure 11 have been obtained from an ideal VSC model. The results using a detailed model considering PWM, dead times, delays and noise are presented in Appendix A. However, the conclusions regarding the impact of the PLL bandwidth remain the same.

4.2. Current Controllers

For the parameters of the current controllers presented in Table 4, Figure 12 shows the maximum PLL natural frequency as a function of the SCR for inverter mode. Similarly, Figure 13 shows the minimum PLL natural frequency as a function of the SCR for rectifier mode. Note that in Figure 12, the stable region is below the curves, whereas in Figure 13, the stable region is above the curves.
In inverter mode (Figure 12), it can be seen that for higher SCRs, higher PLL bandwidths are allowed. For a given PLL design (natural frequency), faster current controllers can be connected to grids with lower SCRs. Moreover, the faster the current controller, the greater its impact (note that the difference between the 30 ms and 20 ms curves is smaller than the difference between the 20 ms and 10 ms curves).
In rectifier mode (Figure 13), it can be observed that higher SCRs allow for lower PLL bandwidths. For a given PLL design (natural frequency), slower current controllers enable connection to grids with lower SCRs. Moreover, the faster the current controller, the greater its negative impact (note that the difference between the 20 ms and 25 ms curves is larger than that between the 25 ms and 30 ms curves).
Again, the impact of the current controller differs in rectifier and inverter operation. While faster current controllers benefit the stability in inverter operation, they worsen the stability in rectifier mode.

4.3. Weighting Factor b of Current Controllers

This section analyses the influence of the reference weighting factor b of the 2DOF-PI on the system stability. This parameter attenuates the impact of the reference on the proportional action, reducing overshoot in transient responses. This adjustment is useful for improving the system’s response to reference changes without compromising disturbance rejection.
For inverter operation, Figure 14 shows the relation between the PLL natural frequency, the grid SCR and the parameter b for four settling times of the current controllers in Table 4. The weighting factor worsens the stability, with b = 1 being the best value regardless of the settling time of the current controller. The effect of the parameter b is more pronounced for faster current controllers. Thus, for inverter operation, the best choice is b = 1.
Similarly, for rectifier operation, Figure 15 shows the relation between the PLL natural frequency, the grid SCR and the parameter b for four settling times of the current controllers. In contrast to the inverter operation, the weighting factor enhances the system stability, with lower values of b being the best choice regardless of the settling time of the current controller. The effect of the parameter b is more pronounced for faster current controllers.

5. Robustness and Performance Analysis

The sensitivity function S ( s ) is widely recognised as a key indicator for assessing both the robustness and performance of a control system, as it represents the transfer function between the references and the corresponding errors. In a single-input single-output system, the H -norm of S ( s ) is defined as the peak value of its frequency response. However, for multiple-input multiple-output systems, where S ( s ) is a transfer function matrix, the H -norm is defined in terms of its singular values. Specifically, the H -norm is given by
S = sup ω σ ¯ S ( j ω ) ,
where σ ¯ ( · ) denotes the maximum singular value. This definition captures the worst-case gain over all input directions. In this sense, higher values of the H -norm indicate that the closed-loop system amplifies disturbances and uncertainties to a greater extent, which implies reduced robustness. Conversely, lower values suggest that the system is less sensitive to perturbations, thereby exhibiting enhanced robustness. A typical specification for robust performance is to constrain the sensitivity peak to a value around 2 [31], which helps to prevent excessive noise amplification at high frequencies while ensuring a quantifiable margin of robustness.
In the system under study, S ( s ) is defined as the function that has the active and reactive power references as inputs and the corresponding power-tracking errors as outputs. The power-tracking errors e P and e Q for both active and reactive powers are computed as
e P = P * 3 V c d + R f I 1 d I 2 d I 1 d + V c q + R f I 1 q I 2 q I 1 q e Q = Q * 3 V c q + R f I 1 q I 2 q I 1 d V c d + R f I 1 d I 2 d I 1 q
As can be observed, Equation (34) shows non-linear expressions since some variables appear to be multiplied. Therefore, by linearising these equations, it is obtained that
Δ e P = Δ P * 6 R f I 1 d 0 3 R f I 2 d 0 + 3 V c d 0 Δ I 1 d + 3 R f I 1 d 0 Δ I 2 d 3 I 1 d 0 Δ V c d 6 R f I 1 q 0 3 R f I 2 q 0 + 3 V c q 0 Δ I 1 q + 3 R f I 1 q 0 Δ I 2 q 3 I 1 q 0 Δ V c q Δ e Q = Δ Q * 3 R f I 2 q 0 + 3 V c q 0 Δ I 1 d 3 R f I 1 q 0 Δ I 2 d + 3 I 1 q 0 Δ V c d 3 R f I 2 d 0 3 V c q 0 Δ I 1 q + 3 R f I 1 d 0 Δ I 2 q 3 I 1 d 0 Δ V c q
Note that linearisation restricts the validity of the model to small deviations around the chosen operating point. This is standard practice in small-signal analyses, where the focus is on local stability rather than on large excursions or varying conditions. Here, the case of P = ± 1 pu is examined (covering both inverter and rectifier operation) because higher power levels (in absolute value) generally translate into lower SCRs, representing a worst-case scenario for stability.
Then, the state-space model that defines the system under study and has the active and reactive power references u as inputs and the power-tracking errors y as outputs is
x ˙ = A x + B u y = C x + D u
where matrices A and B are those defined in (30) and (31), and matrices C and D are
C = 6 R f I 1 d 0 + 3 R f I 2 d 0 3 V c d 0 6 R f I 1 q 0 + 3 R f I 2 q 0 3 V c q 0 0 0 0 0 3 R f I 1 d 0 3 R f I 1 q 0 3 I 1 d 0 3 I 1 q 0 3 R f I 2 q 0 3 V c q 0 3 R f I 2 d 0 + 3 V c q 0 0 0 0 0 3 R f I 1 q 0 3 R f I 1 d 0 3 I 1 q 0 3 I 1 d 0
D = 1 0 0 1
Hence, the sensitivity transfer function matrix S ( s ) is
S ( s ) = C s I A 1 B + D
and the peak of the maximum singular values of S ( j ω ) can be computed.
Regarding the performance analysis, it is conducted based on the system’s settling time at 98%. Given the system state-space representation defined by matrices A, B, C, and D, the settling time is estimated through the analysis of the eigenvalues of the state matrix A. Specifically, the dominant mode of the system is determined by the eigenvalue λ dom with the smallest absolute real part. Thus, the associated settling time at 98% can be approximated by
t s 98 4 Re ( λ dom )
This estimation of the settling time is derived from the decay ratio associated with the dominant eigenvalue’s real part. It does not explicitly account for the damping factor, yet provides a practical measure of the dominant system behaviour and is considered sufficient for illustrative purposes.
To clearly illustrate how the parameters of the current controller and PLL affect both robustness and performance, several contour plots (from Figure 16, Figure 17, Figure 18 and Figure 19) are presented below. Robustness refers to the H -norm defined in (33), while performance is assessed through t s 98 defined in (40). The PLL parameters have been taken into account by using the natural frequency ω n p (in Hz), represented on the vertical axes, and the current controller parameters by using ω c c (in Hz), represented on the horizontal axes. ω c c is defined as ω c c = ξ c c ω n c , where ξ c c is the damping factor (for all simulations in this work, a damping factor of ξ c c = 0.93 has been employed) and ω n c is the natural frequency (as can be derived from (4), ξ c c ω n c in Hz is ξ c c ω n c = k p c + R 1 4 π L 1 ) of the closed-loop current control loop (see Section 2). All contour plots have been obtained by performing a parameter sweep of ω n p and ω c c with a sufficiently fine step size for both inverter and rectifier operating modes. Specifically, Figure 16 and Figure 17 show the impact of varying SCR values while keeping the weighting factor b fixed at 1, and Figure 18 and Figure 19 maintain a constant SCR value and vary the weighting factor b, clearly demonstrating how the adjustment of b significantly enhances robustness and performance. Presenting the results in this manner provides a visual and intuitive understanding of how the different parameters affect robustness and performance, offering practical insights into controller design considerations.
Figure 16 shows the contour plots of the H norm values, which serve as the robustness metric, where for an acceptable performance, an H -norm around 2 at most is considered [31]. The plots are generated for a sweep of PLL natural frequencies ( ω n p ) and different closed-loop design frequencies of the current controller ( ω c c ), considering SCR values of 2.5, 5, and 10 for both inverter and rectifier modes. In both operation modes, the feasibility regions where the system remains stable reduce as the SCR decreases. In inverter mode, for a given current controller, faster PLLs tend to decrease robustness, eventually leading to instability beyond a certain limit. In contrast, in rectifier mode, faster PLLs slightly improve robustness (resulting in a lower H ), while faster current controllers tend to reduce robustness and may induce instability. These results indicate that the PLL is the critical design element in inverter mode, with a slower PLL being favourable, whereas the current controller is more critical in rectifier mode, with slower controllers being interesting.
In weak grids, the achieved settling time may differ from that used to design the current controller due to variations in the PCC voltage during changes in active and reactive power, as well as potential oscillations in the current response if insufficient damping is provided. Figure 17 presents the achieved settling time at 98% (as defined in (40)) for the same conditions as in Figure 16, with the settling time derived from the dominant pole of the closed-loop system. It is observed that, for both operating modes, as the SCR decreases, the settling time increases and deviates further from the closed-loop time employed in the current controller design. In inverter mode, for a given current controller, an optimal PLL frequency exists that minimises the settling time, i.e., faster PLLs (or slower) lead to a slower system response. For instance, for SCR = 2.5, it can be observed that the PLL has a significant impact on the settling time. For a given ω c c , the fastest response is achieved with a PLL with a natural frequency around 15 Hz. If the PLL is faster or slower, the settling time of the current controller increases considerably. It is also observed that for a given PLL, faster controllers lead to smaller settling times; however, the speed of the response is much more influenced by the PLL design than the current controller parameters. Similarly, in rectifier mode, for a given PLL frequency, an optimal current controller minimises the achieved settling time and for a given controller, faster PLLs lead to smaller settling times and also improved robustness, with faster PLLs being favourable. However, in this case, the impact of the current controller is much more pronounced than that of the PLL.
For an SCR of 2.5 and a sweep of different values of the weighting parameter b (0, 0.25, 0.5, 0.75, and 1), the contour plots for the H -norm (Figure 18) and the settling times (Figure 19) are presented for both inverter and rectifier modes. In inverter mode, reducing b generally results in lower H -norm values. However, the size of the feasible (stable) regions also decreases as b is reduced. As noted previously, in inverter mode, the PLL is the most critical component, so for a given current controller, the minimum PLL frequency that triggers instability decreases slightly with a reduction in b. In this sense, adjusting b mainly affects performance (e.g., the oscillatory behaviour) rather than stability. For rectifier mode, the parameter b yields considerably greater improvements in stability. As b decreases, the feasible region expands and improved robustness is observed through lower H -norm values. Regarding the achieved settling times, in addition to the conclusions drawn from Figure 17, it is observed that as b decreases, the settling times increase, indicating a slower overall system response that diverges further from the design values.
Figure 20 illustrates the time-domain responses in inverter and rectifier modes when the reference power changes from 0.95 pu to 1 pu (inverter) and from −0.95 pu to −1 pu (rectifier), considering an SCR of 2.5. The responses of four different controllers, as detailed in Table 5, are compared. Note that the same ω c c is used for all the controllers (25.5 Hz), which corresponds to a settling time of approximately 25 ms for the design of the current control loop. Therefore, in inverter mode, controllers with a slow PLL (C1 and C3) remain stable, with the weighting parameter b affecting only performance, as indicated by differences in oscillatory behaviour and settling times. In contrast, controllers with a fast PLL (C2 and C4) fall outside the feasible region, resulting in unstable system behaviour that cannot be corrected by adjusting b. For rectifier mode, controllers with a lower b value (C1 and C2) lead to a stable system response, with the PLL primarily influencing performance (with faster PLLs being more favourable). Controllers with b = 1 (C3 and C4) fall outside the feasible region, leading to instability.

6. Conclusions

Numerous papers have studied the stability of VSCs connected to weak grids when operating as inverters. However, their stability when working as rectifiers has received little attention. This paper analyses the different impacts of the PLL and current controller parameters depending on the converter’s operation mode. The main findings are summarised as follows:
  • During inverter operation, a low PLL bandwidth improves the system stability, enabling the connection of VSCs to weaker grids. Conversely, during rectifier operation, a high PLL bandwidth enhances the system stability.
  • The settling time of the inner current control loops has a minor impact on the stability during inverter operation, with faster current controls only marginally increasing the stability. Conversely, faster current control loops significantly reduce the stability margins during rectifier operation, potentially leading to system instability.
  • The reference weighting factor b of the 2DOF-PI used in the current loops has a minor impact on the stability during inverter operation, with smaller values of b worsening the stability. On the contrary, lower values of b improve the system stability during rectifier operation, with b having a significant impact.
  • During rectifier operation, although a lower value of the parameter b reduces the stability limits, it enhances system performance for typical PLL and current controller design parameters by increasing the damping, consequently reducing oscillations.
The impacts of the PLL bandwidth, the settling time of the current control loops, and the reference weighting factor b have opposing effects on VSC stability when operating as a rectifier or inverter, results that have been validated through the root locus of the eigenvalues, the H -norm of the sensitivity function and EMT-PSCAD simulations. Therefore, with the increasing number of VSCs working as rectifiers (e.g., HVDC links, energy storage systems, converter-interfaced loads), the typical design recommendations used for the inverter operation may not be valid for rectifier operation.

Author Contributions

Conceptualisation, R.V.-A., C.D.-S. and I.P.-A.; methodology, R.V.-A. and C.D.-S.; software, J.J.T.B.; validation, R.V.-A., J.J.T.B. and C.D.-S.; formal analysis, R.V.-A., C.D.-S. and I.P.-A.; investigation, R.V.-A., J.J.T.B., C.D.-S. and I.P.-A.; writing, R.V.-A., J.J.T.B. and C.D.-S.; supervision, R.V.-A. and I.P.-A. All authors have read and agreed to the published version of the manuscript.

Funding

The authors would like to acknowledge the support of the Spanish Research Agency through grant PID2020-112943RBI00 funded by MCIN/AEI/10.13039/501100011033; grant PID2021-125634OB-I00 funded by MCIN/AEI/10.13039/501100011033 and ERDF a way of making Europe; and grants TED2021-130120BB-C21 and TED2021-130120B-C22 funded by MCIN/AEI/10.13039/501100011033 and by the European Union NextGenerationEU/PRTR.

Data Availability Statement

The data are included in the article. Additional data are available from the corresponding author upon request.

Conflicts of Interest

The authors declare no conflicts of interest.

Abbreviations

The following abbreviations are used in this manuscript:
2DOF-PITwo-Degree-of-Freedom Proportional Integral
GFLGrid Following
GFMGrid Forming
PIProportional Integral
PCCPoint of common coupling
PLLPhase-Locked Loop
SCRShort circuit ratio
VCCVector current control
VSCVoltage Source Converter

Appendix A

The results presented in Section 4 are obtained using an averaged ideal model of the VSC. To study the impact of delays, measurement filters, dead times and grid harmonics, a detailed model of a two-level converter has been developed. The switching frequency is 2500 Hz and the dead time is 7 μ s. The harmonic content of the grid voltage is 3rd harmonic (1%), 5th harmonic (2%), 7th harmonic (2%) and 15th harmonic (0.1%) according to real measurements in medium-voltage grids conducted by E.ON Distribution in the Czech Republic [32].
Figure A1 shows the results for a change in active power when the VSC works as an inverter. The SCR is 2 as in Section 4.1.1. Initially, the active and reactive powers are zero. From t = 0.1 s to t = 0.2 s, the power ramps up from 0 to 0.95 pu, and at t = 0.6 s, the power increases to 1 pu. Figure A1a and Figure A1b present the results for two designs of the PLLs with natural frequencies of 18 Hz and 23 Hz, respectively. The proportional and integral gains of the current controllers are those presented in Table 2. From top to bottom, both figures display the following variables: active power, grid-side current and grid voltage. As it is observed, a higher PLL natural frequency worsens the stability of the system. The system with a PLL with a lower natural frequency (Figure A1a) remains stable, whereas the other (Figure A1b) becomes unstable.
The same simulation has been repeated for the rectifier operation (Figure A2). The SCR is 3 as in Section 4.1.2. The changes in the active power are the same; however, the active power is now negative. The natural frequency of the PLL is 20 Hz (Figure A2a) and 30 Hz (Figure A2b). As observed, a higher PLL natural frequency enhances the stability of the system. Therefore, although the exact value of the SCR at which the VSC becomes unstable varies slightly with respect to the small-signal model, the conclusions drawn from the ideal model remain valid. A faster PLL worsens stability during the inverter operation while it improves the stability during the rectifier operation.
Figure A1. Influence of the PLL natural frequency on the VSC stability when operating as an inverter. Left figure: ω n p = 18 Hz; right figure: ω n p = 23 Hz. From top to bottom: active power, grid-side current and grid voltage.
Figure A1. Influence of the PLL natural frequency on the VSC stability when operating as an inverter. Left figure: ω n p = 18 Hz; right figure: ω n p = 23 Hz. From top to bottom: active power, grid-side current and grid voltage.
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Figure A2. Influence of the PLL natural frequency on the VSC stability when operating as a rectifier. Left figure (a) ω n p = 20 Hz ; right figure (b) ω n p = 30 Hz . From top to bottom: active power, grid-side current and grid voltage.
Figure A2. Influence of the PLL natural frequency on the VSC stability when operating as a rectifier. Left figure (a) ω n p = 20 Hz ; right figure (b) ω n p = 30 Hz . From top to bottom: active power, grid-side current and grid voltage.
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Figure 1. Grid-following VSC model.
Figure 1. Grid-following VSC model.
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Figure 2. Scheme of the SRF-PLL.
Figure 2. Scheme of the SRF-PLL.
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Figure 3. Current control loop with 2DOF-PI.
Figure 3. Current control loop with 2DOF-PI.
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Figure 4. Angle change of the grid voltage within the SRF-PLL.
Figure 4. Angle change of the grid voltage within the SRF-PLL.
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Figure 5. Comparison of the small-signal and PSCAD results for a step change in P of 0.02 pu. From top to bottom: (a) d- and q-axis components of the converter current, (b) d- and q-axis components of the grid current, (c) d- and q-axis components of the PCC voltage, (d) PLL angle obtained from the integrator after the PLL-PI controller (see Figure 2), (e) active and reactive power at the PCC point.
Figure 5. Comparison of the small-signal and PSCAD results for a step change in P of 0.02 pu. From top to bottom: (a) d- and q-axis components of the converter current, (b) d- and q-axis components of the grid current, (c) d- and q-axis components of the PCC voltage, (d) PLL angle obtained from the integrator after the PLL-PI controller (see Figure 2), (e) active and reactive power at the PCC point.
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Figure 6. Root locus for five PLL natural frequencies in inverter operation ( P = 1 pu, Q = 0 pu and S C R = 2 ).
Figure 6. Root locus for five PLL natural frequencies in inverter operation ( P = 1 pu, Q = 0 pu and S C R = 2 ).
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Figure 7. Zoom-in of the root locus of Figure 6.
Figure 7. Zoom-in of the root locus of Figure 6.
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Figure 8. PSCAD results for inverter mode (P > 0) with two PLL natural frequencies.
Figure 8. PSCAD results for inverter mode (P > 0) with two PLL natural frequencies.
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Figure 9. Root locus for five PLL natural frequencies in rectifier operation ( P = 1 pu , Q = 0 pu and S C R = 3 ).
Figure 9. Root locus for five PLL natural frequencies in rectifier operation ( P = 1 pu , Q = 0 pu and S C R = 3 ).
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Figure 10. Zoom-in of the root locus of Figure 9.
Figure 10. Zoom-in of the root locus of Figure 9.
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Figure 11. PSCAD results for rectifier mode (P < 0) with two PLL natural frequencies.
Figure 11. PSCAD results for rectifier mode (P < 0) with two PLL natural frequencies.
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Figure 12. Maximum PLL natural frequency as a function of the grid SCR and the current PI settling time in inverter operation (P = 1 pu, Q = 0 pu).
Figure 12. Maximum PLL natural frequency as a function of the grid SCR and the current PI settling time in inverter operation (P = 1 pu, Q = 0 pu).
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Figure 13. Minimum PLL natural frequency as a function of the grid SCR and the current PI settling time in rectifier operation (P = −1 pu, Q = 0 pu).
Figure 13. Minimum PLL natural frequency as a function of the grid SCR and the current PI settling time in rectifier operation (P = −1 pu, Q = 0 pu).
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Figure 14. Influence of the weighting factor b on the minimum SCR for 4 settling times of the current controllers. Inverter mode (P = 1 pu, Q = 0 pu).
Figure 14. Influence of the weighting factor b on the minimum SCR for 4 settling times of the current controllers. Inverter mode (P = 1 pu, Q = 0 pu).
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Figure 15. Influence of the weighting factor b on the minimum SCR for 4 settling times of the current controllers. Rectifier mode (P = −1 pu, Q = 0 pu).
Figure 15. Influence of the weighting factor b on the minimum SCR for 4 settling times of the current controllers. Rectifier mode (P = −1 pu, Q = 0 pu).
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Figure 16. H -norm for inverter (top) and rectifier (bottom) operation for different values of SCR and the weighting factor b = 1 .
Figure 16. H -norm for inverter (top) and rectifier (bottom) operation for different values of SCR and the weighting factor b = 1 .
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Figure 17. Achieved settling times at 98% (in ms) for inverter (top) and rectifier (bottom) operation for different values of SCR and the weighting factor b = 1 .
Figure 17. Achieved settling times at 98% (in ms) for inverter (top) and rectifier (bottom) operation for different values of SCR and the weighting factor b = 1 .
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Figure 18. H -norm for inverter (top) and rectifier (bottom) operation for different values of the weighting factor b and SCR = 2.5.
Figure 18. H -norm for inverter (top) and rectifier (bottom) operation for different values of the weighting factor b and SCR = 2.5.
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Figure 19. Achieved settling times at 98% (in ms) for inverter (top) and rectifier (bottom) operation for different values of the weighting factor b and SCR = 2.5.
Figure 19. Achieved settling times at 98% (in ms) for inverter (top) and rectifier (bottom) operation for different values of the weighting factor b and SCR = 2.5.
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Figure 20. Step response of four controllers (C1 to C4) to a power reference change in inverter and rectifier modes considering SCR = 2.5.
Figure 20. Step response of four controllers (C1 to C4) to a power reference change in inverter and rectifier modes considering SCR = 2.5.
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Table 1. System parameters.
Table 1. System parameters.
DescriptionParameterValue
Transformer leakage inductance L T 112.7 mH
Transformer copper resistance R T 1.416  Ω
Filter capacitance C f 0.623  μ F
Damping resistance of the filter R f 104.1  Ω
Filter inductance L 1 150.7 mH
Filter copper resistance R 1 1.890   Ω
Line-to-ground grid voltage V g 38.11 kV
Converter rated active powerP8 MW
Grid angular frequency ω g 2 π 50 rad/s
Table 2. System parameters for the small-signal model validation.
Table 2. System parameters for the small-signal model validation.
DescriptionParameterValue
Grid SCR S C R 4
Grid X g / R g ratio X g / R g 10
Proportional gain of the current PI controllers k p c 57 V/A
Integral gain of the current PI controllers k i c 7100 V/As
Reference weighting factor for the current PI controllersb 0.75
Proportional gain of the PLL PI controller k p p 125 rad/s
Integral gain of the PLL PI controller k i c 4000 rad/s2
Table 3. Current, voltage and angle values at the operating point where the system is linearised.
Table 3. Current, voltage and angle values at the operating point where the system is linearised.
Variable I 1 d 0 (A) I 1 q 0 (A) I 2 d 0 (A) I 2 q 0 (A) V c p d 0 (kV) θ 0 (rad)
Value47.467−15.45747.299−24.06642.1170.204
Table 4. Parameters of the current controller used in Figure 12 and Figure 13.
Table 4. Parameters of the current controller used in Figure 12 and Figure 13.
Settling Time (ms) k pc k ic b
5239.21.12 × 10 5 0.75
10118.72.78 × 10 4 0.75
1578.51.24 × 10 4 0.75
2058.46.97 × 10 3 0.75
2046.34.46 × 10 3 0.75
3038.33.10 × 10 3 0.75
Table 5. Comparison of controllers.
Table 5. Comparison of controllers.
Controller ω np (Hz) ω cc (Hz)b
C11025.50.25
C24025.50.25
C31025.51
C44025.51
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MDPI and ACS Style

Vidal-Albalate, R.; Tejedor Bomboi, J.J.; Díaz-Sanahuja, C.; Peñarrocha-Alós, I. Two-Degree-of-Freedom Proportional Integral Controllers for Stability Enhancement of Power Electronic Converters in Weak Grids: Inverter and Rectifier Operating Modes. Electronics 2025, 14, 1565. https://doi.org/10.3390/electronics14081565

AMA Style

Vidal-Albalate R, Tejedor Bomboi JJ, Díaz-Sanahuja C, Peñarrocha-Alós I. Two-Degree-of-Freedom Proportional Integral Controllers for Stability Enhancement of Power Electronic Converters in Weak Grids: Inverter and Rectifier Operating Modes. Electronics. 2025; 14(8):1565. https://doi.org/10.3390/electronics14081565

Chicago/Turabian Style

Vidal-Albalate, Ricardo, José Jesús Tejedor Bomboi, Carlos Díaz-Sanahuja, and Ignacio Peñarrocha-Alós. 2025. "Two-Degree-of-Freedom Proportional Integral Controllers for Stability Enhancement of Power Electronic Converters in Weak Grids: Inverter and Rectifier Operating Modes" Electronics 14, no. 8: 1565. https://doi.org/10.3390/electronics14081565

APA Style

Vidal-Albalate, R., Tejedor Bomboi, J. J., Díaz-Sanahuja, C., & Peñarrocha-Alós, I. (2025). Two-Degree-of-Freedom Proportional Integral Controllers for Stability Enhancement of Power Electronic Converters in Weak Grids: Inverter and Rectifier Operating Modes. Electronics, 14(8), 1565. https://doi.org/10.3390/electronics14081565

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