A Low-Complexity Hybrid Phase Shifter Network with Shared-Control Voltage for High-Scan-Gain Phased Arrays

Abstract

This article presents a low-complexity hybrid phase shifter network (PSN) with a shared-control voltage architecture for high-gain phased arrays. The proposed system integrates a 1-bit reconfigurable antenna and a voltage-controlled phase shifter in each channel, achieving continuous 360° phase tuning with low insertion loss (below−1.2 dB) and small amplitude fluctuation (±0.2 dB). A single analog control voltage, distributed through reconfigurable passive resistor dividers, replaces per-channel bias sources, significantly reducing hardware complexity. A genetic algorithm is employed to optimize division ratio vectors for beam steering across a wide angular range while enhancing main-lobe gain. Simulation and experimental results show that compared with a conventional 1-bit PSN, the proposed architecture achieved up to 3.6 dB main-lobe gain enhancement while requiring only two additional control lines. This design offers an effective trade-off between performance and implementation cost for large-scale phased array systems.

1. Introduction

Phased arrays enable beamforming and rapid beam scanning through precise control of the signal phase radiated by each array element [1]. Due to these capabilities, they have been widely used in wireless communications [2], radar systems [3], and wireless power transfer [4]. In such systems, key performance indicators such as scanning gain and sidelobe level (SLL) largely depend on the architecture and implementation of the phase shifter network (PSN) [5]. Depending on where phase control is implemented within the signal chain, PSNs can be categorized into local oscillator (LO), intermediate frequency (IF), and radio frequency (RF) phase shifter networks [6].

In the LO PSN, phase control is applied in the LO path and transferred to the RF signal through mixing, thereby enabling beam steering [7,8,9]. A self-adaptive beam-scanning architecture based on a DDS-PLL structure and angle-of-arrival (AoA) estimation was reported in [10], where the phase adjustment was performed in the local oscillator (LO) path to enable real-time beam control. The IF PSN performs phase adjustment at a lower intermediate frequency before upconverting the signal to RF [11,12]. The relatively low IF frequency simplifies the implementation of phase control [13]. In contrast, the RF PSN directly applies phase control to the RF signal path without requiring an additional LO distribution network [14]. This architecture is compact and low-cost, making it especially suitable for large-scale phased array systems. Consequently, it is the most widely adopted in practice [15,16].

Among various RF phase shifters, electronic phase shifters controlled by electrical signals are the most widely used due to their compact size, low cost, and high integration capability [6]. Based on their operating mechanisms, electronic phase shifters can be classified into switched-type or reflective-type [17,18]. A switched-type phase shifter typically realizes quantized phase shifts through switched delay lines of discrete electrical lengths [19] or switched filter networks consisting of high-pass and low-pass branches [20]. However, achieving finer phase resolution (i.e., more bits) requires additional delay or filter branches and switches. Consequently, the number of control lines increases with bit resolution, leading to higher control circuit complexity [21]. A reflective-type phase shifter achieves continuous phase tuning by controlling the impedance of reflective loads using analog voltages [22]. Nevertheless, conventional single-voltage-controlled reflective structures exhibit a trade-off between phase tuning range and insertion-loss flatness [23]. Fluctuations in insertion loss across phase states lead to amplitude mismatches among array elements, thereby degrading beam-scanning performance [24]. Therefore, achieving a wide continuous phase tuning range while maintaining low insertion loss and amplitude consistency remains a key challenge in RF phase shifter design.

To address this issue, several improved reflective-type topologies based on C–L–C π-type networks have been reported [25,26], which enhance amplitude flatness and extend the phase tuning range. However, these designs typically require multiple independent bias voltages, increasing hardware complexity. Recently, hybrid phase shifters, which combine discrete coarse tuning with continuous fine tuning, have attracted considerable attention. By leveraging the cooperation between discrete and continuous phase-shift units, hybrid shifters can achieve wide phase coverage and stable insertion-loss characteristics [27,28,29]. Nonetheless, when implemented in large-scale phased arrays, these architectures still require multiple independent bias voltages, resulting in complex control networks and limited scalability.

To overcome these limitations, this work proposes a low-complexity RF hybrid phase shifter network architecture with shared control voltage. Each channel integrates a 1-bit reconfigurable antenna and a cascaded voltage-controlled phase shifter, enabling full 360° phase control with insertion loss below −1.2 dB and insertion-loss fluctuation within ±0.2 dB. Compared with switched-type and reflective-type phase shifters, the proposed design exhibits low insertion loss and minimal amplitude fluctuation. Furthermore, a reconfigurable passive resistive voltage-divider network is introduced to provide a unified reference bias voltage for the entire array, reducing the number of control lines from 2N in conventional designs to N + 2. Unlike conventional hybrid phase shifters, this approach eliminates the need for independent voltage sources for each channel. An eight-element prototype array based on the proposed method was fabricated and experimentally verified at 915 MHz. Compared with a traditional 1-bit array, the proposed architecture improves scanning gain by up to 3.6 dB and effectively suppresses sidelobes, while requiring only two additional control lines. This work introduces a new design concept for developing low-complexity, high scanning gain phased array systems, which can be widely applied in wireless power transfer and related fields.

The remainder of this paper is organized as follows. Section 2 introduces the proposed RF hybrid architecture and shared-bias control circuit. Section 3 presents the performance analysis and GA-based optimization. Section 4 describes the reconfigurable 1-bit element design, Section 5 discusses the measurement results, and Section 6 concludes the paper.

2. Design and Implementation of a Hybrid PSN with Shared-Control Voltage

2.1. System Overview

Figure 1 shows the block diagram of the proposed 1 × N linear phased array, which is designed to balance beamforming performance and the control complexity of the PSN. The array comprises N uniformly spaced elements with a half-wavelength (${\lambda }_0/2$.) inter-element spacing. Each channel integrates a 1-bit reconfigurable antenna, cascaded with a voltage-controlled phase shifter that is driven by a shared control voltage distributed through passive resistor dividers. This shared-voltage scheme eliminates the need for independent biasing circuits in each channel, thereby significantly reducing control complexity. The hybrid configuration combines the advantages of discrete and continuous phase shifters, enabling continuous 0–360° phase control while achieving a maximum insertion loss of −1 dB and an insertion loss fluctuation within ±0.2 dB.

Table 1. Comparison of representative commercial phase shifters operating at 915 MHz.

Chip Model	Type	Number of Control Lines	Maximum Insertion Loss	Insertion Loss Fluctuation
HMC936	Dig.	6	−5 dB	±1 dB
SPHSA-152	Ana.	1	−3.8 dB	±1 dB
hybrid configuration	hybrid	2	−1.2 dB	±0.2 dB

compares the performance of the proposed hybrid architecture with two representative commercial phase shifters. The HMC936 is a digital phase shifter that provides full 360° tuning but requires 6 control lines, with a maximum insertion loss of −5 dB and an insertion loss fluctuation of ±1 dB. The SPHSA-152 is an analog phase shifter that uses only one control line but exhibits a maximum insertion loss of −3.8 dB and an insertion-loss fluctuation of ±1 dB. In contrast, the hybrid architecture uses only two control lines, significantly simplifying the control circuitry while maintaining a lower maximum insertion loss of −1.2 dB and a smaller fluctuation of ±0.2 dB, which is beneficial for beamforming and sidelobe suppression in array applications.

To further reduce the hardware complexity of the proposed hybrid phase shifter architecture, all analog phase shifters are driven by a shared control voltage, $V_{ref}$. In each channel, the local control voltage, $V_n$, is generated through a passive resistor divider network consisting of $R_{1,n}$ and $R_{2,n}$, expressed as:

$$V_n=k_n{V}_{ref}$$

(1)

where

$$k_n={\displaystyle \frac{R_{2,n}}{R_{1,n}+R_{2,n}}}$$

(2)

By selecting an appropriate value for $V_{ref}$, the phase distribution across the array is tailored to approximate the ideal phase profile required for beam steering. This shared control voltage approach eliminates the need for independent control voltages for each channel, effectively simplifying the control circuitry.

2.2. System Performance Analysis

Accurate phase control is critical for optimal beamforming performance in phased array systems. In the proposed design, a shared control voltage $V_{ref}$ and passive resistor dividers are used to simplify the control circuitry. However, this approach introduces phase approximation errors across channels, which may degrade beam steering accuracy.

To quantitatively evaluate the impact of phase errors, the ideal excitation phase ${Ø}_{id,n}$ required at the n-th element for beam steering towards a target angle ${Ø}_0$ is given by [30]:

$${Ø}_{id,n}=-k_0·d·\sin {\theta }_0·\left(n-1\right), n=1,2,\cdots ,N$$

(3)

where $k_0=2\pi /{\lambda }_0$ represents the wavenumber in free space, and d is the inter-element spacing.

In the proposed design, the actual excitation phase ${Ø}_{rea,n}$ at the n-th array element is determined jointly by the discrete and continuous phase shifters. The voltage-controlled phase shifter ${Ø}_{ana,n}$ is continuously tunable and depends on the division ratio $k_n$ and the shared control voltage $V_{ref}$. The 1-bit reconfigurable antenna introduces a discrete phase ${Ø}_{dig,n}ϵ\left\{0,\pi \right\}$, which is selected based on the phase discrepancy between the ideal phase and ${Ø}_{ana,n}$, according to:

$${Ø}_{dig,n}=\left\{\begin{array}{c}0, {\displaystyle \frac{\pi }{2}}\le {Ø}_{id,n}-{Ø}_{ana,n}\le {\displaystyle \frac{3\pi }{2}}\\ \pi ,-{\displaystyle \frac{\pi }{2}}<{Ø}_{id,n}-{Ø}_{ana,n}<{\displaystyle \frac{\pi }{2}}\end{array}\right..$$

(4)

The actual excitation phase ${Ø}_{rea,n}$ is then given by:

$${Ø}_{rea,n}={Ø}_{ana,n}+{Ø}_{dig,n}$$

(5)

To assess the impact of phase errors on array performance, we introduce the Phase Accuracy Efficiency (PAE) metric, defined as:

$${\eta }_{PAE}\left({\theta }_0\right)={\displaystyle \frac{{\left|{\sum }_{n=1}^N{e}^{j·\left({Ø}_{rea,n}\left({\theta }_0\right)-{Ø}_{id,n}\left({\theta }_0\right)\right)}\right|}^2}{{\left|{\sum }_{n=1}^N{e}^{j·\left({Ø}_{id,n}\left({\theta }_0\right)-{Ø}_{id,n}\left({\theta }_0\right)\right)}\right|}^2}}$$

(6)

A PAE value close to unity indicates that the main-lobe gain of the proposed system closely approximates that of an ideal phased array with continuous phase control, thereby confirming its beamforming accuracy.

In addition to main beam gain, side-lobe level (SLL) is a critical metric for evaluating the overall quality of the array radiation pattern. Poor sidelobe suppression not only degrades beam directivity but may also cause electromagnetic interference to adjacent systems or unintended receivers. The SLL, expressed in decibels (dB), is defined as:

$$SLL=20 {\log }_{10}\left({\displaystyle \frac{Max main-lobe level}{Max side-lobe level}}\right)$$

(7)

2.3. Design of the Hybrid PSN with a Shared-Control Voltage Scheme

In the proposed phased array, the voltage-controlled phase shifter for the n-th channel is expressed as:

$${Ø}_{ana,n}=f\left(v_n\right)=f\left({\displaystyle \frac{R_{2,n}}{R_{1,n}+R_{2,n}}}{V}_{ref}\right)=f\left(k_n{V}_{ref}\right)$$

(8)

where $f\left(·\right)$ represents the nonlinear mapping between the control voltage and the phase shift, as defined by the voltage-controlled phase shifter’s characteristic.

To enhance beam steering range and phase control resolution, a digital switching mechanism is introduced, as shown in Figure 2. Specifically, each fixed resistor is replaced with a bank of selectable resistors controlled by Single-Pole-n-Throw (SPnT) switches. All SPnT switches are driven through shared digital control lines, enabling synchronous switching across all channels. In the basic configuration, the division-ratio vector $k=\left[k_1,k_2,\cdots k_N\right]$ remains fixed. However, with the shared digital control lines, multiple division-ratio vectors $k^{\left(g\right)}=\left[k_1^{\left(g\right)},k_2^{\left(g\right)},\cdots ,k_N^{\left(g\right)}\right]$ can be selected, where $g\in \left\{1,2,\cdots ,G\right\}$ represents different configuration states.

The design objective is to determine the optimal set of division ratios ${\left\{k^{\left(g\right)}\right\}}_{g=1}^G$ that maximizes the sum of ${\eta }_{PAE}$ across a specified set of beam steering angles while ensuring that the SLL remains below a predefined threshold ${SLL}_{target}$. The optimization problem is formulated as:

$$\begin{gathered} Objective=\underset{{\left\{k^g\right\}}_{g=1}^G}{\max }\sum _{\theta ϵ\mathsf{\Theta }}\underset{\mathit{gϵ}\left\{1,\cdots ,G\right\}}{\max }{\eta }_{PAE}\left(\theta ,k^{\left(g\right)}\right) \\ subject to:SLL\left(\theta , k^{\left(g^{*}\right)}\right)\le {SLL}_{target} \\ {g}^{*}=arg\underset{g\in \left\{1,\cdots ,g\right\}}{\max }{\eta }_{PAE}\left(\theta ,k^{\left(g\right)}\right), \forall \theta ϵ\mathsf{\Theta } \end{gathered}$$

(9)

where $\mathsf{\Theta }=\{{\theta }_1,{\theta }_2,\cdots ,{\theta }_M\}$ denotes the set of target steering angles, and $G$ is the number of available division ratio vectors. For each steering angle ${\theta }_m$ the optimization process selects the configuration index $g^{*}$ that maximizes ${\eta }_{PAE}$ while satisfying the sidelobe constraint.

Because this problem is nonlinear and lacks a closed-form analytical solution, a genetic algorithm (GA) [31] is employed to obtain a near-optimal solution. The detailed GA optimization framework is presented in

Table 2. GA-based Optimization Framework.

Input: Steering angle set $\mathsf{\Theta }$ Target sidelobe level ${SLL}_{target}$; GA parameters: population size P, crossover probability $P_c$, mutation probability $P_m$, and maximum generation $G_{max}$ Performance threshold ${\eta }_{th}$ convergence threshold $\mathsf{\epsilon }$. Output: Optimized set of division ratio vectors ${\left\{k^g\right\}}_{g=1}^G$

Initialization: Set the division ratio vector count G = 1. Randomly initialize a population of size P for ${\mathrm{k}}^{\left(\mathrm{g}\right)}$. Optimization via GA: (1) For the current value of G, apply GA to optimize each ${\mathrm{k}}^{\left(\mathrm{g}\right)}$ (2) across all $\theta \in \mathsf{\Theta }$. (3) GA iteratively refines ${\mathrm{k}}^{\left(\mathrm{g}\right)}$ through selection, crossover, and mutation to maximize the sum of ${\eta }_{PAE}$ across all steering angles, subject to the constraint that the sidelobe level at each angle remains below ${\mathrm{S}\mathrm{L}\mathrm{L}}_{\mathrm{t}\mathrm{a}\mathrm{r}\mathrm{g}\mathrm{e}\mathrm{t}}$. (4) The GA terminates when the relative improvement of the fitness function between consecutive generations falls below the predefined convergence threshold $\epsilon$, indicating that the optimization has converged. Performance Evaluation: After GA convergence, calculate the total ${\eta }_{PAE}$ across all $\mathsf{\theta }\in \mathsf{\Theta }$ and verify that the sidelobe-level constraint is satisfied. If the achieved total ${\eta }_{PAE}$ is below the target performance threshold ${\mathrm{\eta }}_{\mathrm{t}\mathrm{h}}$, increment G to enlarge the configuration space and repeat Step 2. If the achieved total ${\eta }_{PAE}$ exceeds ${\mathrm{\eta }}_{\mathrm{t}\mathrm{h}}$, the optimization process terminates.

.

It is worth noting that the reconfigurable resistor divider network operates only in the low-frequency control path. Since no RF signal passes through this network, it introduces negligible power loss and does not affect the RF signal path. Unlike conventional hybrid phase shifters, this approach eliminates the need for independent voltage sources in each channel. Although several passive components are added for voltage division, the overall control complexity remains significantly lower than that of conventional per-channel biasing architectures.

3. Numerical Results and Performance Evaluation

To assess the effectiveness of the proposed shared-control hybrid PSN, a numerical simulation was performed on a linear phased array consisting of N = 8 elements with half-wavelength spacing using MATLAB R2023a.

Following the GA-based optimization process described in Section 2.3, two division ratio vectors (i.e., G = 2) were selected for implementation, denoted as $k^{\left(1\right)}$ and $k^{\left(2\right)}$. The detailed division ratio ${k_n}^{\left(g\right)}$ for each element $n=1,2,3,\cdots ,8$ and each configuration $g\in \left\{1,2\right\}$ are summarized in

Table 3. The division ratio vectors under $g=1,2$.

	${\mathit{k}}_1$	${\mathit{k}}_2$	${\mathit{k}}_3$	${\mathit{k}}_4$	${\mathit{k}}_5$	${\mathit{k}}_6$	${\mathit{k}}_7$	${\mathit{k}}_8$
$g=1$	0.047	0.146	0.877	0.428	0.420	0.950	0.178	0.867
$g=2$	0.495	0.973	0.679	0.339	0.481	0.948	0.667	0.323

. These values are used to generate the corresponding local control voltages $v_n=k_n^{\left(g\right)}{V}_{ref}$, which determine the analog phase responses of each channel. The simulation assumes an operating frequency of 915 MHz. The reference control voltage $V_{ref}$ was adjusted from 0 V to 15 V to cover the full phase-tuning range of the JSPHS-1000 phase shifter. This voltage range lies well within the device’s rated operating limit of 18 V. Since the control port of the JSPHS-1000 presents a high input impedance, the bias current is extremely small (<1 mA), and the resulting control-line power consumption is negligible. Therefore, the applied voltage range does not compromise the overall low-power characteristic of the proposed system. Beam steering is evaluated across a scan range from $-60°$ to $60°$, with a step size of $1°$.

Figure 3 illustrates the simulated ${\eta }_{PAE}$ of the 1-bit, 2-bit, and proposed hybrid PSN-based phased array as a function of the beam-steering angle. The 1-bit array shows a pronounced efficiency degradation at large steering angles, whereas the 2-bit array maintains high ${\eta }_{PAE}$ across most directions. The proposed design exhibits an efficiency profile closely comparable to that of the 2-bit array throughout the $\pm 60°$, sustaining stable performance even under wide-angle steering. The average ${\eta }_{PAE}$ values of the 1-bit, 2-bit, and proposed array were 51.8%, 86%, and 79.3%, respectively. Compared with the 1-bit array, the 2-bit and proposed arrays improved the average ${\eta }_{PAE}$ by 66% and 53%, respectively. The small difference in improvement demonstrates that the proposed array achieves near 2-bit efficiency while requiring substantially fewer control resources. When the steering angle approaches $0°$, the phase difference between adjacent elements becomes small, so quantization errors accumulate weakly across the array and have only a minor impact on ${\mathsf{\eta }}_{\mathrm{P}\mathrm{A}\mathrm{E}}$ However, as the beam is steered toward larger angles, the coarse quantization of the 1-bit array causes a significant efficiency degradation, whereas the proposed method maintains a high ${\mathsf{\eta }}_{\mathrm{P}\mathrm{A}\mathrm{E}}$ comparable to that of the 2-bit array.

Notably, the proposed architecture achieved this near 2-bit performance with only $\mathrm{N}+2$ control lines, compared with the 2N lines required by the conventional 2-bit array. This reduction greatly simplifies the biasing and routing networks. Consequently, the proposed shared-control scheme provides a practical and scalable solution that effectively balances high efficiency, low control complexity, and ease of implementation in large phased-array systems.

Figure 4 shows the simulated SLL versus beam-steering angle for the 1-bit, 2-bit, and proposed hybrid PSN-based phased arrays. The 1-bit array exhibited severe SLL degradation at large steering angles due to the periodic quantization errors of the phase shifters, which caused the sidelobes to rise to levels comparable to the main beam amplitude. In contrast, both the 2-bit and the proposed arrays maintained low sidelobes over the entire $\pm 60°$ scanning range. The average SLLs of the 2-bit and proposed arrays were −8.09 dB and −7.82 dB, respectively, which were substantially lower than that of the 1-bit array. The small difference of only 0.27 dB between the 2-bit and proposed arrays demonstrates that the proposed architecture achieves near−2-bit sidelobe suppression performance. Notably, the proposed design accomplishes this performance using only $N+2$ control lines, whereas a conventional 2-bit array requires 2N control lines. This reduction greatly simplifies the biasing and routing networks.

Overall, the proposed architecture maintains high ${\mathsf{\eta }}_{\mathrm{P}\mathrm{A}\mathrm{E}}$ as demonstrated in Figure 3) while effectively suppressing sidelobes, achieving an excellent trade-off among efficiency, control complexity, and implementation feasibility—making it well suited for large-scale, low-cost phased-array systems.

4. Element Design and Simulated Results

To realize low-cost and compact 1-bit phase control in phased arrays, this work adopted a reconfigurable antenna element that functions as a digitally controlled phase shifter. This antenna achieves a 180° phase shift through physical reconfiguration of the feed path. Specifically, by switching the excitation between two symmetric feed points, the surface current direction on the patch reverses, resulting in a spatial phase shift of 180°.

Figure 5 shows the detailed configuration of the proposed 1-bit antenna unit. The antenna comprises two printed circuit boards (PCBs): a radiation board and a feed board that incorporates a metallic ground plane. These two boards are separated by an air gap of height $\mathrm{h}$ which improves impedance matching and enhances radiation efficiency. The radiation board is fabricated from a 1 mm thick FR4 substrate and carries a rectangular patch that serves as the primary radiating element. The feed board is positioned beneath the radiation board and includes the ground plane together with a π-shaped feed network. This feed network consists of two symmetric feed probes that connect to the patch through vertical coaxial pins, two PIN diodes located at the junction of the feed lines, and a central grounding probe positioned between the feed probes. The grounding probe provides a direct current return path, ensuring electrical continuity and stabilizing the bias circuit. The feed network is connected to both the RF input port and the DC bias circuit. By applying different DC bias voltages, one of the PIN diodes is switched on while the other remains off, thereby selecting the active feed probe. When the excitation changes from Probe 1 to Probe 2, the surface current on the radiation patch reverses direction, resulting in an approximate 180° spatial phase shift. The detailed geometrical parameters of the antenna are summarized in

Table 4. Dimensions of the proposed 1-bit antenna unit (all dimensions are in millimeters).

$\mathit{w}$	$\mathit{L}$	${\mathit{w}}_1$	${\mathit{w}}_2$	${\mathit{L}}_1$	$\mathit{h}$
200	200	120	48	146	5

.

An equivalent schematic of the proposed 1-bit reconfigurable unit cell is presented in Figure 6 to illustrate the operating mechanism of the switching structure. The radiating patch is excited through two probes, denoted as Port 1 and Port 2, which are connected to the asymmetric microstrip feed network. A pair of PIN diodes is inserted between the two probe branches, forming a reconfigurable switching path that controls the dominant excitation port. When the diodes are biased in the ON state, the RF signal is primarily coupled to Port 1, whereas the OFF state shifts the excitation toward Port 2. The two biasing states result in opposite current distributions on the radiating patch, thereby generating the required 0° and 180° phase responses. A grounding probe is also included in the structure to provide a stable current-return path and maintain consistent switching behavior. The schematic highlights the essential RF paths and switching states of the unit cell and offers a simplified representation of the physical configuration shown in Figure 5.

In the simulation model, each PIN diode (BAR64-02V H6327) is represented by an equivalent circuit for the on and off states. When forward-biased, the diode is modeled as a series connection of a 1.8 Ω resistance and a 0.6 nH package inductance. When reverse-biased, it is modeled as a series combination of a 25 kΩ resistance, a 0.6 nH inductance, and a 0.35 pF junction capacitance. Considering that the forward conduction current of the PIN diode is approximately 20 mA, a 250 Ω current-limiting resistor is inserted in each DC bias line to prevent over-current damage and ensure stable biasing operation.

Figure 7a shows the simulated input reflection coefficients versus frequency for the two switching states. Due to the structural symmetry of the proposed antenna element, both states exhibited nearly identical impedance characteristics, with a common impedance bandwidth of 0.901–0.921 GHz, confirming stable impedance matching regardless of the switching state. Figure 7b illustrates that the phase difference between the two states remained approximately 180° within the impedance bandwidth.

Figure 8a,b shows the simulated co-polarized far-field radiation patterns of the proposed 1-bit antenna unit under the two operating states. The co-polarization gains of both states were nearly identical, with a maximum gain of 6.25 dBi and a half-power beamwidth of approximately $\pm 38°$. Moreover, the phase transition between the two states introduced negligible amplitude fluctuation, indicating low insertion-loss fluctuation and stable radiation behavior during state switching.

5. Experimental Validation

Based on the reconfigurable antenna unit described above, a proposed 8-element phased-array prototype integrating the proposed low-complexity hybrid PSN was fabricated and experimentally characterized. A 1-to-8 power divider was employed to provide equal-amplitude and in-phase microwave signals to each antenna element, with an inter-element spacing of half a wavelength. The far-field measurement was conducted inside a microwave anechoic chamber using the setup shown in Figure 9. The measurement configuration included the 8-element phased array under test, a measurement probe antenna, RF cables for signal transmission, and a network cable for control communication. Each antenna element’s PIN diode was biased between ±5 V to realize the 0° and 180° digital phase states, forming the digital control part. The proposed hybrid PSN adopted a shared control structure consisting of one global analog voltage line and one digital switching line, resulting in a total of only ten control lines for the entire array.

Due to the non-isotropic radiation patterns of the antenna elements, direction-dependent variations arise in the array response. To mitigate this effect and enhance beamforming accuracy, the design of the division ratio vectors in the hybrid PSN was informed by the measured element patterns.

Table 5. The division ratio vectors under $g=1,2$.

	${\mathit{k}}_1$	${\mathit{k}}_2$	${\mathit{k}}_3$	${\mathit{k}}_4$	${\mathit{k}}_5$	${\mathit{k}}_6$	${\mathit{k}}_7$	${\mathit{k}}_8$
$g=1$	1	0.966	0.709	0.556	0.377	0.873	0.357	0.001
$g=2$	0.529	0.678	0.935	0.346	0.458	0.744	0.002	0.168

summarizes the optimized two division ratio vectors. Figure 10 displays the analog phase shift characteristics of all eight channels corresponding to the two optimized division ratio vectors. As a result, by continuously tuning a single $V_{ref}$, distinct phase shifts can be simultaneously induced across different channels.

To further assess the beamforming capability of the proposed scheme, the actual excitation phases ${Ø}_{rea,n}$ applied to each antenna element were measured and compared with the ideal excitation phases ${Ø}_{\mathrm{r}\mathrm{e}\mathrm{a},\mathrm{n}}$ for four steering angles: $-27°$, $-10°$, $14°$, and $32°$. As shown in Figure 11, the measured phases closely matched the ideal distributions across all cases, demonstrating that the proposed system can accurately synthesize the desired phase profiles for various beam directions. This performance was achieved using only a single additional shared control voltage ${\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}$ which significantly reduces the control complexity compared to conventional per-channel control methods.

Figure 12 presents the measured radiation patterns of the proposed hybrid analog–digital PSN. The multiple colored thin curves correspond to the radiation patterns measured under different steering angles and control states. The bold black curve represents the scanning envelope of the conventional 1-bit phased array, while the bold red curve shows the enhanced scanning envelope achieved by the proposed architecture. By employing only two additional shared control paths, the proposed array achieves a peak main-lobe gain improvement of 3.6 dB and a maximum SLL reduction to −4 dB, compared with the conventional 1-bit phased array, while maintaining stable beam performance within the ±50° steering range. These results clearly demonstrate that the proposed design significantly improves beamforming performance and radiation efficiency over the 1-bit array, while retaining remarkable hardware simplicity.

Therefore, the hybrid PSN provides a practical and scalable solution that effectively balances array performance, implementation cost, and control complexity, making it highly suitable for large-scale, low-cost phased-array applications.

6. Conclusions

This paper presented a low-complexity hybrid PSN based on a shared-control voltage architecture for high-gain phased-array applications operating at 0.915 GHz. Each channel integrates a 1-bit reconfigurable antenna and a voltage-controlled phase shifter, enabling continuous 0–360° phase tuning with an insertion loss below −1.2 dB and an amplitude fluctuation within ±0.2 dB. Compared with switched-type or reflective-type phase shifters, the proposed design exhibited lower insertion loss and minimal amplitude fluctuation. By employing reconfigurable passive resistor dividers, a single analog voltage source can simultaneously bias all channels, eliminating the need for per-channel voltage sources and substantially reducing system complexity. Compared with a conventional 1-bit PSN, the proposed architecture achieved up to 3.6 dB improvement in main-lobe gain while requiring only two additional control lines, thus demonstrating an excellent balance between performance and implementation simplicity.

Although experimentally verified at 0.915 GHz, the shared-control concept is frequency-independent and can be readily applied to high-frequency phased-array systems. Furthermore, the proposed hybrid PSN with shared-control architecture is not limited to linear arrays; it can be extended to planar or conformal arrays by employing orthogonal shared-control voltages or subarray-based voltage-distribution networks, thereby enabling two-dimensional beam steering while maintaining hardware simplicity. These characteristics make the proposed PSN a scalable, energy-efficient, and cost-effective solution for next-generation phased-array systems.