Resistor Variation Compensation for Enhanced Current Matching in Bandgap References

Abstract

A precision bandgap reference (BGR) is an essential building block in modern analog and mixed-signal systems, as it provides stable and predictable current and voltage references required for reliable operation across process, voltage, and temperature variations. However, one of the key challenges in conventional BGR circuits is their sensitivity to resistance variations, which directly impacts the accuracy of bias currents. Even small changes in resistance can lead to significant current mismatch between the core branches of the circuit, thereby degrading output stability and limiting the precision of the overall system. This degradation is particularly problematic in high-performance applications such as data converters, oscillators, and low-power biasing networks, where robust current matching is critical. To address this limitation, this work proposes a resistance-compensated BGR architecture that incorporates an auxiliary trimming network and a compensation branch. The trimming network senses variations in resistance and generates a control bias proportional to the deviation, while the compensation branch injects a corrective current into the output stage. By dynamically balancing the mismatch introduced by resistor spread, the proposed architecture effectively restores current stability across process corners. This method achieves reduction in the current variation across resistance corners from 21% to 3% in worst-case corners (±3%). This approach offers enhancement of current mismatches in analog systems in which robust current is essential.

1. Introduction

The bandgap reference (BGR) circuit is widely recognized as one of the most fundamental building blocks in analog and mixed-signal integrated circuits, as it serves the essential role of providing stable and predictable voltage and current references. Practically every subsystem in an integrated design—whether analog, digital, or mixed-signal—relies on a well-defined reference for correct biasing and reliable operation. When these reference levels fluctuate, circuit functions can quickly lose accuracy, leading to degraded performance at the system level. Ensuring stability is particularly challenging because bandgap circuits are inherently sensitive to environmental and technological factors, such as temperature changes, variations in supply voltage, and process differences introduced during semiconductor fabrication. Even slight deviations in the reference value can propagate through the system, resulting in measurable errors that compromise precision and reliability [1,2].

The need for robust and invariant reference circuits becomes even more apparent in high-precision applications. For example, in oscillators, maintaining a highly stable bias current is crucial to guarantee that the output clock frequency remains accurate under all operating conditions. Any drift in the reference current directly shifts the oscillation frequency, creating timing errors that may cascade through digital logic or communication systems. Similar challenges exist in other key circuit blocks such as analog-to-digital converters (ADCs), phase-locked loops (PLLs), and voltage regulators. In each case, the performance of the system hinges on the stability of the reference, making the BGR a cornerstone of reliable circuit design [3].

To achieve this stability, the conventional bandgap reference circuit leverages the principle of combining two temperature-dependent signals with opposite behaviors, such that their variations cancel each other out. The first component is the complementary-to-absolute-temperature (CTAT) voltage, derived from the base–emitter voltage V_BE of a bipolar transistor. This quantity naturally decreases with increasing temperature, producing a negative temperature coefficient. The second component is the proportional-to-absolute-temperature (PTAT) voltage, obtained from the difference in base–emitter voltages ΔV_BE of two transistors operating at different current densities. In contrast to V_BE, this difference increases linearly with temperature, producing a positive temperature coefficient. By appropriately scaling these two voltages and summing them together, the negative slope of the CTAT component cancels the positive slope of the PTAT component. The resulting output voltage becomes nearly independent of temperature and is designed to approximate the silicon bandgap voltage, which is around 1.2 V at room temperature [4,5].

This basic principle underlies most bandgap reference circuits used today and provides a foundation for further enhancements. While the conventional architecture successfully reduces temperature dependence, additional refinements are often needed to address other issues, such as sensitivity to supply variations, mismatch caused by device geometry, and process-induced spread in resistor and transistor parameters. These factors remain critical challenges in advanced CMOS technologies, where reduced headroom and shrinking device dimensions magnify the effects of variability. As a result, research continues to explore new topologies and compensation techniques that build upon the conventional bandgap model to deliver ever more accurate and reliable references for modern integrated systems.

Recent works highlight complementary directions in advancing voltage and current references. Azimi et al. [6] propose a two-stage sub-threshold voltage reference that employs body-bias curvature compensation, achieving a remarkably low temperature coefficient (≈26.7 ppm/°C), low line sensitivity (≈17.1 ppm/V), and power consumption in the picowatt range. Their approach emphasizes curvature correction for ultra-low-power operation. In contrast, Gagliardi et al. [7] present a CMOS-only current reference that exploits geometry-dependent threshold voltage V_TH variations to realize first-order temperature compensation within a single core, demonstrating a temperature coefficient of ≈194 ppm/°C and line sensitivity of ≈−0.017%/V across Monte Carlo analysis. These recent contributions underscore the active exploration of curvature- and temperature-compensation techniques in the literature.

Our work targets a complementary design axis: process-induced resistor variation. Specifically, we propose a bandgap reference architecture with an auxiliary trimming network and compensation branch designed to suppress the sensitivity of bias currents to resistor mismatches. Unlike curvature-compensation methods, which primarily address temperature dependencies, the proposed approach directly mitigates process spread in resistors—one of the most dominant sources of error in deep-submicron CMOS. Importantly, this strategy can be combined with existing temperature-compensation techniques, thereby offering a pathway toward robust, multi-dimensional improvement in reference stability.

2. Materials and Methods

All the results presented in this paper were obtained through circuit-level simulations performed in the Cadence design environment, including AC, transient, DC, and stability analyses. In addition, generative artificial intelligence tools were employed to refine the written content, specifically for rephrasing preliminary drafts into a more formal and scientific style. In certain instances, AI assistance was also used to generate text passages after the underlying concepts and ideas had been initially outlined in an informal manner.

3. Bandgap Architectures

3.1. Voltage-Mode Bandgap References

This architecture is now the most widely adopted method for producing stable reference voltages across integrated circuits. In its voltage-mode form, as shown in Figure 1, the output is designed to approximate the fundamental bandgap voltage of the semiconductor material used (around 1.2 V for silicon) [8,9]. The key principle is the combination of two voltages with opposing thermal behaviors: a positive temperature coefficient (PTAT) term that rises linearly with absolute temperature and a negative temperature coefficient (CTAT) term that decreases with temperature.

The PTAT voltage is generated by the difference in base–emitter voltages between two BJTs operated at distinct current densities, whereas the CTAT contribution is taken from the forward voltage drop of a diode-connected BJT. A practical circuit typically integrates a core bandgap network, an operational amplifier to maintain balance between nodes, resistors to set ratios, and current mirrors for biasing. The base–emitter voltage of a transistor can be expressed as

$${\mathrm{V}}_{\mathrm{BE}} =V_T\mathit{ln}\left({\displaystyle \frac{I}{I_s}}\right)$$

(1)

and the PTAT difference between two devices of area ratio n is given by

$$∆{\mathrm{V}}_{\mathrm{BE}}={\mathrm{V}}_{\mathrm{EB}2}-{\mathrm{V}}_{\mathrm{EB}1}=V_T\mathit{ln}\left(n\right)$$

(2)

In the standard structure, the operational amplifier regulates the differential nodes, causing the current I₁ through resistor R₁ to be proportional to temperature. Adding this PTAT voltage to the CTAT base–emitter voltage of another transistor produces the final reference

$${\mathrm{V}}_{\mathrm{ref}}={\mathrm{V}}_{\mathrm{EB}3}+{ V}_T\mathit{ln}\left(n\right)\left({\displaystyle \frac{R_b}{R_a}}\right)$$

(3)

Selecting an appropriate resistor ratio ensures that these two effects nearly cancel, yielding a reference with minimal temperature drift.

Despite its robustness, this approach has drawbacks in advanced processes. The PTAT generation loop is constrained by the current–voltage behavior of vertical BJTs and by the common-mode range of the amplifier. Consequently, traditional bandgap circuits, which inherently produce ~1.2 V outputs, cannot operate efficiently in ultra-low-voltage environments [9]. In such cases, current-mode bandgap architectures become preferable, as they require less headroom and can sustain operation under the reduced supply levels of deep-submicron CMOS [10].

3.2. Current-Mode Bandgap Reference

Figure 2 illustrates a current-mode BGR in which transistors Q₁, Q₂, and resistor R₁ constitute the Brokaw-type PTAT current generator. The operational amplifier provides negative feedback, regulating the bias so that nodes V_A and V_B are held at the same potential. With this condition, resistor R₁ conducts a PTAT current, while resistor R₂—placed across the diode-connected device—carries a CTAT current. As a result, the total current through transistors (M_p1–M_p4) include both PTAT and CTAT components, and the gates of the transistors share a common node to provide the current mirror connection to ensure correct circuit functionality, transistors (M_p1–M_p4) are required to operate in the saturation region, while transistors (M_p5–M_p8) are incorporated as cascode devices. Therefore, the current flowing through (M_p1–M_p4) is the same, as described by (4).

$${\mathrm{I}}_1={\mathrm{I}}_2={\mathrm{I}}_{\mathrm{o}}$$

(4)

The op-amp from the circuit has a folded cascode architecture to provide high gain so that the voltages at its two inputs are the same; thus, from Figure 1, V_B = V_EB1.

Therefore,

$${\mathrm{I}}_{11}{\mathrm{R}}_2={\mathrm{V}}_{\mathrm{B}}={\mathrm{V}}_{\mathrm{A}}={\mathrm{V}}_{\mathrm{EB}1}$$

(5)

$${\mathrm{I}}_{11}={\displaystyle \frac{∆{\mathrm{V}}_{\mathrm{EB}1}}{{\mathrm{R}}_2}}$$

(6)

and,

$${\mathrm{I}}_{12}{\mathrm{R}}_1={\mathrm{V}}_{\mathrm{A}}-{\mathrm{V}}_{\mathrm{EB}2}$$

(7)

$$={\mathrm{V}}_{\mathrm{B}}- {\mathrm{V}}_{\mathrm{EB}2}$$

(8)

$$={\mathrm{V}}_{\mathrm{EB}1}- {\mathrm{V}}_{\mathrm{EB}2}=∆{\mathrm{V}}_{\mathrm{EB}}$$

(9)

$${\mathrm{I}}_{12}={\displaystyle \frac{∆{\mathrm{V}}_{\mathrm{EB}}}{{\mathrm{R}}_1}}$$

(10)

Based on those findings, the output reference voltage of the current-mode BGR is obtained as follows,

$${\mathrm{V}}_{\mathrm{ref}}={\mathrm{R}}_{\mathrm{o}}{\mathrm{I}}_{\mathrm{o}}={\mathrm{R}}_4{\mathrm{I}}_1$$

(11)

$$={\mathrm{R}}_{\mathrm{o}}\left({\mathrm{I}}_{11}+{\mathrm{I}}_{12}\right)$$

(12)

$$={\mathrm{R}}_{\mathrm{o}}\left({\displaystyle \frac{∆{\mathrm{V}}_{\mathrm{EB}1}}{{\mathrm{R}}_2}}+{\displaystyle \frac{∆{\mathrm{V}}_{\mathrm{EB}}}{{\mathrm{R}}_1}}\right)$$

(13)

The trade-off is headroom: as V_DD drops, device overdrive shrinks, intrinsic gain (A₀ ∝ g_mr_o) and output swing decrease, and non-dominant poles shift—so phase margin can degrade unless compensation is retuned. To keep GBW at a given load, g_m must be maintained, which implies either modestly higher bias current (power) or more efficient g_m/I_D biasing. In our design, sizing and bias were optimized to preserve gain and stability with low power in the targeted supply range; while ultra-low V_DD operation is more challenging for folded-cascode stages, within our range it offers a balanced compromise among gain, stability, and power.

For a practical emitter-area ratio of 8 between Q₁ and Q₂, canceling temperature drift can be achieved by selecting an appropriate ratio of R₂/R₁. This tuning minimizes the overall temperature coefficient of the output voltage. A key advantage of this architecture is its ability to generate reference voltages below 1 V, which also reduces the supply voltage requirement compared with voltage-mode BGRs.

Despite this benefit, several drawbacks limit the use of current-mode bandgaps. First, the circuit has multiple possible operating points, unlike voltage-mode BGRs that typically have only two. For example, if the bias current is very small, the current primarily flows through R₁ and R₂ until Q₁ and Q₂ transition from off to on. When Q₁ and Q₂ remain off, the structure is highly symmetrical, and the op-amp can stabilize the circuit at any current level up to a few microamps—an undesirable condition. By contrast, voltage-mode references lack this symmetry and therefore avoid such unwanted equilibria.

Second, the current-mode BGR inherently generates only ZTAT (zero temperature coefficient) currents. This is a disadvantage in applications where PTAT currents are required, such as temperature sensors, constant-gm biasing, or RF circuits. In contrast, the voltage-mode architecture naturally provides PTAT currents.

Third, the op-amp offset and noise are magnified more severely in current-mode references. Because R₂ loads the op-amp input, the offset error is amplified by the same gain as the PTAT component, making this structure more sensitive than voltage-mode designs.

Finally, resistor R₂, which provides the CTAT component, often requires a very large resistance value—on the order of 4.3 Mohm as in the designed BGR—leading to considerable silicon area consumption. This area penalty is another practical drawback of the current-mode approach.

Bandgap reference (BGR) circuits can fall into two states: the desired operating state, which produces a stable ~1.2 V reference, and an undesired zero-current state, where all devices are off and the output remains at zero. To prevent lock-up at startup, a dedicated circuit (startup circuit) provides a small bias “kick” that forces the core into operation. Once the reference is established, the startup circuit automatically turns off, ensuring reliable initialization without disturbing steady-state behavior, as shown in Figure 3 [11]. An RC filter is used after the bandgap reference output to act as a low-pass filter, suppressing high-frequency noise, improving PSRR, reducing startup glitches, and ensuring a clean, stable DC reference voltage. The resistors are more susceptible to process and temperature variations [12,13].

4. The Proposed Biasing Compensation Circuit

Figure 4 illustrates the proposed compensation circuit, which is specifically designed to suppress process-induced resistor variations that often limit the precision of bandgap reference (BGR) circuits. In modern CMOS technologies, resistor mismatches resulting from lithographic and doping fluctuations constitute one of the most dominant sources of inaccuracy, as they directly perturb the resistance ratio used for generating the proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) currents. Such deviations inevitably alter the bias currents of the circuit, thereby compromising the temperature independence and stability of the generated reference voltage. Since these inaccuracies propagate into analog and mixed-signal building blocks, they can significantly degrade the performance of precision systems such as analog-to-digital converters (ADCs), phase-locked loops (PLLs), and voltage regulators. Therefore, addressing resistor variability is a key requirement for designing high-accuracy and reliable reference circuits.

The underlying principle of the architecture lies in reusing the BGR’s output current to establish a self-correcting biasing mechanism. Specifically, transistors Mn1–Mn2 are configured as a current mirror to replicate the bandgap-derived current with high fidelity, while Mn3–Mn4 are employed as cascode devices to enhance output resistance. The adoption of the cascode structure is essential, as it mitigates the channel-length modulation effect and significantly improves current replication accuracy under variations in supply voltage and process parameters. This arrangement results in a highly stable biasing node, which not only preserves the integrity of the mirrored current but also strengthens the circuit’s immunity against second-order effects such as mobility degradation and threshold-voltage mismatches.

A key innovation of the architecture is the introduction of a bias voltage, denoted as V_bias, which is designed to be directly proportional to the resistance R_bg. This proportionality naturally gives rise to a compensation current, I_comp, that also scales linearly with R_bg. This compensation current is intentionally designed to oppose the variation in the bandgap current I_bg, which is inversely proportional to the same resistance. By exploiting this natural proportional–inverse relationship, the two currents partially cancel each other’s process dependence. The net result is an output current, I_out, that demonstrates a much weaker sensitivity to resistor fluctuations compared to conventional BGR designs.

To further improve the robustness of the proposed architecture under worst-case operating conditions, a three-bit digital trimming mechanism is incorporated into the resistance path as shown in Figure 5. Specifically, R_trim is realized as a series ladder with one always-on segment of 921.8 kΩ and three selectable segments of 221.246 kΩ, 442.492 kΩ, and 884.984 kΩ, each shunted by a switch (open ⇒ segment included; closed ⇒ bypassed). Thus, at 27 °C,

$${\mathrm{R}}_{\mathrm{t}\mathrm{r}\mathrm{i}\mathrm{m}}\left(\mathrm{T}\right)=921.8 \mathrm{K}\Omega +\mathrm{S}0. 221.246 \mathrm{k}\Omega +\mathrm{S}1. 442.492 \mathrm{k}\Omega +\mathrm{S}2. 884.984 \mathrm{k}\Omega$$

(14)

with Si ∈ {0,1}. This yields eight codes spanning 0.922 MΩ (all bypassed) to 2.471 MΩ (all included). All the segments use the same resistor type, so the temperature dependence is common-mode:

$${\mathrm{R}}_{\mathrm{t}\mathrm{r}\mathrm{i}\mathrm{m}}\left(\mathrm{T}\right)={\mathrm{R}}_{\mathrm{t}\mathrm{r}\mathrm{i}\mathrm{m},27 }\left[ 1+{\alpha }_R\left(T-27 °\mathrm{C}\right) \right]$$

(15)

where ${\alpha }_R$ is the first-order TCR from the PDK; hence, ratios and trim resolution are preserved versus temperature while the absolute value scales uniformly.

The inclusion of this trimming scheme allows fine-grained adjustment of the effective resistance value, thereby providing a practical means of compensating for fabrication-induced deviations that cannot be fully addressed through the intrinsic compensation technique alone. Extreme process corners such as slow–slow (SS) and fast–fast (FF) often introduce significant shifts in resistance values, which in turn strongly impact the stability and accuracy of the bandgap current. By enabling programmable correction of the resistance, the trimming network ensures that the effective resistance remains close to the intended design target, thereby stabilizing circuit behavior across all the process variations. Moreover, maintaining the trimming resistance constant across different corners improves yield and manufacturability by allowing post-fabrication calibration to align each device instance with the nominal performance specification.

The mathematical behavior of the circuit can be summarized as follows:

$${\mathrm{V}}_{\mathrm{bias}}= {\mathrm{V}}_{\mathrm{DD}} - {\mathrm{I}}_{\mathrm{bg}}{\mathrm{R}}_{\mathrm{trim}}$$

(16)

$${\mathrm{R}}_{\mathrm{trim}}=\mathrm{Constant}=\mathrm{k}$$

(17)

$${\mathrm{I}}_{\mathrm{bg}}={\displaystyle \frac{\Delta {\mathrm{V}}_{\mathrm{BE}}}{{\mathrm{R}}_{\mathrm{bg}}}}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{T}}{\mathrm{l}}_{\mathrm{n}}\left(\mathrm{n}\right)}{{\mathrm{R}}_{\mathrm{bg}}}}$$

(18)

$${\mathrm{I}}_{\mathrm{bg}} \mathrm{\alpha } {\displaystyle \frac{1}{{\mathrm{R}}_{\mathrm{bg}}}}$$

(19)

$${\mathrm{V}}_{\mathrm{bias}} \mathrm{\alpha } {\mathrm{R}}_{\mathrm{bg}}$$

(20)

$${\mathrm{I}}_{\mathrm{out}}={\displaystyle \frac{ {\mathrm{V}}_{\mathrm{T}}{\mathrm{l}}_{\mathrm{n}}\left(\mathrm{n}\right)}{{\mathrm{R}}_{\mathrm{bg}}}}+\mathrm{k}·{\mathrm{R}}_{\mathrm{bg}}$$

(21)

$${\mathrm{I}}_{\mathrm{out}}={\mathrm{I}}_{\mathrm{bg}}+{\mathrm{I}}_{\mathrm{comp}}$$

(22)

where V_bias is the generated bias voltage, I_bg denotes the conventional bandgap current, I_comp represents the compensation current, and R_trim is the trimming resistance. From these relations, it can be observed that the opposing dependencies of I_bg and I_comp on the resistance value naturally cancel out, thereby stabilizing the total output current I_out.

In summary, the proposed compensation circuit introduces a systematic method to neutralize process-driven resistor variations in bandgap circuits. By exploiting mirrored currents, cascode stabilization, and a proportional compensation mechanism, the architecture ensures that the generated bias current remains highly stable across a wide range of process conditions. The addition of a compact trimming feature further guarantees robustness under corner cases. This makes the design particularly suitable for precision analog blocks, such as oscillators, ADCs, and PLLs, where stable biasing is critical for ensuring accuracy and reliability. From Equations (10)–(16), it follows that while ${\mathrm{I}}_{\mathrm{bg}}$ decreases with ${\mathrm{R}}_{\mathrm{bg}}$, ${\mathrm{I}}_{\mathrm{comp}}$ increases with ${\mathrm{R}}_{\mathrm{bg}}$. The resulting output current, therefore, exhibits reduced sensitivity to resistor variations, providing a theoretical basis for the process compensation achieved in this work.

The effectiveness of the compensation scheme can be quantified by examining the sensitivity of the output current to resistor variations:

$${\displaystyle \frac{\partial I_{out}}{\partial {\mathrm{R}}_{\mathrm{bg}}}}={\displaystyle \frac{ {\mathrm{V}}_{\mathrm{T}} l_n\left(n\right)}{{{\mathrm{R}}_{\mathrm{bg}}}^2 }}+k$$

(23)

By carefully selecting the proportionality constant k, this derivative can be minimized or even nulled, implying that the output current becomes largely insensitive to changes in ${\mathrm{R}}_{\mathrm{bg}}$. This analytical proof confirms that the proposed design significantly reduces process dependence compared to conventional BGR implementations.

5. Results

The proposed compensation circuit has been designed to operate under a nominal supply voltage of 2.5 V and has been evaluated across a wide temperature range extending from –40 °C to 125 °C, thereby ensuring its suitability for standard industrial applications. The performance of the circuit has been thoroughly assessed through Spectre simulations, which provide reliable insights into its behavior under varying process and environmental conditions.

As summarized in

Table 1. Current output variation across resistance corners on each MOSFET corner.

MOSFET Corner	TT	SS	FF	SF	FS
Uncompensated Ibg (±%)	21	21	21	21	21
Iout Variation (+%)	0.039	3	1.14	1.58	0.45
Iout Variation ($-\mathrm{\%}$)	0.45	2.21	2.96	1.38	1.45

, the proposed compensation technique results in a significant improvement in robustness against resistance corner variations. Specifically, the current variation, which originally exhibited a deviation across resistance corners of approximately 21% (as illustrated in Figure 6) with a temperature coefficient of 154 ppm/C, is effectively reduced to nearly 3% after compensation and achieves a typical 0.45% current variation. Figure 7 shows the temperature coefficient of the output reference voltage (V_ref) across corners, which achieves 420.14 ppm/°C, and Figure 8 shows the transient analysis of the output reference voltage.

Figure 9 illustrates the current variation observed at the slow–slow (SS) and fast–fast (FF) process corners across the specified temperature range, where the circuit typically achieves a temperature coefficient of approximately 751 ppm/°C. This result further confirms that although process variations are effectively mitigated by the proposed compensation scheme, residual temperature dependence remains a limiting factor in overall accuracy. Future optimization may focus on incorporating higher-order curvature-compensation techniques or hybrid PTAT/CTAT balancing methods to further suppress temperature-induced deviations while preserving the low process sensitivity achieved in this work. Figure 10 shows values of Rtrim across temperature.

Figure 11 and Figure 12 show that V_ref and I_bg exhibit low line sensitivity across process corners, confirming that the bandgap core is effectively decoupled from V_DD. In contrast, the output current I_out demonstrates noticeable supply dependence due to its bias path being referenced to V_DD, as shown in Figure 13. This sensitivity can be mitigated by introducing a regulated bias voltage.

Figure 14 presents the simulated loop gain of the folded-cascode operational amplifier, demonstrating a minimum gain of approximately 57 dB with a corresponding gain margin of 32 dB. In addition, Figure 15 illustrates the loop phase response, where the amplifier exhibits a minimum phase margin of 70°, thereby confirming the stability of the proposed design under the intended operating conditions.

Figure 16 illustrates the power supply rejection (PSR) characteristics of the output current (I_out), which range from approximately –154 dB to –138 dB at DC. At a frequency of 100 MHz, the circuit achieves a maximum PSR of –118 dB. These results indicate that the implemented compensation scheme preserves the PSR performance, as no degradation is observed across the evaluated frequency range.

6. Discussion

Table 2. Comparison with other references.

Parameter	This Work	[14]	[15]	[16]
CMOS Technology	0.065-μm	0.18-μm	0.18-μm	0.13-μm
Supply (V)	2.5	1	3.3	-
Vref (V)	1.2	-	-	-
Iout (μA)	0.076	2	12.42	7.7
ITotal (μA)	6.7	-	32	-
TC (ppm/°C)	1500	153	1162	-
T range (°C)	−40 to 125	−40 to 120	−40 to 100	-
% Process	3	14	6	3.4

summarizes a performance comparison between the proposed bandgap reference (BGR) circuit and previously reported designs [12,13,14]. The proposed implementation in 65 nm CMOS operates with a 2.5 V supply and delivers a stable reference voltage of 1.2 V, while consuming a total bias current of 6.7 µA. Although the reported temperature coefficient (TC) of 1500 ppm/°C over the range –40 °C to 125 °C is higher than that achieved in [12] (153 ppm/°C) and [13] (1162 ppm/°C), hence the residual TC (~1500 ppm/°C), which means that the reference varies slightly with temperature. In ADCs, this appears as a small gain/offset drift (typically a few LSBs in high-resolution parts); in PLLs, it can mildly affect VCO gain and phase noise—within our target specs. We did not include curvature-compensation blocks because the work focuses on suppressing process-induced variation, which we identified as the dominant error source. Standard curvature-reduction techniques can be added if ultra-low TC is required without altering the proposed compensation approach; the proposed design achieves a deviation of only 3%, thereby demonstrating superior robustness against process variations. This performance marks a substantial improvement relative to previously reported works, namely 14% in [12], 6% in [13], and 3.4% in [14], highlighting the effectiveness of the implemented compensation technique in minimizing circuit sensitivity and ensuring higher accuracy. Furthermore, despite being realized in a more advanced process node, the circuit achieves reliable startup and stable biasing at lower power consumption than [13], which reports a current of 32 µA. Regarding mirrors, a current–voltage mirror (CVM) could further raise effective output resistance and desensitize the compensation branch to VDD and device/temperature shifts, tightening the I_bg ∝ $1/\mathrm{R}$ vs. I_comp ∝ $1/\mathrm{R}$ cancellation; the trade-offs are extra headroom, added poles (stability effort), and modest area/power, so we leave CVM integration as promising future work for ultra-low-VDD or tighter TC/line-sensitivity targets. These results demonstrate that the proposed design achieves a favorable trade-off among process insensitivity; in addition to that, the trimming scheme mainly provides a one-time post-fabrication calibration to correct resistor-induced process variations. Since the trimming elements (e.g., digital switches or fuse-programmed resistors) are static and not subject to continuous stress, their contribution to long-term drift is minimal. The dominant aging mechanisms in CMOS—such as bias temperature instability (BTI) and hot-carrier injection (HCI)—affect MOS transistors more strongly than passive trimming resistors. Therefore, the trimming network itself is expected to remain stable over time.

That said, some residual drift in the overall reference can still occur due to resistor aging, mobility degradation, or threshold-voltage shifts in the active devices. These are second-order effects and would impact both trimmed and untrimmed BGR designs. The trimming simply ensures that the circuit starts closer to its nominal point, which improves yield and stability across process corners.

7. Conclusions

This work presented a bandgap reference (BGR) architecture with an enhanced current-matching scheme achieved through process–resistance compensation. By introducing a biasing circuit that adjusts branch currents in response to trimming resistor variations, the proposed design reduces current mismatch between the core branches of the BGR, achieving a worst-case variation of only 3%. The simulation results further confirm that the architecture significantly lowers output voltage fluctuations compared to a conventional implementation, thereby improving both temperature stability and process tolerance.

The theoretical foundation of the technique lies in exploiting the opposing dependencies of the bandgap current, ${\mathrm{I}}_{\mathrm{bg}} \mathrm{\alpha } {\displaystyle \frac{1}{{\mathrm{R}}_{\mathrm{bg}}}}$, and the compensation current, I_comp $\mathrm{\alpha }$ R_bg. Their mutual cancellation ensures that the total output current, ${\mathrm{I}}_{\mathrm{out}}= {\mathrm{I}}_{\mathrm{bg}}+ {\mathrm{I}}_{\mathrm{comp}}$, becomes largely insensitive to resistor variations. The addition of cascode devices strengthens current mirroring accuracy, while the incorporation of a three-bit trimming network enables fine-tuning under extreme process corners such as SS and FF.

Together, these features establish a compact, high-stability solution that requires minimal area overhead while offering robustness against process-induced deviations. The proposed architecture is, therefore, particularly suitable for precision analog and mixed-signal applications, such as oscillators, ADCs, PLLs, and regulators, where reference accuracy and long-term reliability are of critical importance.