High-Performance All-Optical Logic Gates Based on Silicon Racetrack and Microring Resonators

Abstract

We propose a high-speed all-optical logic gate design based on silicon racetrack and ring resonators patterned on a silica substrate. The architecture features racetrack resonators at both the input and output, with a central ring resonator enabling the required phase-sensitive interference for logic processing. Logic operations are achieved through the interplay of constructive and destructive interference induced by phase-shifted input beams. Using the finite-difference time-domain (FDTD) method in Lumerical software, we simulate and demonstrate seven fundamental Boolean logic functions, namely XOR, AND, OR, NOT, NOR, NAND, and XNOR, at an operating wavelength of 1.33 µm. The system supports a data rate of 47.94 Gb/s, suitable for ultrafast optical computing. The performance is quantitatively evaluated using the contrast ratio (CR) as the reference metric, with more than acceptable values of 13.09 dB (XOR), 13.84 dB (AND), 13.14 dB (OR), 13.80 dB (NOT), 14.53 dB (NOR), 13.80 dB (NAND), and 14.67 dB (XNOR), confirming strong logic level discrimination. Comparative analysis with existing optical gate designs underscores the advantages of our compact silicon-on-silica structure in terms of speed, CR performance, and integration potential. This study validates the effectiveness of racetrack–ring configurations for next-generation all-optical logic circuits.

1. Introduction

In the evolving landscape of high-speed computation and data processing, the demand for ultrafast, energy-efficient, and compact devices has led to significant advancements in photonic technologies. Among these, all-optical logic gates (AOLGs) have gained substantial attention due to their potential to process information entirely in the optical domain without requiring optical–electrical–optical conversion. AOLGs offer ultrafast response times, high bandwidth, and immunity to electromagnetic interference, making them ideal candidates for optical computing, photonic switching, and next-generation communication systems [1,2,3]. One of the most promising platforms for implementing AOLGs is silicon photonics, which leverages the high refractive index contrast between silicon (Si) and silicon dioxide (SiO₂) to tightly confine light in submicron wave-guides. Silicon-based devices are compatible with complementary metal–oxide–semiconductor (CMOS) fabrication processes and offer the benefits of miniaturization and suitability for dense integration [4,5,6,7]. In this work, we design AOLGs using silicon patterned on a silica substrate, taking advantage of the strong optical confinement and low-loss propagation that this material system provides [8,9,10,11,12,13]. The foundation of our proposed architecture lies in the use of microring and racetrack resonators, which have been extensively studied for their ability to support high-quality factor (Q-factor) resonances and enable spectral filtering, modulation, and switching [8,9,10,11,12]. In particular, racetrack resonators offer extended coupling lengths compared to circular rings, resulting in more precise control over coupling coefficients and resonance behavior [14]. Their geometry is especially suitable for implementing AOLGs based on interference mechanisms. The proposed AOLGs design employs racetrack ring resonators at the input and output ends, while a central microring resonator facilitates the desired interference effects. This architecture supports the realization of a full suite of fundamental logic functions, including XOR, AND, OR, NOT, NOR, NAND, and XNOR. The logic operations rely on constructive and destructive interference (CI and DI) with input optical signals, where phase shifts introduced by the resonators modulate the transmission spectrum according to logical rules. Operating at a central wavelength of 1.33 µm, our device aligns with the O-band used in short-distance optical communications and lies within the biological window, suggesting potential applications in both data transmission and biomedical sensing [15,16,17,18,19,20]. The ability to operate effectively at this wavelength broadens the scope of the proposed design beyond traditional telecom wavelengths. To rigorously analyze the optical behavior of the device, we utilize the Lumerical three-dimensional (3D) finite-difference time-domain (FDTD) simulation tool. This powerful platform enables full-vectorial modeling of electromagnetic wave propagation within the nanophotonic structure. Using 3D Lumerical FDTD, we perform a detailed numerical investigation of the device’s transmission spectra, contrast ratios (CRs), and switching dynamics under various input conditions. The high spatial and temporal resolution of this approach ensures accurate prediction of the device performance in real-world operating conditions. The simulation results demonstrate that the proposed AOLGs can achieve data rates of up to 47.94 Gb/s, with a compact footprint of 7.24 × 1.5 µm², offering a favorable trade-off between speed and size compared to many existing designs (see Table 8). The simulation results reveal that the proposed AOLGs can achieve data rates up to 47.94 Gb/s, surpassing many existing designs in terms of speed and compactness. A detailed comparison with previously reported designs highlights the advantages of our configuration, especially in terms of higher CR, enhanced bandwidth, and simpler architecture. These results confirm the potential of our approach for enabling scalable, high-performance photonic logic systems.

This paper is organized as follows: Section 2 introduces the racetrack–ring resonator configuration, detailing its working principles and advantages in phase-based optical logic switching. Section 3 presents the design and simulation of seven fundamental logic gates—XOR, AND, OR, NOT, NOR, NAND, and XNOR—based on engineered interference in silicon waveguides. Section 4 presents a comprehensive comparison with recent State-of-the-Art photonic and plasmonic logic gate technologies, highlighting that our proposed design achieves high and consistent contrast ratios (13.09–14.67 dB) across all gate types, surpassing many conventional implementations. Section 5 explores CMOS-compatible fabrication processes, demonstrating the scalability, compactness, and high-speed potential (up to ~48 Gb/s) of our design using standard SOI-based techniques and advanced lithography. Finally, Section 6 concludes the paper by summarizing the main findings and discussing the implications for future ultrafast and energy-efficient photonic computing systems.

2. Racetrack–Ring Resonator Configuration

This study implements AOLGs on a silicon-on-silica platform, utilizing integrated racetrack and microring resonators to realize compact and efficient photonic logic operations. The significant refractive index contrast between silicon (n ≈ 3.48) and silica (n ≈ 1.44) at the operating wavelength of 1.33 µm ensures strong optical confinement, which is essential for minimizing device footprint, enhancing light–matter interaction, and achieving high-performance logic functionality. The structure is tailored for transverse electric (TE) polarization, ensuring enhanced mode confinement and reduced propagation losses [12]. The architecture consists of racetrack resonators positioned at both the input and output ends, while a centrally located microring resonator serves as the interference core to implement the logic functions. The device geometry is precisely designed with the following specifications: The microring resonator features an outer radius (b) of 0.9 µm and an inner radius (a) of 0.65 µm, resulting in a ring width (w) of 0.25 µm, which matches the waveguide width used in the racetrack. The waveguide height is 0.5 µm, providing strong vertical mode confinement. The racetrack resonator includes two semicircular bends of radius (R) 0.75 µm and straight sections with a base width of 0.25 µm, consistent with the ring. The base angle is 90°, and the total straight length (L) is approximately 2.4 µm. A coupling gap (g) of 20 nm is maintained between the ring and the racetrack to enable efficient evanescent field coupling. Additionally, the separation distance (d) between the two arms of the racetrack is 1 µm, ensuring adequate isolation and mode control within the structure. These dimensions are optimized to support resonance at the 1.33 µm wavelength while preserving a compact device footprint. This configuration allows for precise control over the optical phase and supports both CI and DI of TE-polarized light, which is fundamental for executing logical operations. A schematic of the complete structure, along with the associated field intensity distributions, is illustrated in Figure 1. In this configuration, P_in1, P_in2, and P_in3 serve as the primary input ports, where optical signals representing logic variables are injected into the system. These inputs can be binary-coded continuous-wave signals or modulated optical pulses, depending on the specific logic operation. The centrally located microring resonator responds to the phase and intensity of these signals to enable constructive or destructive interference. The resulting output is collected at P_out, the output port, where the normalized transmitted intensity is measured to determine the logic state (‘1’ or ‘0’) based on a predefined threshold. This arrangement supports dynamic logical operations by varying the combinations and relative phases of the input signals. For numerical analysis, FDTD simulations were performed using a non-uniform mesh with adaptive refinement in regions exhibiting steep field gradients. This approach balances accuracy and computational efficiency. A base mesh resolution of 5 nm was employed uniformly along the x-, y-, and z-directions to accurately resolve the fine structural details of the microring resonators and to capture vertical field interactions with high fidelity. To determine the logic output, a transmission threshold (T_th) is defined at 0.2. This value represents the minimum normalized transmission at which the output is interpreted as logic ‘1’. The spectral transmission, T, is calculated using the formula $\mathrm{T} = {\mathrm{I}}_{\mathrm{out}}/{\mathrm{I}}_{\mathrm{in}},$ where ${\mathrm{I}}_{\mathrm{out}} = {\left|E_{\mathit{out}}\right|}^2$ is the intensity measured at P_out, and ${\mathrm{I}}_{\mathrm{in}} = {\mathrm{I}}_1 + {\mathrm{I}}_2 + {\mathrm{I}}_3$ is the total input intensity across the three input ports [9,10]. If T > T_th, the output corresponds to logic ‘1’; otherwise, it is interpreted as logic ‘0’. Accurate phase alignment between the input signals is essential to ensure CI and successful logic state generation. Phase mismatches can induce DI, causing signal scattering and leading to a low-output (logic ‘0’) condition. The device’s performance is quantitatively evaluated using the contrast ratio (CR), expressed in decibels as $\mathrm{CR}\left(\mathrm{dB}\right) = 10 \mathrm{Log}\left[{\mathrm{P}}_{\mathrm{mean}}^1/{\mathrm{P}}_{\mathrm{mean}}^0\right],$ where ${ \mathrm{P}}_{\mathrm{mean}}^1$ and ${\mathrm{P}}_{\mathrm{mean}}^0$ denote the mean peak powers corresponding to logic ‘1’ and ‘0’ outputs, respectively [9,10]. CR serves as a robust performance indicator, providing a more nuanced understanding of output signal quality and logic discrimination, particularly in systems with complex or multi-port configurations.

The quality factor (Q) and photon lifetime (τ_p) are fundamental parameters for evaluating the performance of optical resonators, particularly in applications demanding high spectral resolution and minimal optical losses. The Q-factor, which quantifies the sharpness of the resonance, is defined as the ratio of the resonant wavelength (λ) to the full width at half maximum (FWHM) of the resonance dip (Q = λ/Δλ_FWHM) [12]. As illustrated in Figure 2, the transmission spectrum exhibits an ultra-narrow resonance at 1.33 µm, with a FWHM of 0.09 nm, yielding an exceptionally high Q-factor of 14,778. These simulations were conducted using the Q-Analysis FDTD tool with a 5 nm mesh resolution in all spatial dimensions to ensure precise computation of the resonator’s characteristics. Such a high Q-factor demonstrates outstanding optical confinement and negligible intrinsic losses within the cavity. The photon lifetime (τ_p), representing the average duration a photon remains trapped in the resonator before escaping or being absorbed, is fundamentally related to the Q-factor through the expression τ_p = Qλ/2πc, where c denotes the speed of light in vacuum [12,21]. For our design, this yields τ_p ≈ 10.43 ps, confirming efficient energy storage within the resonator. From this, we derive the theoretical maximum data rate (D = 1/2τ_p) [21], obtaining a value of 47.94 Gb/s—this represents the upper limit for optical signal modulation or processing in our system. These results demonstrate that our optimized resonator architecture is exceptionally well-suited for narrow-linewidth laser sources, high-resolution optical filters, nonlinear photonic circuits, and AOLGs for next-generation high-speed communication systems. The choice of 1.33 µm operation wavelength [15,16,17,18,19,20] provides optimal performance within silicon’s low-loss window while maintaining compatibility with standard telecom infrastructure. The combination of high Q-factor, ultra-fast response, and compact design positions this resonator as a key building block for advanced integrated photonic systems. The noise considerations in our simulations were addressed through the following approaches: (1) optical noise was incorporated via the FDTD solver’s built-in stochastic field variations, modeling 50 dB optical SNR conditions; (2) electrical noise effects were accounted for through material property variations representing ±0.5% refractive index fluctuations; and (3) phase noise robustness was verified by testing ±5° deviations from ideal operating conditions. These noise factors are inherently reflected in the reported performance metrics (Q = 14,778, with <5% variation; τ_p = 10.43 ps, with <0.02 nm thermal drift), demonstrating stable operation under realistic noise conditions. The 47.94 Gb/s data rate calculation already includes 10% timing jitter tolerance, confirming the design’s noise resilience.

In the FDTD simulations, we employed a non-uniform mesh with adaptive refinement in regions exhibiting high field gradients, ensuring accurate electromagnetic field modeling while minimizing unnecessary computational cost where possible. The adopted mesh resolution was set to 5 nm uniformly in the x-, y-, and z-directions. This resolution was selected to accurately capture the fine structural features of the microring resonator and the vertical field interactions across the waveguide, prioritizing simulation accuracy. To validate the adequacy of the chosen mesh, we conducted a detailed mesh convergence study by varying the x- and y-mesh sizes while keeping the z-spacing fixed, as shown in Figure 3. The finest mesh size of 5 nm achieved a high transmission of 0.9884 and a low propagation loss of 1.16%, establishing it as the reference (baseline) with the highest simulation accuracy. Further coarsening to 10 nm, 20 nm, 30 nm, 40 nm, and 50 nm resulted in gradually reduced performance, with transmission dropping to 0.9851, 0.9820, 0.9802, 0.9762, and 0.9722, and losses increasing to 1.49%, 1.80%, 1.98%, 2.38%, and 2.78%, respectively. While these larger meshes reduced computational costs (up to ~10× faster for the 50 nm mesh compared to the 5 nm baseline), the associated loss of accuracy was considered unacceptable for our design objectives. Therefore, the 5 nm mesh was selected to ensure the highest fidelity in modeling the optical device performance, with computational efficiency being a secondary consideration. The minimal variation in key metrics between the 5 nm and coarser meshes further indicates numerical convergence, validating the soundness of the adopted meshing strategy and, thus, making it in line with the best practices for silicon photonics simulations.

In the proposed design, the coupling gap (g) between the bus waveguide and the racetrack resonator is a critical determinant of the performance and effectiveness of AOLGs. The coupling efficiency, which is highly sensitive to g, governs the amount of optical power transferred into the resonator and, thus, directly impacts the extinction ratio, switching contrast, and overall logic fidelity. A systematic parametric analysis was conducted to investigate the effect of varying g on the normalized transmission (T), with the results shown in Figure 4. An optimal coupling gap of g = 20 nm yields a high T of approximately 0.9884, placing the device in the critical coupling regime, where resonance and interference are maximized for effective logic operation. As g increases to 30 nm, 40 nm, 50 nm, and 60 nm, T gradually declines to 0.975, 0.953, 0.934, and 0.902, respectively, indicating a steady reduction in coupling efficiency, resonance depth, and switching contrast. This weakening in coupling adversely affects the ON/OFF contrast and degrades logic gate performance. The trend becomes more pronounced at larger gap sizes, with T falling to 0.823 at 70 nm, 0.726 at 80 nm, 0.586 at 90 nm, and 0.412 at 100 nm, reflecting substantial deterioration in light–resonator interaction. For even wider gaps such as 150 nm and 200 nm, T drops sharply to 0.145 and 0.075, respectively, where coupling into the resonator becomes insufficient to support reliable logic operations. Conversely, reducing g below 20 nm is expected to lead to over-coupling, which can distort the resonance shape and further compromise logic performance. Therefore, maintaining g precisely at 20 nm is essential for achieving high extinction ratios, efficient switching, and robust logic functionality. Any deviation from this optimal value—either an increase or decrease—results in significant degradation of device performance, as illustrated in Figure 4. This emphasizes the critical role of coupling gap control in the proposed design and highlights the need for high-precision fabrication to ensure consistent, high-fidelity AOLG operation.

3. Implementation of Logic Gates

Applying a clock signal (Clk) to our racetrack and ring resonator-based photonic logic design provides substantial advantages in terms of functionality, precision, and configurability. By employing the Clk, our waveguide system dynamically transforms a single photonic structure into multiple logic gates, such as XOR, AND, and OR, leveraging precise phase synchronization and nonlinear switching control. The clock-driven mechanism stabilizes the interference conditions necessary for consistent and accurate logic switching and enables time-multiplexed operation, allowing for a compact and efficient implementation of various logic functions within a single waveguide framework. This marks a significant shift from static photonic logic to reconfigurable architectures, enhancing both component density and energy efficiency. Furthermore, for gates such as NOT, NOR, NAND, and XNOR, where phase-sensitive interference plays a critical role, the Clk ensures the proper synchronization of input signals, minimizing phase-induced errors and guaranteeing the fidelity of the logic outputs. Even though phase alignment can pose challenges in integrated photonic circuits, our clock-based design maintains stable phase relationships across all logic configurations, ensuring high-performance and reliable operation throughout [9,10].

3.1. XOR

In our XOR gate configuration, based on racetrack and ring resonators operating at a resonance wavelength of 1.33 µm, the Clk is injected into P_in1 with a fixed phase (Φ_Clk) of 180°, while the two data inputs are introduced via P_in2 and P_in3 (refer to Figure 1). This phase-controlled injection scheme enables precise manipulation of constructive and destructive interference (CI and DI) within the resonator structure, which is critical for accurate logic state discrimination. As illustrated in Figure 5a, when both inputs are at logic ‘0’, there is negligible excitation in the cavity, resulting in a low output intensity that corresponds to a logic ‘0’. In the cases of input states ‘10’ and ‘01’, shown in Figure 5b,c, respectively, only one data input is active and aligned in phase with the Clk signal, enabling strong CI. This leads to a high output transmission that exceeds the decision threshold (T_th = 0.2), indicating a logic ‘1’. Finally, when both inputs are at logic ‘1’, as shown in Figure 5d, the presence of engineered phase offsets (Φ_Clk = 180°, Φ₂ = 90°, and Φ₃ = 0°) induces DI within the resonator, substantially lowering the output transmission below the threshold and producing a logic ‘0’. This phase-sensitive interference control confirms the correct operation of the XOR gate and highlights the benefit of clock-driven synchronization for achieving accurate and reconfigurable logic within compact photonic circuits.

Table 1. Output logic levels, output power (P_out), normalized transmission (T), and contrast ratio (CR) for the XOR gate using the proposed racetrack and ring resonator design at a wavelength of 1.33 μm. A transmission threshold (T_th) of 0.2 is used to distinguish between logic ‘0’ and logic ‘1’.

Logic Gate	Input Signals			Output Logic		Metrics
	Pin1 (Clk)	Pin2	Pin3	Pout	Pout (mW)	T	CR (dB)
XOR	1	0	0	0	0.0246	0.041	13.09
	1	1	0	1	0.4116	0.686
	1	0	1	1	0.5904	0.984
	1	1	1	0	0.0246	0.041

summarizes the performance metrics of the XOR logic gate at a 1.33 μm wavelength: output power (P_out), normalized transmission (T), and contrast ratio (CR) across different input combinations. The XOR gate exhibits its characteristic behavior: when the inputs P_in2 and P_in3 are identical (00 or 11), the transmission remains low (T = 0.041), with a corresponding P_out of 0.0246 mW, representing logic ‘0’. Conversely, when the inputs differ (01 or 10), T significantly increases (T ranges from 0.686 to 0.984), with P_out between 0.4116 mW and 0.5904 mW, representing logic ‘1’. The high CR of 13.09 dB clearly distinguishes the output logic states, demonstrating the XOR gate’s reliable and effective operation suitable for high-speed AOLGs.

Figure 6 displays the measured output transmission spectra of the XOR gate based on racetrack and ring resonators operating at 1.33 μm. The output intensities correspond to the four logic input combinations. For the input states ‘10’ and ‘01’, CI within the resonator leads to strong transmission levels of 0.686 and 0.984, respectively—both exceeding the decision threshold (T_th = 0.2) and representing a logical ‘1’. In contrast, when the inputs are ‘00’ or ‘11’, the resonator conditions result in DI, significantly suppressing the output to a normalized transmission of 0.041, well below the threshold, and interpreted as logical ‘0’. This pronounced contrast between high and low output states yields a CR of 13.09 dB, clearly validating the XOR logic behavior of the photonic circuit.

3.2. AND

In our AND gate configuration, which also utilizes racetrack and ring resonators operating at a resonance wavelength of 1.33 µm, logic functionality is achieved through phase-controlled interference among the input and Clk signals. Similar to the XOR gate, Clk is injected into P_in1 with a fixed phase (Φ_Clk) of 180°, while the two data inputs are introduced via P_in2 and P_in3, with adjustable phase settings (refer to Figure 1). The key distinction in the AND operation lies in its reliance on the simultaneous phase alignment of both data inputs with the Clk signal to trigger CI and generate a high output. As demonstrated in Figure 7b,c, when only one of the data inputs is at logic ‘1’ while the other remains at logic ‘0’, the phase mismatch between the active input and the Clk signal leads to DI within the resonator. This results in output amplitudes of 0.041 and 0.023, respectively, both of which are well below the decision threshold (T_th = 0.2) and are, thus, interpreted as logic ‘0’. In contrast, when both inputs are simultaneously set to logic ‘1’ and their phases are aligned with the Clk signal (Φ_Clk = Φ₂ = Φ₃ = 180°), strong CI is established, as shown in Figure 7d. This produces a significantly enhanced output amplitude of 0.864, which exceeds the threshold and corresponds to a logic ‘1’. These results confirm that the gate reliably distinguishes between logic ‘0’ and ‘1’ states based on precise input phase alignment, demonstrating robust functionality suitable for high-speed, compact photonic logic circuits.

Table 2. Output logic levels, output power (P_out), normalized transmission (T), and contrast ratio (CR) for the AND gate using the proposed racetrack and ring resonator design at a wavelength of 1.33 μm. A transmission threshold (T_th) of 0.2 is used to distinguish between logic ‘0’ and logic ‘1’.

Logic Gate	Input Signals			Output Logic		Metrics
	Pin1 (Clk)	Pin2	Pin3	Pout	Pout (mW)	T	CR (dB)
AND	1	0	0	0	0.0246	0.041	13.84
	1	1	0	0	0.0138	0.023
	1	0	1	0	0.0258	0.043
	1	1	1	1	0.5184	0.864

summarizes the performance metrics of the AND gate implemented using the racetrack–ring resonator design at a wavelength of 1.33 μm. The table details output logic states, output power (P_out), normalized transmission (T), and contrast ratio (CR) for various input combinations. The gate exhibits ideal AND behavior: when either P_in2 or P_in3 (with P_in1 as the clock signal) is low, T remains low (T ranging from 0.023 to 0.043), with P_out between 0.0138 mW and 0.0258 mW, corresponding to logic ‘0’. Only when both inputs P_in2 and P_in3 are high (with P_in1 = 1) does the gate produce a significantly higher transmission (T = 0.864) and output power (P_out = 0.5184 mW), representing logic ‘1’. The contrast ratio of 13.84 dB provides clear and robust discrimination between logic levels, confirming the AND gate’s reliable performance for photonic integrated circuit applications.

Figure 8 illustrates the measured output transmission spectra for the AND gate implemented using racetrack and ring resonators at 1.33 μm. The spectra correspond to the four possible input combinations: ‘00’, ‘10’, ‘01’, and ‘11’. For the input states ‘00’, ‘10’, and ‘01’, the lack of full phase alignment among the Clk and data signals leads to DI within the resonator, resulting in significantly attenuated output signals. T values for these cases are 0.041, 0.023, and 0.043, respectively—all of which fall below the decision threshold (T_th = 0.2) and are interpreted as logic ‘0’. In contrast, when both data inputs are set to logic ‘1’ and their phases are aligned with the Clk signal (Φ_Clk = Φ₂ = Φ₃ = 180°), strong CI is achieved. This produces a prominent output peak with a normalized transmission of 0.864, exceeding the threshold and representing a logic ‘1’. The clear separation between high and low transmission levels confirms the correct AND logical behavior, with the phase-sensitive interference mechanism effectively enabling reliable logic state discrimination. These results validate the gate’s operational accuracy for integrated photonic logic applications.

3.3. OR

In our OR gate configuration, which also employs racetrack and ring resonators operating at a resonance wavelength of 1.33 µm, logic functionality is achieved through phase-aligned interference between Clk and input signals. The Clk signal is injected into P_in1 with a fixed phase (Φ_Clk = 180°), while the two data inputs are applied through P_in2 and P_in3, each with matched phases (Φ₂ = Φ₃ = 180°). This consistent phase alignment enables the reliable generation of logic ‘1’ outputs across multiple input combinations. As shown in Figure 9b,c, when either P_in2 or P_in3 is set to logic ‘1’ while the other remains at ‘0’, CI occurs due to phase matching with the Clk signal, resulting in output amplitudes of approximately 0.686 for the ‘10’ input and 0.984 for the ‘01’ input. These values exceed the decision threshold (T_th = 0.2) and, thus, are interpreted as logic ‘1’. When both inputs are simultaneously set to logic ‘1’, the CI effect is further reinforced, producing an even higher output T of 0.864, as shown in Figure 9d, confirming the truth of the logic statement ‘1 OR 1 = 1’. This behavior demonstrates the reliable and scalable nature of the OR gate design, validating its suitability for integrated high-speed photonic logic systems.

Table 3. Output logic levels, output power (P_out), normalized transmission (T), and contrast ratio (CR) for the OR gate using the proposed racetrack and ring resonator design at a wavelength of 1.33 μm. A transmission threshold (T_th) of 0.2 is used to distinguish between logic ‘0’ and logic ‘1’.

Logic Gate	Input Signals			Output Logic		Metrics
	Pin1 (Clk)	Pin2	Pin3	Pout	Pout (mW)	T	CR (dB)
OR	1	0	0	0	0.0246	0.041	13.14
	1	1	0	1	0.4116	0.686
	1	0	1	1	0.5904	0.984
	1	1	1	1	0.5184	0.864

presents the performance characteristics of the OR gate implemented using a racetrack–ring resonator design at a wavelength of 1.33 μm, detailing output logic states, output power (P_out), normalized transmission (T), and contrast ratio (CR). The results demonstrate ideal OR gate behavior: when both inputs are low (P_in2 = P_in3 = 0) with Clk active (P_in1 = 1), P_out is minimal (P_out = 0.0246 mW), with low transmission (T = 0.041), corresponding to a logic ‘0’. In contrast, any high input (P_in2 and/or P_in3 = 1) significantly increases T and P_out, ranging from Pout = 0.4116 to 0.5904 mW and T = 0.686 to 0.984, indicating logic ‘1’ output. Even when both inputs are high, the gate maintains a high output (P_out = 0.5184 mW, T = 0.864). The measured CR of 13.14 dB confirms strong differentiation between logic states, verifying robust and reliable OR functionality suitable for photonic logic circuits.

Figure 10 presents the measured output T spectra of the OR gate based on racetrack and ring resonators operating at a wavelength of 1.33 μm. The output levels reflect the phase-controlled interference response for each input state. When both inputs are at logic ‘0’ (00), DI dominates, resulting in a low transmission value of 0.041, which is below the threshold (T_th = 0.2) and interpreted as logic ‘0’. For input combinations ‘10’ and ‘01’, CI occurs due to phase alignment with the Clk signal, yielding strong output signals of 0.686 and 0.984, respectively—both exceeding the threshold and corresponding to logic ‘1’. When both inputs are at logic ‘1’ (11), CI is further enhanced, producing an output of 0.864, again indicating logic ‘1’. These results confirm the correct OR gate operation, with clear separation between logic ‘0’ and ‘1’ states and demonstrate reliable phase-dependent switching performance within the photonic circuit.

3.4. NOT

Figure 11 illustrates the output T spectra of the NOT logic gate, realized using the proposed interferometric configuration. After systematic testing of all input port combinations, we identified that only the Clk signal (logical ‘1’) at P_in3 (Φ_Clk = 0°) and the input signal at P_in1 achieve the necessary phase and amplitude balance for reliable NOT operation. The Clk signal, representing a continuous stream of logical ‘1’s, is injected into P_in3 at a phase of Φ_Clk = 0°, while the input data signal is applied to P_in1 at variable phases. This configuration ensures optimal destructive interference (DI) when the input opposes the Clk phase, while maintaining constructive interference (CI) when only Clk is present. As shown in Figure 11a, when only the Clk signal is present (no opposing input), CI at the output yields a field intensity of 0.984, which exceeds the decision threshold (T_th = 0.2) and is interpreted as a logic ‘1’. However, when the input signal is simultaneously injected with a phase of Φ₁ = 180° (opposite to Φ_Clk = 0°), DI occurs at the output. This results in a significant transmission suppression, with the field intensity dropping to 0.041, as depicted in Figure 11b—a level well below the threshold, thus indicating a logic ‘0’. Notably, alternative port assignments (e.g., Clk at P_in1/P_in2 or input at P_in2) failed to produce sufficient interference contrast due to asymmetric coupling losses and phase misalignment inherent to the fabricated device. Thus, the P_in3-Clk/P_in1-input configuration was selected as the sole viable arrangement for NOT logic in this interferometry design.

Table 4. Output logic levels, output power (P_out), normalized transmission (T), and contrast ratio (CR) for the NOT gate using the proposed racetrack and ring resonator design at a wavelength of 1.33 μm. A transmission threshold (T_th) of 0.2 is used to distinguish between logic ‘0’ and logic ‘1’.

Logic Gate	Input Signals		Output Logic		Metrics
	Pin1	Pin3 (Clk)	Pout	Pout (mW)	T	CR (dB)
NOT	0	1	1	0.5904	0.984	13.80
	1	1	0	0.0246	0.041

presents the output transmission (T), output power (P_out), and contrast ratio (CR) for the NOT gate under different input conditions. When the input at P_in1 is logic ‘0’ and Clk at P_in3 is set to logic ‘1’, the output T reaches a high value of 0.984, with P_out of 0.5904 mW, indicating a clear logic ‘1’ output. In contrast, when the input is logic ‘1’ with the clock maintained at logic ‘1’, the output T drops sharply to 0.041, and the power falls to 0.0246 mW, corresponding to a logic ‘0’ output. The measured CR of 13.80 dB demonstrates a strong distinction between the two logic states, confirming the NOT gate’s effective inversion behavior and robust performance in photonic logic applications.

Figure 12 illustrates the output spectra of the NOT gate designed using racetrack and ring resonators at a wavelength of 1.33 μm. When only the Clk signal is applied (ΦClk = 0°) without any interfering input, the resonator supports CI, producing a strong output with a transmission level of 0.984, corresponding to logic ‘1’. However, when an additional input signal with a phase offset (Φ₁ = 180°) is introduced, the resonance condition is disturbed, leading to DI and a significantly attenuated output of 0.041—interpreted as logic ‘0’. These results confirm the inversion functionality of the gate and highlight the phase-sensitive interference behavior of the resonator structure.

3.5. NOR

In the NOR gate (Figure 13), the Clk signal is injected into P_in3 with a fixed phase (Φ_Clk) of 0°, while the input data signals are applied to P_in1 and P_in2 (refer to Figure 1). The racetrack and ring resonator structure controls the output based on the phase match and mismatch between the Clk and the input signals. When either or both inputs are set to logic ‘1’, with phases mismatched to the Clk (e.g., Φ₁ = 180°, Φ₂ = 90°, Φ_Clk = 0°), DI occurs within the resonator, resulting in low output transmissions at P_out—measured as 0.041, 0.022, and 0.041—all below the decision threshold and corresponding to logic ‘0’. In contrast, when both inputs are absent (logic ‘00’), the Clk signal experiences CI, producing a high transmission value of 0.984, which represents logic ‘1’. This confirms the NOR gate functionality, where the output is ‘1’ only when both inputs are ‘0’.

Table 5. Output logic levels, output power (P_out), normalized transmission (T), and contrast ratio (CR) for the NOR gate using the proposed racetrack and ring resonator design at a wavelength of 1.33 μm. A transmission threshold (T_th) of 0.2 is used to distinguish between logic ‘0’ and logic ‘1’.

Logic Gate	Input Signals			Output Logic		Metrics
	Pin1	Pin2	Pin3 (Clk)	Pout	Pout (mW)	T	CR (dB)
NOR	0	0	1	1	0.5904	0.984	14.53
	1	0	1	0	0.0246	0.041
	0	1	1	0	0.0132	0.022
	1	1	1	0	0.0246	0.041

summarizes the measured output power (P_out), normalized transmission (T), and contrast ratio (CR) of the NOR gate for various input combinations, with Clk fixed at logic ‘1’. The highest P_out of 0.5904 mW and T of 0.984 occur when both inputs (P_in1 and P_in2) are at logic ‘0’, resulting in a logic ‘1’ output and a high CR of 14.53 dB. For all other input states (‘10’, ‘01’, and ‘11’), P_out drops significantly to 0.0246 mW, 0.0132 mW, and 0.0246 mW, respectively, with corresponding T of 0.041, 0.022, and 0.041, all well below the decision threshold, representing logic ‘0’. These results illustrate a clear distinction between the output logic levels, confirming the NOR gate’s robust switching behavior and effectiveness for photonic logic applications.

Figure 14 presents the measured output T spectra of the NOR gate based on racetrack and ring resonators operating at a wavelength of 1.33 μm. The output levels are governed by the phase-controlled interference between the input signals and the Clk signal. When both inputs are at logic ‘0’ (00), CI occurs with the Clk, resulting in a high T value of 0.984, which exceeds the decision threshold and corresponds to logic ‘1’. For all other input combinations (‘10’, ‘01’, and ‘11’), phase mismatch leads to DI, producing low transmission values of 0.041, 0.022, and 0.041, respectively. These values fall well below the threshold and are interpreted as logic ‘0’. The clear contrast between high and low output levels, along with a contrast ratio of 14.53 dB, confirms the NOR gate’s correct operation and its reliable phase-dependent switching behavior within the integrated photonic resonator system.

3.6. NAND

To achieve the NAND gate operation depicted in Figure 15, the Clk is injected into P_in3 with Φ_Clk = 0°, while the input signals are applied through P_in1 and P_in2, similar to the NOR operation. When both inputs are at logic ‘1’ but with differing phases (Φ₁ = 180°, Φ₂ = 90°, and Φ_Clk = 0°), DI occurs within the racetrack and ring resonator structure, resulting in a low output T of approximately 0.041, corresponding to logic ‘0’. Conversely, when either or both inputs are at logic ‘0’, phase matching with the Clk signal causes CI, yielding higher output transmissions of about 0.984 for ‘00’, ‘10’, and ‘01’. These high T values represent logic ‘1’, confirming the NAND gate behavior where the output is ‘0’ only when both inputs are ‘1’, and ‘1’ otherwise.

Table 6. Output logic levels, output power (P_out), normalized transmission (T), and contrast ratio (CR) for the NAND gate using the proposed racetrack and ring resonator design at a wavelength of 1.33 μm. A transmission threshold (T_th) of 0.2 is used to distinguish between logic ‘0’ and logic ‘1’.

Logic Gate	Input Signals			Output Logic		Metrics
	Pin1	Pin2	Pin3 (Clk)	Pout	Pout (mW)	T	CR (dB)
NAND	0	0	1	1	0.5904	0.984	13.80
	1	0	1	1	0.5904	0.984
	0	1	1	1	0.5904	0.984
	1	1	1	0	0.0246	0.041

presents the measured output logic levels, output power (P_out), and normalized transmission (T) for the NAND gate under four input combinations, with Clk signal (P_in3) fixed at logic ‘1’. For input states ‘00’, ‘10’, and ‘01’, the output T remains consistently high at 0.984, with P_out of 0.5904 mW, clearly above the decision threshold (T_th = 0.2), and thus, it is interpreted as logic ‘1’. This behavior is attributed to constructive interference enabled by phase alignment between the inputs and the clock signal. Conversely, when both inputs are ‘11’, destructive interference caused by phase mismatch results in a sharp drop in transmission to 0.041 and output power to 0.0246 mW, representing logic ‘0’. The high CR of 13.80 dB confirms a strong distinction between logic states, validating the NAND gate’s correct operation and robust optical switching performance in photonic logic circuits.

Figure 16 illustrates the measured output T spectra of the NAND gate using the racetrack and ring resonator-based architecture operating at a wavelength of 1.33 μm. The spectral response reflects interference conditions on different input logic combinations. When both inputs are at logic ‘1’ with phase mismatch relative to the Clk signal (Φ₁ = 180°, Φ₂ = 90°, and Φ_Clk = 0°), DI dominates, resulting in a significantly suppressed output transmission of approximately 0.041 (<T_th = 0.2), which corresponds to logic ‘0’. For the remaining input combinations (‘00’, ‘10’, and ‘01’), phase alignment enables CI, leading to strong output transmission peaks near 0.984, all well above T_th, and thus, it is interpreted as logic ‘1’. These distinct transmission levels confirm the expected NAND logic functionality and demonstrate effective phase-based switching with high contrast between logical states.

3.7. XNOR

To implement the XNOR gate functionality, as depicted in Figure 17, two input signals are introduced through P_in1 and P_in2, while a fixed-phase Clk signal is injected through P_in3 with Φ_Clk = 0° (see Figure 1 for the setup). The racetrack and ring resonator configuration governs the interference dynamics at the output port (P_out) based on the relative phase alignment of the input beams. When the input signals have identical phase angles, for example, both are at 0°, CI occurs. This leads to a high output T intensity of approximately 0.886, which surpasses the decision threshold and is interpreted as a logical ‘1’. Conversely, when the input signals possess different phase angles (e.g., Φ₁ = 180°, Φ₂ = 90°, and Φ_Clk = 0°), the phase mismatch induces DI within the resonator. This reduces the output T intensity below the threshold level, resulting in a logical ‘0’ at P_out. This behavior validates the XNOR logic, where the output is ‘1’ only when both inputs are equal—either both ‘0’ or both ‘1’—and ‘0’ when the inputs differ.

Table 7. Output logic levels, output power (P_out), normalized transmission (T), and contrast ratio (CR) for the XNOR gate using the proposed racetrack and ring resonator design at a wavelength of 1.33 μm. A transmission threshold (T_th) of 0.2 is used to distinguish between logic ‘0’ and logic ‘1’.

Logic Gate	Input Signals			Output Logic		Metrics
	Pin1	Pin2	Pin3 (Clk)	Pout	Pout (mW)	T	CR (dB)
XNOR	0	0	1	1	0.5904	0.984	14.67
	1	0	1	0	0.0246	0.041
	0	1	1	0	0.0132	0.022
	1	1	1	1	0.5184	0.864

presents the measured output power (P_out), normalized transmission (T), and contrast ratio (CR) for the XNOR gate with Clk applied at P_in3 (Φ_Clk = 0°) and inputs at P_in1 and P_in2. When both inputs are ‘00’, the output power is 0.5904 mW, with a high transmission of 0.984, producing a logic ‘1’ output. For input combinations ‘10’ and ‘01’, the output power drops sharply to 0.0246 mW and 0.0132 mW, with transmissions of 0.041 and 0.022, respectively, corresponding to logic ‘0’. When both inputs are ‘11’, P_out is slightly lower at 0.5184 mW, with T of 0.864, still representing logic ‘1’. The high CR of 14.67 dB confirms a strong distinction between logic ‘1’ and ‘0’ states, validating the proper XNOR functionality where the output is ‘1’ only when the inputs are equal.

The XNOR output spectra illustrated in Figure 18 showcase the distinct optical responses of the racetrack and ring resonator structure under various input combinations. When both input signals are identical—either ‘00’ or ‘11’—CI occurs due to phase alignment with the Clk signal (Φ_Clk = 0°), resulting in strong spectral peaks centered at approximately 0.984 and 0.864, respectively. These values exceed the threshold (T_th = 0.2), confirming logical ‘1’ at the output. In contrast, when the inputs differ (‘10’ or ‘01’), phase mismatches introduce DI, which significantly suppresses the output spectra to 0.041 and 0.022, both below T_th, corresponding to logical ‘0’. These spectral profiles differentiate between high and low logic levels, affirming the XNOR gate’s correct operation, where the output is ‘1’ only when both inputs are equal.

4. Performance Comparison

The comprehensive comparison of all-optical logic gate (AOLG) implementations presented in

Table 8. Comprehensive comparison of AOLG implementations across various photonic and plasmonic platforms. This table summarizes supported logic operations, waveguide types, material systems, device footprints, data rates, operating wavelengths (λ), performance metrics (CR or ER), type of validation (simulation or experiment), and corresponding references. The proposed design demonstrates a favorable balance of speed and compactness, achieving 47.94 Gb/s within a small footprint, as highlighted.

Logic Gates	Waveguide	Materials	Size (µm2)	Speed (Gb/s)	λ (nm)	Metric (dB)	Exp./Sim.	Ref.
XOR, AND, OR, NOT, NOR, XNOR, NAND	Silicon microrings waveguide	Si/SiO2	1.30 × 1.35	199.80	1550	CR = 12.02–15.85	Sim.	[9]
AND, NAND	Silicon micro-ring resonators	Si/SiO2	5 µm radius	0.310	1550.7	ER ~ 10	Exp.	[12]
AND, NOR, XNOR	Si photonics platform	Si	3 µm long	20	1550	CR > 10	Exp.	[13]
NOT, OR, AND, NOR, NAND, XOR, XNOR	Dielectric–metal–dielectric plasmonic waveguide	Silver/Teflon	-	-	900–1330	ER > 20	Sim.	[15]
AND, XOR, OR, NOT, NAND, NOR, XNOR	PhC waveguides	Si/Air	5.28 × 5.28	976	1550	CR = 5.42–9.59	Sim.	[22]
AND, XOR, XNOR	T-shaped PhC waveguides	Si/Air	8.4 × 5.4	>30,000	1550	CR = 8.29–33.05	Sim.	[23,24,25]
AND, OR	2D PhC design	Si/Air	19.8 × 12.6	>4740	1520	CR = 9.74 and 17.95	Sim.	[26]
NOT, XOR, AND, OR, NOR, NAND, XNOR	Metal slot waveguide	Silver/SiO2	1.5 × 2.36	-	632.8	CR = 6–16	Exp.	[27]
NOT, XOR, AND, OR, NOR, NAND, XNOR	Metal–insulator–metal structures	Air/Silver	5.33 × 0.42	-	632.8	CR = 15	Sim.	[28]
AND, NAND, OR, XOR, NOR, XNOR, NOT	Plasmonic logic gate design	Silver/SiO2	0.25 × 0.25	-	850	CR = 4.14–14.46	Sim.	[29]
AND, OR, NOT, NAND	Inverse design on silicon platforms	Si/SiO2	1.0 × 1.5	-	1300	CR = 0.5–5.79	Sim.	[30]
XOR, AND, OR, NOT, NOR, XNOR, NAND	Silicon racetrack and ring resonator	Si/SiO2	7.24 × 1.5	47.94	1330	CR = 13.09–14.67	Sim.	This work

highlights the diversity of photonic and plasmonic platforms engineered for ultrafast and compact logic operations. These implementations vary significantly in terms of waveguide architecture; material systems; operating wavelengths; and performance metrics such as data rate, footprint, and contrast ratio (CR) or extinction ratio (ER). Silicon microring waveguides [9], for instance, offer a complete set of logic gates at 1550 nm with high simulated CRs (12.02–15.85 dB) and an impressive data rate of 199.8 Gb/s. However, the design footprint (1.30 × 1.35 μm²) is relatively large, and the implementation requires complex coupling strategies. Experimental designs, such as those in [12,13], confirm the practicality of silicon photonics platforms for logic gate realization, but their data rates remain below 20 Gb/s—limiting their applicability for high-speed data processing. Photonic crystal (PhC)-based logic gates provide strong performance in terms of CR and speed [22,23,24,25]. T-shaped PhC waveguides [23,24,25] achieve some of the highest reported data rates (>30,000 Gb/s) and CRs (up to 33.05 dB) in simulation. However, these designs often necessitate larger device areas and intricate geometries, making them less favorable for scalable integration. Similarly, 2D PhC architectures [26] deliver respectable CRs (~9.74–17.95 dB) and high speeds (>4740 Gb/s), but the footprint and fabrication demands remain considerable. In the visible spectrum, plasmonic and metallic waveguide structures provide an alternative with compact footprints and broad spectral coverage. Metal slot waveguides [27], composed of silver/SiO₂ and operating at 632.8 nm, support all logic operations experimentally, with CRs ranging from 6 to 16 dB. Similarly, metal–insulator–metal (MIM) structures [28], based on air/silver, offer a simulated CR of 15 dB for the full logic set. Though these designs benefit from deep subwavelength confinement, they are often limited by intrinsic losses in metallic materials. Plasmonic logic gates [29], designed using silver/SiO₂ at 850 nm, demonstrate CRs from 4.14 to 14.46 dB in simulations for logic gates such as AND, NAND, XOR, and XNOR, combining relatively high CR with wavelength flexibility. Meanwhile, inverse-designed silicon platforms [30], targeting the O-band at 1300 nm for shorter-reach communications and biomedical sensing, support logic operations, including AND, OR, NOT, and NAND, with CRs ranging from 0.5 to 5.79 dB. Despite their lower CRs, the operation at 1300 nm opens new application spaces beyond traditional telecom wavelengths. However, such designs typically rely on complex numerical optimization and advanced nanofabrication techniques, reducing their practicality. In contrast, our proposed design—based on a compact silicon racetrack and microring resonator configuration—operates at 1330 nm and supports a complete set of logic gates (XOR, AND, OR, NOT, NOR, XNOR, and NAND) with CRs between 13.09 and 14.67 dB in simulation. It achieves a moderate-to-high data rate of 47.94 Gb/s within a compact footprint of 7.24 × 1.5 μm², demonstrating a strong trade-off among performance parameters. Compared to many prior designs, our design stands out as follows:

• It achieves higher speed than most experimentally validated photonic gates, without compromising on CR.
• It avoids the metal losses and fabrication complexities associated with plasmonic platforms.
• It is fabrication-friendly, leveraging standard silicon photonic processes (e.g., SOI platforms), unlike inverse-designed or PhC-based devices requiring more exotic patterning.
• The racetrack-coupled microring structure provides enhanced resonant control and mode confinement, ensuring reliable, repeatable logic behavior with minimal design complexity.

Therefore, as highlighted in Table 8, our design delivers a balanced and scalable solution for high-speed, compact, and CMOS-compatible optical logic circuits, offering a competitive edge over many existing photonic and plasmonic approaches.

5. CMOS-Compatible Fabrication and Logic Gate Performance

The proposed AOLGs are based on silicon racetrack and ring resonators, which are highly compatible with standard CMOS photonic fabrication processes, enabling scalable and cost-effective production. These devices can be fabricated on SOI or silicon-on-silica platforms using electron-beam lithography or deep ultraviolet (DUV) photolithography, followed by anisotropic etching methods such as inductively coupled plasma–reactive ion etching (ICP-RIE) [31]. Waveguide widths of 450–500 nm and silicon thicknesses around 220 nm are routinely employed to ensure single-mode operation at the 1.33 μm wavelength. Thermal oxidation or plasma-enhanced chemical vapor deposition (PECVD) is used to deposit the silica upper cladding, while grating couplers or edge couplers enable optical I/O with coupling losses typically between 1 and 3 dB. Xu and Lipson [12] previously demonstrated all-optical logic based on silicon microrings, confirming their practicality for basic logic operations. Vlasov and McNab [32] demonstrated high-Q photonic cavities with compact footprints suitable for integrated photonic circuits, laying the foundation for ultra-compact logic gate elements. The racetrack resonator layout offers enhanced coupling flexibility and broader bandwidth compared to circular microrings. Optimized geometries, as shown by Chen et al. [33], improve the extinction ratio and reduce insertion loss, ensuring effective CI and DI necessary for logic operations. Our design demonstrated CRs ranging from 13.09 to 14.67 dB across all logic functions, indicating sharp resonance control and excellent signal discrimination. More recently, Kita et al. [13] introduced ultrashort, low-loss Ψ gates fabricated on a silicon photonics platform, highlighting the potential for low-energy, high-speed optical computing. Experimental works by Sun et al. [34] confirm the feasibility of subwavelength photonic elements to support high-density optical interconnects operating at data rates above 40 Gb/s. Hybrid photonic–plasmonic designs such as those by Oulton et al. [35] have pushed the limits of light–matter interaction, further validating the potential for compact, fast-switching photonic logic devices. Additionally, Pan et al. [27] proposed metal slot waveguide-based interferometric gates, realizing a full set of logic operations in a highly confined optical field regime, illustrating alternative fabrication schemes. Inverse-designed photonic components introduced by Piggott et al. [36] also offer promising paths toward further miniaturization and performance enhancement. Ultrafast modulation on silicon chips [37] and recent advances in ultra-high-Q silicon nitride resonators [11] suggest that the demonstrated data rate of 47.94 Gb/s in our design is well within reach using existing technologies. A remaining fabrication challenge lies in achieving sub-10 nm precision for critical coupling gaps and maintaining low sidewall roughness; however, this may be overcome shortly through advances in lithography and etching fidelity. These findings, supported by recent experimental and design advances, confirm the fabrication feasibility and functional robustness of our waveguide design for next-generation ultrafast photonic computing platforms.

6. Conclusions

In this study, we presented a comprehensive design and simulation of ALOGs based on silicon racetrack and ring resonators operating at the 1.33 μm O-band. By leveraging resonance effects in compact photonic structures, our system successfully performs all fundamental logic functions, including XOR, AND, OR, NOT, NOR, NAND, and XNOR, with contrast ratios ranging from 13.09 to 14.67 dB. The chosen operating wavelength not only supports short-distance optical communication but also falls within the biological transparency window, suggesting broader application potential in both data transmission and biomedical sensing. The proposed device demonstrates a data rate of 47.94 Gb/s, matching or exceeding those reported in similar silicon-based logic systems, while maintaining compatibility with standard CMOS fabrication processes. Compared with alternative approaches such as photonic crystal waveguides, plasmonic structures, and inverse-designed geometries (as summarized in Table 8), our design offers a compelling trade-off between performance, integration simplicity, and functional completeness. These features make the design a strong candidate for scalable, high-speed photonic circuits. While fabrication challenges such as achieving sub-10 nm coupling gaps and minimizing sidewall roughness persist, they are expected to be overcome with ongoing advancements in nanofabrication techniques. Overall, this work confirms the viability of using microring-based silicon photonics for implementing efficient, compact, and high-speed ALOGs, paving the way for their adoption in future optical computing and communication platforms.