High-Gain Coupled-Inductor Boost Converters Using Voltage-Doubling and Continuous Input Current Design

Abstract

This paper proposes a family of high-efficiency DC-DC boost converters employing voltage-doubling coupled-inductor technology with a low component count. By varying the homonymous winding connections of the coupled inductor, three topologies are developed: parallel (PWCDVD-CLBC), series (SWCDVD-CLBC), and flipped-parallel (FPWCDVD-CLBC). These converters achieve high-voltage gain, continuous input current, and low-voltage stress across components. The PWCDVD-CLBC and FPWCDVD-CLBC configurations exhibit voltage gains proportional to the turn ratio, while the SWCDVD-CLBC shows an inverse relation, enabling reduced turn ratios. Detailed operational principles, mathematical analysis, and performance advantages are presented. A comparative evaluation demonstrates a higher voltage gain, realizes continuous input current, and has lower voltage stresses. The experimental results validate the theoretical analysis and confirm the feasibility and efficiency of the proposed designs.

1. Introduction

Wireless charging systems have been extensively applied to electric vehicle batteries due to their contactless nature, safety, and convenience. Various DC/DC converter topologies have been developed to meet the demands of high-voltage gain and improved efficiency in renewable energy and electric vehicle applications [1]. However, conventional boost converters suffer from limited voltage gain and high-voltage stress on switching devices, which restricts their applicability in high step-up scenarios.

To address these limitations, Z-source converters (ZSCs) and Y-source were introduced, offering an impedance network capable of boosting voltage [2,3,4]. However, ZSCs typically suffer from discontinuous input current and limited gain, which has led to the development of quasi-Z-source (QZSC) and enhanced Z-source networks [5,6,7,8]. While these offer better performance, they often involve increased component count and complexity.

By introducing switched-inductor cells to realize four inductors’ parallel charging and serial discharging, the converter [9] largely improves boost ability. By adding switched-impedance networks, an enhanced Z-source structure is presented in [10] to increase boost ability, which results in larger device counts and system losses. Therefore, converters based on coupled-inductor boost technology are presented for a higher voltage gain but utilizing a lesser component count. Magnetically coupled structures have gained attention due to their ability to combine multiple inductors and achieve a higher voltage gain. The Δ-source converter [11] realizes high-voltage gain by utilizing a three-winding magnetically structured, two capacitors, and two diodes. Different from converters [11], Γ-source and flipped Γ-source converters [12,13] have an inversely proportional relation; namely, a low turn ratio can help produce a high boost ability. A Y-source converter with a three-winding coupled-inductor cell is reported in [14], which has more freedom in winding matches.

Figure 1 shows the topologies of the Δ-source, Γ-source, and Y-source converters. The Δ-source, Γ-source, and Y-source converters utilize multi-winding coupled-inductor cells to achieve enhanced performance [11,12,13,14], though many of them still suffer from discontinuous input current and parasitic-induced losses. Subsequently, a three-winding Π-source converter [15] realizes a stronger boost ability, but its voltage gain is heavily affected by the parasitic resistances on passive components and switching devices. Although the converters above enhance the output performance of systems, input currents are discontinuous, which is not beneficial to the input power source, and is sensitive to passive component parasitics.

Figure 1. Δ-source, Γ-source, and Y-source converters. (* represents the homonymous end of the coupling inductance).

Through varying the charging and discharging paths of the Z-source converter, quasi-Z-source converters (QZSCs) [5] realize the continuous input current. Subsequently, enhanced QZSCs [6,7,8] are reported to produce a higher voltage gain by introducing multiple parallel charging paths. Next, some high-performance coupled-inductor converters, such as the T-source [16], LCCT-Z-source [17], quasi-Y-source [18], modified-Y-source [19], quasi-Γ-source [20], and switched-coupled-inductor converters [21], are presented to further optimize the topology performance. Figure 2 shows the topologies of the switched-inductor and the quasi-switched-inductor converters. However, these converters use multiple diodes, one individual inductor, one coupled-inductor cell, and two capacitors, which will increase system losses to a great degree. Quasi-switched-boost impedance networks are discussed in references [22,23,24,25,26] and have been proposed to further improve gain and continuity of the input current; however, these approaches often introduce multiple diodes, additional switches, and complex control requirements, thereby increasing overall system loss and design costs. The corresponding comparison is shown in Table 1.

Figure 2. Switched-inductor converter and quasi-switched-inductor converter.

Table 1. Comparison table of converters.

Topology	G	Component Count	Input Current
Z-source converter	${\displaystyle \frac{1}{1-2D}}$	4	Discontinuous
Quasi-switched boost converter	${\displaystyle \frac{1}{1-3D}}$	11	Continuous
Modified-Y-source network	${\displaystyle \frac{1+KD}{1-D}}$	12	Continuous
Δ-Source network	${\displaystyle \frac{1}{1-K_{△}D}}$	9	Discontinuous
Y-source impedance network	${\displaystyle \frac{1}{1-K_{Y}D}}$	8	Discontinuous
Extended Z-source	${\displaystyle \frac{1+KD}{1-\left(1+n_{TZ}\right)D}}$	10	Discontinuous
Π-source impedance network	${\displaystyle \frac{1}{1-K_{\mathrm{\Pi }}D}}$	7	Discontinuous
extended boost trans-Z-source inverter	${\displaystyle \frac{1}{(1-2D){(1-D)}^2}}$	9	Continuous
Switched-inductor-Z-source	${\displaystyle \frac{1+D}{1-3D}}$	13	Continuous
L-Z-source inverter	${\displaystyle \frac{1+D}{1-D}}$	5	Continuous
Trans-switched boost inverters	${\displaystyle \frac{1+n_{S}D}{1-\left(2+n_S\right)D}}$	6	Discontinuous
Quasi-Y-source inverter	${\displaystyle \frac{1}{1-\delta D}}$	7	Continuous
LCCT Z-source	${\displaystyle \frac{m+1}{2-2\left(1+\frac{n_2}{n_3}\right)D}}$	8	Continuous
Improved trans-Z-source inverter	${\displaystyle \frac{1}{1-\left(2+n\right)D}}$	6	Continuous
Three-winding switched-coupled inductor (PSCL)	${\displaystyle \frac{\frac{1+n_1}{n_1}}{1-\left(1+\frac{1+n_1+n_2}{n_1}\right)D}}$	9	Continuous

In summary, there remains a need for converter topologies that simultaneously achieve a high-voltage gain, continuous input current, reduced component count, and low-voltage stress. In response, this paper introduces a novel family of voltage-doubling coupled-inductor boost converters with simplified structures and enhanced performance, addressing the limitations found in prior designs. By utilizing different winding homonymous end connections of coupled-inductor cells, three converters are formed and have these performance advantages at the same time. Regarding some differences for the proposed topologies, the voltage gain and turn ratio of the PWCDVD-CLBC and FPWCDVD-CLBC have proportional relations, and yet the SWCDVD-CLBC has inversely proportional relations.

2. Proposed Topologies and Analysis

2.1. Proposed Topologies

Figure 3 provides the topology of the ZSC. It can be seen that the ZSC can realize a boosted performance by the X-source impedance network. When the switch is on, two capacitors charge two inductors. When the switch is off, the two inductors and the input source discharge to loads and capacitors. However, the input source is lower than the capacitor voltage and results in discontinuous input current when the switch is on.

Figure 3. Z-source converter.

Inspired by the operation principle of the ZSC and combining magnetically boost technology, a family of voltage-double coupled-inductor boost DC/DC converters is proposed in Figure 4. The proposed converters directly utilize the input source to charge the coupled-inductor cell and construct a voltage-double circuit path with diode-winding-capacitor technology. The proposed three converters realize a continuous input current, have a lower component count, and obtain a higher boost ability. Different winding homonymous end connections form different topologies, respectively, called PWCDVD-CLBC in Figure 4a, FPWCDVD-CLBC in Figure 4b, and SWCDVD-CLBC in Figure 4c. The voltage gain and turn ratio of the PWCDVD-CLBC and FPWCDVD-CLBC exhibit a proportional relation, and yet the SWCDVD-CLBC has an inversely proportional relation. Therefore, the proposed three converters must produce different outcomes. (* represents the homonymous end of the coupling inductance).

Figure 4. Proposed converters: (a) PWCDVD-CLBC, (b) FPWCDVD-CLBC, and (c) SWCDVD-CLBC.

In this section, the operational status of the three proposed converters will be analyzed individually. Figure 5 shows the theoretical waveforms of the related components in one cycle of the topology in Figure 4, and Figure 5 shows the equivalent circuits when the switch is on or off.

Figure 5. Theoretical waveforms: (a) PWCDVD-CLBC, (b) FPWCDVD-CLBC, and (c) SWCDVD-CLBC. (V_gs is the switch pulse trigger signal, V_N1/I_N1 is the primary side of the coupling inductance voltage/current, V_N2/I_N2 is the secondary side of the coupling inductance voltage/current, V_D1/I_D1 is the diode voltage/current, and V_Do/I_Do is the diode voltage/current.).

2.1.1. PWCDVD-CLBC

As described in Figure 6a, the input source supplies power for the windings N₁, magnetizing inductance L_M, and the leakage inductance L_k by diode D₁ and switch S₁ when the switch is on. Meanwhile, wind N₂ charges the capacitor C₁ through diode D₁. As described in Figure 6b, the input source V_in, the whole coupled-inductor structure, and capacitor C₁ supply the power for the loads when switch S₁ is off.

Figure 6. Equivalent circuits of different operation states: (a,c,e) switch is on and (b,d,f) switch is off. (* represents the homonymous end of the coupling inductance).

2.1.2. FPWCDVD-CLBC

As described in Figure 6c, the input source supplies power for windings N₁, magnetizing inductance L_M, and leakage inductance L_k by diode D₁ and switch S₁ when the switch is on. Meanwhile, the whole coupled-inductor structure charges capacitor C₁ through diode D₁. As described in Figure 6d, the input source V_in, winding N_2, and capacitor C₁ supply the power for the loads when switch S₁ is off. The relevant parameters and symbols are shown in Table 2.

Table 2. Parameters and symbols.

Symbol	Description	Unit
Vin	Input voltage	V
Co	Output capacitor voltage	V
D1	Diode	-
LK	Leakage inductance	H
LM	Magnetizing inductance	H
C1	Intermediate capacitor	F
R	Load resistance	Ω
N1/2	Primary/secondary edge	-
S1	Switch	-

2.1.3. SWCDVD-CLBC

As described in Figure 6e, the input source supplies power for the whole coupled-inductor structure through the diode D₁ and switch S₁ when the switch is on. Meanwhile, the wind N₁ and leakage inductance L_k thus charge capacitor C₁ through diode D₁. As described in Figure 6f, the input source V_in, winding N_2, and capacitor C₁ supply the power for the loads when switch S₁ is off.

In summary, the proposed converters can achieve continuous input current. Additionally, by forming a voltage-doubling circuit, these topologies can significantly enhance the voltage gain with a low component count.

2.2. Math Derivation and Performance Analysis

The detailed math derivation and performance analysis will be given out as follows. The following definitions are given out. Leakage inductance L_k and magnetizing inductance L_M have the following expressions:

$$g=L_{\mathrm{M}}/(L_{\mathrm{M}}+L_{\mathrm{k}})$$

(1)

where V_in is the input voltage, D is the shoot-through duty ratio, n is the turn ratio of the coupling inductance, V_C1 is the voltage of capacitor C₁, and V_o is the output voltage. V_N1S, V_N1N, V_N2S, V_N2N, V_LkS, and V_LkN are, respectively, the voltages of the windings (N₁ and N₂) and leakage inductance when the switch is on or off.

2.2.1. PWCDVD-CLBC

When the switch is on, the following theoretical relations can be obtained.

$$V_{\mathrm{in}}-V_{L\mathrm{k}S}-V_{N1S}=0$$

(2)

$$V_{N2S}=n{V}_{N1S}$$

(3)

$$V_{C1}=V_{N2S}$$

(4)

When the switch is off, the following theoretical relations can be obtained.

$$V_{\mathrm{in}}-V_{L\mathrm{k}N}-V_{N1N}-V_{N2N}+V_{C1}=V_{\mathrm{o}}$$

(5)

$$V_{N2N}=n{V}_{N1N}=ng{V}_{L\mathrm{k}N}/(1-g)$$

(6)

$$V_{D1}=V_{C1}-V_{N2N}$$

(7)

Therefore, the output voltage is provided as follows.

$$V_{\mathrm{o}}={\displaystyle \frac{(ng+1)V_{in}}{(1-D)}}$$

(8)

When g = 1, the voltage gain and voltage stresses of diode D₁ and capacitor C₁ are provided as follows.

$$\left\{\begin{array}{l}G={\displaystyle \frac{n+1}{1-D}}\\ V_{C1}=n{V}_{\mathrm{in}}\\ V_{D1}={\displaystyle \frac{n{V}_{\mathrm{in}}}{1-D}}\end{array}\right.$$

(9)

2.2.2. FPWCDVD-CLBC

When the switch is on, the following theoretical relations can be obtained.

$$V_{\mathrm{in}}-V_{N1S}-V_{L\mathrm{k}S}=0$$

(10)

$$V_{N2S}=n{V}_{N1S}$$

(11)

$$V_{C1}=V_{N2S}-V_{N1S}-V_{L\mathrm{k}S}$$

(12)

When the switch is off, the following theoretical relations can be obtained.

$$V_{\mathrm{in}}+V_{C1}-V_{N2N}=V_{\mathrm{o}}$$

(13)

$$V_{N2N}=n{V}_{N1N}=n{V}_{L\mathrm{k}S}g/(1-g)$$

(14)

Therefore, the output voltage is provided as follows.

$$V_{\mathrm{o}}={\displaystyle \frac{Dn{g}^2+(1-D)(ng+g-1)}{(1-D)g}}{V}_{\mathrm{in}}$$

(15)

When g = 1, the voltage gain and voltage stresses of diode D₁ and capacitor C₁ are provided as follows.

$$\left\{\begin{array}{l}G={\displaystyle \frac{n}{1-D}}\\ V_{C1}=(n-1)V_{\mathrm{in}}\\ V_{D1}={\displaystyle \frac{(n-1)V_{\mathrm{in}}}{1-D}}\end{array}\right.$$

(16)

2.2.3. SWCDVC-CLBC

When the switch is on, the following theoretical relations can be obtained.

$$V_{\mathrm{in}}-V_{N2S}+V_{N1S}+V_{L\mathrm{k}S}=0$$

(17)

$$V_{N2S}=n{V}_{N1S}$$

(18)

$$V_{C1}=V_{N1S}$$

(19)

When the switch is off, the following theoretical relations can be obtained.

$$V_{\mathrm{in}}+V_{C1}-V_{N2N}-V_{L\mathrm{kN}}=V_{\mathrm{o}}$$

(20)

$$V_{N2N}=n{V}_{N1N}=n{V}_{L\mathrm{k}N}g/(1-g)$$

(21)

$$V_{D1}=V_{C1}-V_{N1N}$$

(22)

Therefore, the output voltage is given out.

$$V_{\mathrm{o}}={\displaystyle \frac{V_{\mathrm{in}}n(1-D+Dg)}{(1-2g+n)(1-D)}}$$

(23)

When g = 1, the voltage gain and voltage stresses of diode D₁ and capacitor C₁ are provided as follows.

$$\left\{\begin{array}{l}G={\displaystyle \frac{n}{(n-1)(1-D)}}\\ V_{C1}={\displaystyle \frac{V_{\mathrm{in}}}{n-1}}\\ V_{D1}={\displaystyle \frac{V_{\mathrm{in}}}{(n-1)(1-D)}}\end{array}\right.$$

(24)

Figure 7a,b illustrates the voltage gain curves that consider various coupling coefficients and turn ratios for the proposed three topologies. As described in Figure 7a,b, the voltage gain can be regulated by varying the switch-duty ratio, and it rises as the coupling coefficient rises. Voltage gains of the PWCDVD-CLBC and FPWCDVD-CLBC are directly proportional to the turn ratio, yet the SWCDVD-CLBC is inversely proportional to the turn ratio. Figure 7c,d, respectively, describes the normalized voltage stresses of capacitor C₁ and diode D₁ under various turn ratios for the proposed three converters. As described in Figure 7c,d, the normalized voltage stresses of capacitor C₁ and diode D₁ of the PWCDVD-CLBC and FPWCDVD-CLBC have a proportional relation with the turn ratio, and then the normalized voltage stresses of capacitor C₁ and diode D₁ of the SWCDVD-CLBC have an inversely proportional relation with the turn ratio.

Figure 7. Performance analysis: (a) voltage gain with various coupling coefficients, (b) voltage gain with various turn ratios, (c) diode voltage, and (d) capacitor voltage.

2.3. Parameter Design and Performance Comparison

The following part shows the design of the coupled-inductor cell and capacitors for the proposed three topologies. Inductor values of primary and secondary winding are typically designed based on the principle that input power equals output power.

$$P_{\mathrm{in}}=V_{\mathrm{in}}{\overline{i}}_{\mathrm{in}}=G{V}_{\mathrm{in}}{\overline{i}}_{\mathrm{out}}=P_{\mathrm{out}}$$

(25)

where i_in is the average input current, the equation for primary and secondary windings, input voltage, shoot-through duty ratio, and switch frequency is given. i_out is the average output current; this is the equation for voltage gain and loads.

The voltage fluctuation of the capacitors is mainly caused by the charging and discharging currents.

$$C{\displaystyle \frac{dV}{dt}}=i$$

(26)

where C is the capacitor value, i is the current across the capacitor C, and dV is the voltage fluctuation of the capacitor in this interval dt.

The coupled-inductor cell and capacitors of the proposed three topologies can be designed separately, as follows.

2.3.1. PWCDVD-CLBC

According to the operation states in Figure 6a,b, i_in and i_out are provided as follows.

$$\left\{\begin{array}{l}{\overline{i}}_{\mathrm{in}}={\displaystyle \frac{V_{\mathrm{in}}D{T}_s(1-D+nD)}{2n{L}_{N1}}}\\ {\overline{i}}_{\mathrm{o}}={\displaystyle \frac{V_{\mathrm{in}}(1+n)}{(1-D)R}}\end{array}\right.$$

(27)

where R is the load, and T_s is the switch cycle. Therefore, the inductor values of the primary and secondary windings are provided as follows.

$$L_{N1}={\displaystyle \frac{D{(1-D)}^2(1-D+nD)R{T}_s}{2{(1+n)}^{2}n}}$$

(28)

$$L_{N2}={\displaystyle \frac{nD{(1-D)}^2(1-D+nD)R{T}_s}{2{(1+n)}^2}}$$

(29)

The capacitor C₁ is designed according to Equation (30).

$${\displaystyle \frac{V_{\mathrm{in}}{D}^2{T}_s^2}{n{L}_{N1}\mathrm{\Delta }{V}_{C1}}}\le C_1$$

(30)

where C₁ is the value of capacitor C₁, and $\mathrm{\Delta }{v}_{C_1}$ is the permitted voltage ripple of capacitors C₁.

2.3.2. FPWCDVD-CLBC

According to the operation states in Figure 6c,d, ${\overline{i}}_{\mathrm{in}}$ and ${\overline{i}}_{\mathrm{out}}$ are provided as follows.

$$\left\{\begin{array}{l}{\overline{i}}_{\mathrm{in}}={\displaystyle \frac{V_{\mathrm{in}}{D}^2{T}_s}{2L_{N1}}}\\ {\overline{i}}_{\mathrm{o}}={\displaystyle \frac{n{V}_{\mathrm{in}}}{(1-D)R}}\end{array}\right.$$

(31)

Therefore, the inductor values of the primary and secondary windings are provided as follows.

$$L_{N1}={\displaystyle \frac{D^2{T}_s{(1-D)}^{2}R}{2n^2}}$$

(32)

$$L_{N2}={\displaystyle \frac{D^2{T}_s{(1-D)}^{2}R}{2}}$$

(33)

The capacitor C₁ is designed according to the Equation (34).

$${\displaystyle \frac{V_{\mathrm{in}}{D}^2{T}_s^2}{n{L}_{N1}\mathrm{\Delta }{V}_{C1}}}\le C_1$$

(34)

2.3.3. SWCDVD-CLBC

According to the operation states in Figure 6e,f, ${\overline{i}}_{\mathrm{in}}$ and ${\overline{i}}_{\mathrm{out}}$ are provided as follows.

$$\left\{\begin{array}{l}{\overline{i}}_{\mathrm{in}}={\displaystyle \frac{V_{\mathrm{in}}D{T}_s(n-1+D)}{2(n-1)n^2{L}_{N1}}}\\ {\overline{i}}_{\mathrm{o}}={\displaystyle \frac{n{V}_{\mathrm{in}}}{(n-1)(1-D)R}}\end{array}\right.$$

(35)

Therefore, the inductor values of the primary and secondary windings are provided as follows.

$$L_{N1}={\displaystyle \frac{D{T}_s(n-1+D)(n-1){(1-D)}^{2}R}{2n^4}}$$

(36)

$$L_{N1}={\displaystyle \frac{D{T}_s(n-1+D)(n-1){(1-D)}^{2}R}{2n^2}}$$

(37)

The capacitor C₁ is designed according to the Equation (38).

$${\displaystyle \frac{V_{\mathrm{in}}{D}^2{T}_s^2}{(n-1)L_{N1}\mathrm{\Delta }{V}_{C1}}}\le C_1$$

(38)

2.4. Comparative Analysis

A comparative analysis was performed among the Δ-source [11], modified-Y-source [19], high-gain quasi-switched [24], and the proposed three converters. The voltage gain, maximum capacitor voltage, maximum diode voltage, shoot-through peak current, component count, and input current state of the converters above are listed in Table 3.

Table 3. Parameter comparisons.

Parameters	Δ-Source Network [11]	Modified-Y-Source Network [19]	Quasi-Switched Network [24]	PWCDVD-CLBC	FPWCDVD-CLBC	SWCDVD-CLBC
G	${\displaystyle \frac{1}{1-K_{△}D}}$	${\displaystyle \frac{1+KD}{1-D}}$	${\displaystyle \frac{1}{1-3D}}$	${\displaystyle \frac{n+1}{1-D}}$	${\displaystyle \frac{n}{1-D}}$	${\displaystyle \frac{n}{\left(n-1\right)\left(1-D\right)}}$
VC-max	${\displaystyle \frac{\left(1-D\right)V_{\mathrm{in}}}{1-K_{△}D}}$	${\displaystyle \frac{\left(1+KD-D\right)V\mathrm{in}}{1-D}}$	${\displaystyle \frac{V_{\mathrm{in}}}{1-3D}}$	$n{V}_{\mathrm{in}}$	$\left(n-1\right)V_{\mathrm{in}}$	${\displaystyle \frac{V_{\mathrm{in}}}{n-1}}$
VD-max	${\displaystyle \frac{\left(K_{△}-1\right)V_{\mathrm{in}}}{1-K_{△}D}}$	${\displaystyle \frac{\left(K+G\right)V_{\mathrm{in}}}{\left(1+K\right)}}$	${\displaystyle \frac{V_{\mathrm{in}}}{1-3D}}$	${\displaystyle \frac{n{V}_{\mathrm{in}}}{1-D}}$	${\displaystyle \frac{\left(n-1\right)V_{\mathrm{in}}}{1-D}}$	${\displaystyle \frac{V_{\mathrm{in}}}{\left(n-1\right)\left(1-D\right)}}$
Shoot-through peak current	${\displaystyle \frac{\left(1-D\right)K_{△}D{T}_{\mathrm{s}}{V}_{\mathrm{in}}}{\left(1-K_{△}D\right)L_{\mathrm{m}}}}$	${\displaystyle \frac{\left(2KG-K+1\right)D{T}_s{V}_{\mathrm{in}}}{\left(\frac{N_3}{N_2}-1\right)L_{N2}}}$	${\displaystyle \frac{\left(3-3D\right)D{T}_{\mathrm{s}}{V}_{\mathrm{in}}}{\left(1-3D\right)L_1}}$	${\displaystyle \frac{D{T}_s{V}_{\mathrm{in}}}{L_{N1}}}$	${\displaystyle \frac{D{T}_s{V}_{\mathrm{in}}}{L_{N1}}}$	${\displaystyle \frac{D{T}_s{V}_{\mathrm{in}}}{\left(n-1\right)L_{N1}}}$
Component count	9	12	11	5	5	5
Input current	Discontinuous	Continuous	Continuous	Continuous	Continuous	Continuous
Cost	Medium	High	Medium	Low	Low	Low

The proposed converters use a lower component count than other converters [11,19,24]. As we can see, their input currents are continuous. In addition, the proposed impedance structure can achieve a high boost effect with a small switch-duty ratio. The specific parameters for comparison are shown below.

The input current of the converter [11] is discontinuous. Still, the converter [19] is continuous, and the converter [24] and the proposed converters are also continuous. The proposed topologies utilize the fewest components while maintaining continuous input current, which is in contrast to other converters [11,19,24].

Parameter comparisons among the converters [11,19,24] and the proposed converters are made. The comparison of voltage gain is shown in Figure 8a. Figure 8a demonstrates that the proposed three converters achieve a higher voltage gain. Voltage gains of the proposed PWCDVD-CLBC and FPWCDVD-CLBC have a positively proportional relationship with the turn ratio, yet the proposed SWCDVD-CLBC has an inversely proportional relationship.

Figure 8. Comparative curves of boost ability, device voltages, and current: (a) voltage gain, (b) capacitors, (c) diode voltage, and (d) shoot-through currents [11,19,24].

Figure 8b provides comparative curves of normalized capacitor voltage stress. The proposed three converters have the lowest voltage stress across capacitors when the turn ratio is 2, compared to other converters [11,19,24]. When the turn ratio is 1.2, the capacitor voltage of the proposed SWCDVD-CLBC is lower than the converters [24] and higher than converters [11,19]. However, as the voltage gain gradually increases, when the voltage gain reaches 7, we can see that the SWCDVD-CLBC is lower than converters [19,24].

Figure 8c illustrates the comparative curves of the normalized diode voltage. It is clear that the diode voltage stresses for the proposed converters are lower than those of converters [11,19,24]. The comparison of normalized shoot-through current is shown in Figure 8d. The proposed impedance networks have a lower shoot-through current than those of the impedance networks [11,19,24].

Based on the above comparison, the three proposed impedance networks can achieve a higher voltage gain with fewer components while exhibiting lower voltage stress in a smaller range through the switch-duty ratio, thereby reducing energy loss.

2.5. Voltage Gain Analysis

2.5.1. PWCDVD-CLBC

The influence of inductance resistance on the voltage gain of the PWCDVD-CLBC is analyzed as follows in Figure 9. R_N1 and R_N2 represent the conduction resistances of the windings (N₁ and N₂, * represents the homonymous end of the coupling inductance).

Figure 9. Simplified analysis of PWCDVD-CLBC inductance resistance.

From the above circuit diagram analysis, we have:

$$\begin{array}{c}{V}_{in}-{\overline{i}}_{in}{R}_{N1}-V_{N1S}=0\\ V_{N2S}=n{V}_{N1S}\\ V_{C1}+{\overline{i}}_{in}{R}_{N2}-V_{N2S}=0\end{array}$$

(39)

$$\begin{array}{c}{V}_{in}-{\overline{i}}_{in}\left(R_{N1}+R_{N2}\right)+V_{C1}-V_{N1N}-V_{N2N}=V_O\\ V_{N2N}=n{V}_{N1N}\end{array}$$

(40)

Due to the existence of inductance resistance, there is a voltage drop in the actual value of V_N1. At the same time, there is also a voltage drop between V_N2 and V_C1 due to electromagnetic induction. Therefore, from this, we obtain the following image in Figure 10.

Figure 10. Influence of inductance resistance on PWCDVD-CLBC voltage gain.

2.5.2. FPWCDVD-CLBC

The influence of inductance resistance on the voltage gain of the FPWCDVD-CLBC is analyzed as follows in Figure 11. R_N1 and R_N2 represent the conduction resistances of the windings (N₁ and N₂, * represents the homonymous end of the coupling inductance).

Figure 11. Simplified analysis of FPWCDVD-CLBC inductance resistance.

From the above circuit diagram analysis, we have:

$$\begin{array}{c}{V}_{in}-{\overline{i}}_{in}{R}_{N1}-V_{N1S}=0\\ V_{N2S}=n{V}_{N1S}\\ V_{C1}=V_{N2S}-{\overline{i}}_{in}\left(R_{N1}+R_{N2}\right)-V_{N1S}\end{array}$$

(41)

$$\begin{array}{c}{V}_{\mathrm{in}}+V_{C1}-V_{N2N}-{\overline{i}}_{in}{R}_{N2}=V_{\mathrm{o}}\\ V_{N2N}=n{V}_{N1N}\end{array}$$

(42)

Due to the existence of inductance resistance, when the switch is on, because of the inductive impedance on N₁, the current of N₁ decreases. The induced electromotive force of N₂ is generated due to electromagnetic induction. At the same time, the energy stored in C₁ is reduced due to the impedance of N₂, resulting in a decrease in voltage gain. The simulation is shown in Figure 12.

Figure 12. Influence of inductance resistance on FPWCDVD-CLBC voltage gain.

2.5.3. SWCDVD-CLBC

The influence of inductance resistance on the voltage gain of the SWCDVD-CLBC is analyzed as follows in Figure 13. R_N1 and R_N2 represent the conduction resistances of the windings (N₁ and N₂, * represents the homonymous end of the coupling inductance).

Figure 13. Simplified analysis of SWCDVD-CLBC inductance resistance.

From the above circuit diagram analysis, we have:

$$\begin{array}{c}{V}_{\mathrm{in}}-V_{N2S}+V_{N1S}-i_{N1}{R}_{N1}-i_{N2}{R}_{N2}=0\\ V_{N2S}=n{V}_{N1S}\\ V_{C1}=V_{N1S}-i_{N1}{R}_{N1}\end{array}$$

(43)

$$\begin{array}{c}{V}_{\mathrm{in}}+V_{C1}-V_{N2N}-i_{\mathrm{N}2}{R}_{N2}=V_{\mathrm{o}}\\ V_{N2N}=n{V}_{N1N}\end{array}$$

(44)

When the switch is on, due to the existence of inductance resistance, the inductive impedance on L_N1 and L_N2 will consume some energy, resulting in a voltage drop. At the same time, when the switch is off—because the inductance impedance on N₂ causes the current to drop—the stored energy of the C₁ capacitor will drop, and then the voltage gain will drop. The simulation is shown in Figure 14.

Figure 14. Influence of inductance resistance on SWCDVD-CLBC voltage gain.

2.6. Efficiency Calculation

Loss models for the proposed three converters are, respectively, described in Figure 15. The relevant efficiency calculation is given as follows. R_N1, R_N2, and R_C1 represent the conduction resistances of the windings (N₁ and N₂) and capacitor C₁. V_SD represents the conduction voltage drop of diode D₁ and switch S₁.

Figure 15. Loss models for proposed converters: (a,b) PWCDVD-CLBC, (c,d) FPWCDVD-CLBC, and (e,f) SWCDVD-CLBC. (* represents the homonymous end of the coupling inductance).

2.6.1. PWCDVD-CLBC

The losses of the capacitor C₁, switch S₁, diode D₁, and coupled-inductor cell are provided as follows.

$$P_{C-loss}=I_{C1}^2{R}_{C1}={\displaystyle \frac{V_{\mathrm{in}}^2{D}^2{T}_s^2{[1-(n+1)D]}^2{R}_{C1}}{n^2{L}_{N1}^2}}$$

(45)

$$P_{S-loss}=I_S{V}_{SD}={\displaystyle \frac{D^2{T}_s{V}_{\mathrm{in}}{V}_{SD}}{2L_{N1}}}$$

(46)

$$P_{D-loss}=I_{D1 }{V}_{SD}={\displaystyle \frac{V_{\mathrm{in}}D{T}_s(1-D+nD)V_{SD}}{2n{L}_{N1}}}$$

(47)

$$\begin{array}{l}{P}_{CL-loss}=I_{N1}^2{R}_{N1}+I_{N2 }^2{R}_{N2}\\ ={\displaystyle \frac{V_{\mathrm{in}}^2{D}^2{T}_s^2[{(1-D+nD)}^2{R}_{N1}+4{(1-nD-D)}^2{R}_{N2}]}{4n^2{L}_{N1}^2}}\end{array}$$

(48)

Therefore, efficiency is provided as follows.

$$\eta ={\displaystyle \frac{P_{\mathrm{in}}-P_{C-loss}-P_{S-loss}-P_{D-loss}-P_{CL-loss}}{P_{\mathrm{in}}}}$$

(49)

where P_in is input power, calculated as follows.

$$P_{\mathrm{in}}={\displaystyle \frac{V_{\mathrm{in}}^{2}D{T}_s(1-D+nD)}{2n{L}_{N1}}}$$

(50)

2.6.2. FPWCDVD-CLBC

The losses of the capacitor C₁, switch S₁, diode D₁, and coupled-inductor cell are provided as follows.

$$P_{C-loss}=I_{C1}^2{R}_{C1}={\displaystyle \frac{V_{\mathrm{in}}^2{D}^4{T}_s^2{R}_{C1}}{L_{N1}^2}}$$

(51)

$$P_{S-loss}=I_S{V}_{SD}={\displaystyle \frac{V_{\mathrm{in}}{D}^2{T}_s{V}_{SD}}{2L_{N1}}}$$

(52)

$$P_{D-loss}=I_{D1 }{V}_{SD}={\displaystyle \frac{V_{\mathrm{in}}{D}^2{T}_s{V}_{SD}}{2L_{N1}}}$$

(53)

$$P_{CL-loss}=I_{N1}^2{R}_{N1}+I_{N2 }^2{R}_{N2}={\displaystyle \frac{V_{\mathrm{in}}^2{D}^4{T}_s^2(R_{N1}+4R_{N2})}{4L_{N1}^2}}$$

(54)

Therefore, efficiency is provided as follows.

$$\eta ={\displaystyle \frac{P_{\mathrm{in}}-P_{C-loss}-P_{S-loss}-P_{D-loss}-P_{CL-loss}}{P_{\mathrm{in}}}}$$

(55)

where P_in is input power, calculated as follows.

$$P_{\mathrm{in}}={\displaystyle \frac{V_{\mathrm{in}}^2{D}^2{T}_s}{2L_{N1}}}$$

(56)

2.6.3. SWCDVD-CLBC

The losses of the capacitor C₁, switch S₁, diode D₁, and coupled-inductor cell are provided as follows.

$$P_{C-loss}=I_{C1}^2{R}_{C1}={\displaystyle \frac{V_{\mathrm{in}}^2{D}^2{T}_s^2{(n-1)}^2{(1-D)}^2{R}_{C1}}{{(n-1)}^2{n}^4{L}_{N1}^2}}$$

(57)

$$P_{S-loss}=I_S{V}_{SD}={\displaystyle \frac{D^2{T}_s{V}_{\mathrm{in}}{V}_{SD}}{2(n-1)L_{N1}}}$$

(58)

$$P_{D-loss}=I_{D1 }{V}_{SD}={\displaystyle \frac{V_{\mathrm{in}}D{T}_s(n-1+D)V_{SD}}{2(n-1)n^2{L}_{N1}}}$$

(59)

$$P_{CL-loss}=I_{N1}^2{R}_{N1}+I_{N2 }^2{R}_{N2}={\displaystyle \frac{V_{\mathrm{in}}^2{D}^2{T}_s^2{(n-1+D)}^2(R_{N1}+R_{N2})}{4(n-1)n^4{L}_{N1}^2}}$$

(60)

Therefore, efficiency is provided as follows.

$$\eta ={\displaystyle \frac{P_{\mathrm{in}}-P_{C-loss}-P_{S-loss}-P_{D-loss}-P_{CL-loss}}{P_{\mathrm{in}}}}$$

(61)

where P_in is input power, calculated as follows.

$$P_{\mathrm{in}}={\displaystyle \frac{V_{\mathrm{in}}^{2}D{T}_s(n-1+D)}{2(n-1)n^2{L}_{N1}}}$$

(62)

3. Results

The hardware structure of the proposed three converters is established and displayed in Figure 16, and their detailed device specifications are given in Table 4.

Figure 16. Experiment prototype.

Table 4. Experiment device’s specifications.

Parameter	Description	Experiment/Value
Input Voltage	Vin	80 V
Output Voltage	Vo	300 V, 200 V, 200 V
Switch frequency	f	50 kHZ
Duty ratio	D	0.2
Output power	P	300 W
Capacitor	C1	240 uF
Capacitor	Co	440 uF
Magnetic core material	/	PC40
Maximum magnetic flux density	Bs	0.4 T
Hysteresis loss coefficient	Ch	1 × 10−7/mT
Effective permeability	μe	2400 ± 20%
Turn ratio	n	16:8
Diode	D1	SF1005G (10 A/300 V)
Diode	Do	MUR1070 (1.5 A/700 V)
Switch	S1	IPW65R019C7
MOSFET driver	/	HCPL3120

Figure 17 displays the experimental waveforms of the proposed PWCDVD-CLBC. Figure 17a shows the experimental waveforms of the voltages of the capacitors (Co and C₁). The experimental values of the parameters mentioned above are approximately 292 V and 156 V. Figure 17b describes the experimental waveforms of the windings (N₁ and N₂), and these waveforms are consistent with the theoretical operational status shown in Figure 6a,b. As described in Figure 17b, the current ranges of windings (N₁ and N₂), respectively, vary from 1 A to 13 A and −5 A to 2 A. Figure 17c shows the experimental waveforms of the voltages of the diodes (Do and D₁), whose experimental peak values are about 291 V and 196 V. Figure 17d–f shows the theoretical waveforms.

Figure 17. The experimental results of the proposed PWCDVD-CLBC’s (a) voltages of capacitors (C1 and Co), (b) currents of windings (N1 and N2), and (c) voltages of diodes (D1 and Do). The theoretical results of the proposed PWCDVD-CLBC’s (d) voltages of capacitors (C1 and Co), (e) currents of windings (N1 and N2), and (f) voltages of diodes (D1 and Do).

Figure 18 displays the experimental waveforms of the proposed SWCDVD-CLBC. Figure 18a shows the experimental waveforms of the voltages of the capacitors (C_o and C₁), whose experimental values are about 195 V and 77 V. Figure 18b shows the experimental waveforms of the windings (N₁ and N₂); the waveforms align with the theoretical operational status shown in Figure 6c,d. Its current ranges of windings (N₁ and N₂), respectively, vary from 0 A to 18 A and 1.5 to 12 A. Figure 18c shows the experimental waveforms of the voltages of the diodes (D_o and D₁), whose experimental peak values are about 194 V and 97 V. Figure 18d–f shows the theoretical waveforms.

Figure 18. The experimental results of the proposed SWCDVD-CLBC’s (a) voltages of capacitors (C₁ and C_o), (b) currents of windings (N₁ and N₂), and (c) voltages of diodes (D₁ and D_o). The theoretical results of the proposed PWCDVD-CLBC’s (d) voltages of capacitors (C1 and Co), (e) currents of windings (N1 and N2), and (f) voltages of diodes (D1 and Do).

Figure 19 displays the experimental waveforms of the proposed FPWCDVD-CLBC. Figure 19a shows the experimental waveforms of the voltages of the capacitors (C_o and C₁), whose experimental values are about 196 V and 78 V. Figure 19b provides the experimental waveforms of the windings (N₁ and N₂), and these waveforms are consistent with the theoretical operational status shown in Figure 6e,f. Its current ranges of windings (N₁ and N₂), respectively, vary from 0 A to 17 A and −2 to 7 A. Figure 19c shows the experimental waveforms of the voltages of the diodes (D_o and D₁), whose experimental peak values are about 195 V and 98 V. Figure 19d–f shows the theoretical waveforms.

Figure 19. The experimental results of the proposed FPWCDVD-CLBC’s (a) voltages of capacitors (C₁ and C_o), (b) currents of windings (N₁ and N₂), and (c) voltages of diodes (D₁ and D_o) The theoretical results of the proposed PWCDVD-CLBC’s (d) voltages of capacitors (C1 and Co), (e) currents of windings (N1 and N2), and (f) voltages of diodes (D1 and Do).

In summary, the experimental results are very close to the theoretical values and confirm the performance and feasibility of the proposed topologies.

An efficiency test for the proposed three converters was conducted, whose turn ratios are 2 and 1.5. The corresponding power range is between 50 W and 350 W. Figure 20 shows the efficiency curves of theoretical efficiency and experimental efficiency. In Figure 20, the experimental efficiency value is slightly higher and close to the theoretical efficiency value. All proposed converters can obtain a higher efficiency since their topologies utilize a lower component count. The magnetizing inductance L_M and leakage inductance L_k are crucial to energy transfer in the coupled-inductor cells. If the core saturates, the inductance values will drop significantly, and the inductor cannot store or transfer the expected energy, which results in a reduced voltage gain and lower output voltage than designed. The paper’s efficiency calculations (Equations (49), (55) and (61)) assume linear inductance behavior. Once core saturation sets in, effective inductance drops. The current increases to maintain power, causing higher conduction and switching losses.

Figure 20. Efficiency (a) n = 2 and (b) n = 1.5.

4. Discussion

By moving the switch device of the proposed converters forward and keeping the original charging and discharging path invariant, the topology extension of the proposed three converters is shown in Figure 21, which lowers the switch voltage stresses to a large degree and maintains the same voltage gain. The generalized structure variation is described in Figure 22. (* represents the homonymous end of the coupling inductance).

Figure 21. Topology extension: (a) PWCDVD-CLBC, (b) SWCDVD-CLBC, and (c) FPWCDVD-CLBC.

Figure 22. Generalized structure variation.

5. Conclusions

This paper proposes a family of voltage-doubling coupled-inductor boost converters—PWCDVD-CLBC, FPWCDVD-CLBC, and SWCDVD-CLBC—where the voltage gains and turn ratios for the PWCDVD-CLBC and FPWCDVD-CLBC have proportional relations, and the SWCDVD-CLBC has an inversely proportional relation, which was designed for high-voltage gains, continuous input current, and a reduced component count. By exploiting different winding configurations, the proposed topologies demonstrate superior performance in terms of efficiency, voltage stress, and shoot-through current, as validated through theoretical analyses, simulations, and experimental results. The practical implications are significant for applications requiring compact and efficient DC/DC conversion, such as renewable energy systems and electric vehicle charging infrastructures. Also, different topologies have varying efficiencies under different output power ranges when the turn ratio is adjusted. Finally, the experimental results of the proposed converters verify the correctness of the theoretical analysis.