An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling
Abstract
1. Introduction
2. FTN Signaling with Turbo Equalization
2.1. FTN Signaling with OBM
2.2. BCJR Detection and Turbo Equalization
2.3. LDPC and RS Code
Algorithm 1 BP Decoding of LDPC Code. |
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2.4. Experiment with 5G LDPC Code and Turbo Equalization in FTN Signaling
3. LDPC-RS Concatenation Code
3.1. Occurrence of an Error Floor in FTN Signaling
3.2. Structure of the Proposed LDPC-RS Concatenation Code
3.3. Perturbation BP Decoder
3.4. RS Parallel Encoder
Algorithm 2 Parallel Encoding Coefficient Calculation. |
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4. Performance Evaluation, Results, and Discussion
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
Appendix A. Parallel RS Encoding Coefficient Calculation
- Initialize the serial encoder, reset all registers to zero. Input . Let the encoder run for 4 clocks. Store all registers’ values and .
- Initialize the serial encoder, reset all registers to zero. Input . Let the encoder run for 4 clocks. Store all registers’ values and .
- Initialize the serial encoder, reset all registers to zero. Input . Let the encoder run for 4 clocks. Store all registers’ values and .
- Initialize the serial encoder, reset all registers to zero. Input . Let the encoder run for 4 clocks. Store all registers’ values and .
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Shi, H.; Luo, Z.; Li, C. An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling. Electronics 2024, 13, 1588. https://doi.org/10.3390/electronics13081588
Shi H, Luo Z, Li C. An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling. Electronics. 2024; 13(8):1588. https://doi.org/10.3390/electronics13081588
Chicago/Turabian StyleShi, Honghao, Zhiyong Luo, and Congduan Li. 2024. "An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling" Electronics 13, no. 8: 1588. https://doi.org/10.3390/electronics13081588
APA StyleShi, H., Luo, Z., & Li, C. (2024). An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling. Electronics, 13(8), 1588. https://doi.org/10.3390/electronics13081588