Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology
Abstract
:1. Introduction
2. Description of the Utilized GNRFET Model
3. Logic Design Employing GNRFETs
3.1. NOT, NOR and NAND Gates
3.2. Full Adder
3.3. D-Latch
4. Comparison of the Performances of Silicon-Based CMOS and GNRFET-Based CMOS Logic Blocks
5. A Deep Learning Network Design for Power Consumption and Delay Modeling of GNRFET Logic
6. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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Ci | A | B | Co | Sum | Result |
---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | (0)10 |
0 | 0 | 1 | 0 | 1 | (1)10 |
0 | 1 | 0 | 0 | 1 | (1)10 |
0 | 1 | 1 | 1 | 0 | (2)10 |
1 | 0 | 0 | 0 | 1 | (1)10 |
1 | 0 | 1 | 1 | 0 | (2)10 |
1 | 1 | 0 | 1 | 0 | (2)10 |
1 | 1 | 1 | 1 | 1 | (3)10 |
D | Clk | Qn | Qn′ |
---|---|---|---|
0 | 0 | Qc | Qc’ |
0 | 1 | 0 | 1 |
1 | 0 | Qc | Qc′ |
1 | 1 | 1 | 0 |
Parame | Design | Unit | Value |
---|---|---|---|
Vdd = Vi+ | Both | V | 0.7 |
Vgnd = Vi− | Both | V | 0 |
Input wave | Both | - | Square |
Input frequency | Both | MHz | 100 |
R (load) | Both | MΩ | 1000 |
Wp/Wn | MOS | nm | 14/7 |
Wp = Wn | GNR | nm | 7/7 |
Lp = Ln | Both | nm | 7/7 |
Np = Nn | GNR | - | 42 |
Circuit/Input | 111 | 110 | 101 | 100 | 011 | 010 | 001 | 000 |
---|---|---|---|---|---|---|---|---|
NOT-MOS | - | - | - | - | - | - | 9.41 | 692.52 |
NOT-Fin | - | - | - | - | - | - | 0.45 | 699.27 |
NOT-GNR | - | - | - | - | - | - | 1.61 | 698.38 |
NOR-MOS | - | - | - | - | 0.14 | 4.46 | 7.68 | 672.52 |
NOR-Fin | - | - | - | - | 0.00 | 0.32 | 0.43 | 697.09 |
NOR-GNR | - | - | - | - | 0.14 | 1.43 | 1.52 | 693.58 |
NAND-MOS | - | - | - | - | 33.36 | 695.70 | 693.38 | 699.82 |
NAND-Fin | - | - | - | - | 1.78 | 699.39 | 699.28 | 699.95 |
NAND-GNR | - | - | - | - | 6.39 | 698.57 | 698.48 | 699.86 |
FA-Co-MOS | 692.44 | 688.27 | 689.14 | 11.77 | 690.32 | 12.63 | 13.28 | 9.51 |
FA-Co-Fin | 699.27 | 699.24 | 699.24 | 0.48 | 699.25 | 0.48 | 0.49 | 0.45 |
FA-Co-GNR | 698.35 | 698.03 | 698.04 | 1.97 | 698.03 | 1.95 | 1.96 | 1.64 |
FA-Sum-MOS | 687.72 | 13.88 | 14.13 | 688.52 | 13.25 | 687.52 | 688.06 | 14.52 |
FA-Sum-Fin | 699.22 | 0.50 | 0.47 | 699.24 | 0.50 | 699.24 | 699.24 | 0.52 |
FA-Sum-GNR | 697.58 | 1.99 | 2.01 | 698.00 | 2.00 | 697.99 | 698.00 | 2.41 |
DL-Q-MOS | - | - | - | - | 699.64 | 37.05 | 34.99 | 692.59 |
DL-Q-Fin | - | - | - | - | 699.95 | 1.81 | 1.80 | 699.37 |
DL-Q-GNR | - | - | - | - | 699.82 | 6.77 | 6.59 | 698.22 |
Circuit/Input | Avg. Power (nW) | PGNR /PMOS | 111 | 110 | 101 | 100 | 011 | 010 | 001 | 000 |
---|---|---|---|---|---|---|---|---|---|---|
NOT-MOS | 1250.60 | 18.50% | - | - | - | - | - | - | 1514.80 | 986.45 |
NOT-Fin | 625.72 | - | - | - | - | - | - | 580.42 | 671.03 | |
NOT-GNR | 231.40 | - | - | - | - | - | - | 226.28 | 236.52 | |
NOR-MOS | 945.39 | 24.56% | - | - | - | - | 44.56 | 735.30 | 1241.40 | 1760.30 |
NOR-Fin | 583.61 | - | - | - | - | 28.84 | 404.76 | 567.89 | 1332.0 | |
NOR-GNR | 232.19 | - | - | - | - | 41.22 | 204.02 | 218.75 | 464.77 | |
NAND-MOS | 1025.00 | 22.94% | - | - | - | - | 2602.50 | 574.06 | 876.26 | 47.21 |
NAND-Fin | 610.88 | - | - | - | - | 1153.80 | 552.27 | 660.92 | 76.50 | |
NAND-GNR | 235.11 | - | - | - | - | 475.08 | 206.99 | 217.65 | 40.73 | |
FA-MOS | 6570.30 | 21.38% | 4335.20 | 7731.60 | 7387.50 | 6518.90 | 6222.60 | 7505.90 | 7561.40 | 5299.20 |
FA-Fin | 3378.30 | 2555.40 | 3700.10 | 3637.00 | 3428.30 | 3305.90 | 3711.50 | 3667.90 | 3019.80 | |
FA-GNR | 1404.90 | 1270.50 | 1437.60 | 1458.50 | 1447.40 | 1445.70 | 1446.10 | 1470.20 | 1263.30 | |
DL-MOS | 6790.60 | 19.50% | - | - | - | - | 7564.20 | 6465.20 | 7410.10 | 5722.60 |
DL-Fin | 3382.10 | - | - | - | - | 3539.00 | 3080.10 | 3746.70 | 3162.50 | |
DL-GNR | 1324.30 | - | - | - | - | 1413.00 | 1217.30 | 1443.90 | 1223.00 |
Circuit/Delay | Average Delay | Delay Ratio (MOS/GNR) | td4 | td3 | td2 | td1 |
---|---|---|---|---|---|---|
NOT-MOS | 1.15 | 43.48% | - | - | 0.87 | 1.44 |
NOT-Fin | 1.19 | - | - | 0.59 | 1.79 | |
NOT-GNR | 0.50 | - | - | 0.45 | 0.55 | |
NOR-MOS | 1.84 | 65.67% | - | - | none | 3.67 |
NOR-Fin | 1.77 | - | - | none | 3.54 | |
NOR-GNR | 1.21 | - | - | none | 2.41 | |
NAND-MOS | 0.88 | 77.14% | - | - | 1.75 | none |
NAND-Fin | 0.92 | - | - | 1.84 | none | |
NAND-GNR | 0.68 | - | - | 1.35 | none | |
FA-Co-MOS | 4.09 | 34.47% | 5.05 | 2.69 | 5.12 | 3.49 |
FA-Co-Fin | 3.07 | 3.82 | 1.62 | 3.84 | 2.97 | |
FA-Co-GNR | 1.06 | 1.86 | none | 0.79 | 1.59 | |
FA-Sum-MOS | 6.73 | 18.57% | 14.07 | 8.90 | 3.63 | 0.30 |
FA-Sum-Fin | 6.15 | 13.60 | 7.78 | 3.22 | none | |
FA-Sum-GNR | 0.31 | none | 1.25 | none | none | |
DL-MOS | 5.79 | 40.93% | - | - | 4.05 | 7.52 |
DL-Fin | 5.19 | - | - | 3.68 | 6.71 | |
DL-GNR | 2.37 | - | - | 1.99 | 2.75 |
Power Dissipation | R2 | MAPE | MAE | RMSE |
---|---|---|---|---|
for N = 3p | 0.99 | 0.04 | 1.42 | 1.85 |
for N = 3p + 1 | 0.99 | 0.15 | 1.61 | 2.90 |
for N = 3p + 2 | 0.94 | 0.03 | 3.74 | 8.23 |
Delay | R2 | MAPE | MAE | RMSE |
---|---|---|---|---|
for N = 3p | 0.86 | 0.14 | 0.05 | 0.07 |
for N = 3p + 1 | 0.96 | 0.31 | 0.07 | 0.13 |
for N = 3p + 2 | 0.92 | 0.27 | 0.02 | 0.03 |
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Emir, R.; Yamacli, D.S.; Yamacli, S.; Tekin, S.A. Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology. Electronics 2024, 13, 2993. https://doi.org/10.3390/electronics13152993
Emir R, Yamacli DS, Yamacli S, Tekin SA. Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology. Electronics. 2024; 13(15):2993. https://doi.org/10.3390/electronics13152993
Chicago/Turabian StyleEmir, Recep, Dilek Surekci Yamacli, Serhan Yamacli, and Sezai Alper Tekin. 2024. "Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology" Electronics 13, no. 15: 2993. https://doi.org/10.3390/electronics13152993
APA StyleEmir, R., Yamacli, D. S., Yamacli, S., & Tekin, S. A. (2024). Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology. Electronics, 13(15), 2993. https://doi.org/10.3390/electronics13152993