Advanced CMOS Devices and Applications

The persistent scaling of transistor dimensions has marked an era characterized by a fourfold increase in transistor density and a twofold boost in electrical performance every 2–3 years, effectively reducing their cost per function. This has been propelled by the scalability and ubiquity of complementary metal–oxide–semiconductor (CMOS) technology in silicon, a cornerstone of the semiconductor industry. However, as conventional silicon devices approach fundamental physical limits, researchers have begun fervently exploring new device architectures and novel channel materials with superior electrical properties. Fin-shaped field-effect transistors (FinFETs) have undeniably become a mainstream CMOS logic technology. However, their scalability challenges at 14/10/7/5 nm underscore the need for alternative architectures. This quest mandates the development of innovative structural, material, and process technologies that align with both current and projected silicon platform advancements.

A pivotal shift is on the horizon, foretold by the International Roadmap for Devices and Systems (IRDS)—the transition from FinFET technology to the intriguing realm of “three-dimensional (3D) power scaling”. This transformative leap necessitates the creation of a new breed of high-performance, low-power transistors fashioned into 3D structures. Unlike traditional lithography-driven density increases, this technology vertically constructs each transistor with the same footprint, leading to a heightened transistor density per unit area. While 3D-stacked transistors introduce an additional degree of freedom for increasing device densities, their potential is fully harnessed when integrated with high-mobility channel materials and channel strain engineering. As standalone units, 3D-stacked transistors do not inherently enhance device performance. The infusion of non-silicon (Si) channel materials like SiGe, Ge, and III-V compounds becomes paramount for optimal integration compatibility with 3D-stacked transistors.

In tandem with 3D power scaling, state-of-the-art component research into advanced transistor processing has emerged as a cornerstone. The pursuit of high-performance, low-power technology mandates a meticulous exploration of innovative transistor processing techniques, ensuring that each step in its fabrication contributes to the overall efficiency and reliability of the device. High-mobility channels, the lifeblood of advanced semiconductor technology, come under intense scrutiny. Researchers are exploring materials and designs that maximize electron and hole mobilities, striving for optimal performance and efficiency. The marriage of 3D transistors with high-mobility channels promises a synergy that can redefine the landscape of semiconductor technology. The heterogeneous and monolithic 3D integration of different devices, chips, or wafers stands as another frontier, presenting an opportunity not only for increased device density but also for the integration of diverse functionalities on a single platform. Challenges in ensuring seamless compatibility and performance optimization across disparate components drive researchers to explore innovative solutions. In this dynamic landscape, the significance of accurate and efficient simulation cannot be overstated. Novel simulation results provide a crucial roadmap, guiding researchers through the intricate design space of emerging technologies. These simulations, often based on advanced methodologies such as artificial neural networks, offer insights into device behavior, aiding circuit designers and process engineers in optimizing their performance and functionality.

This special issue will unfold numerous contributions, each addressing a specific facet of this transformative landscape—from emerging non-volatile memories to gate-all-around 3D transistors. It will cover state-of-the-art component research into advanced transistor processing, high-mobility channels, and heterogeneous and monolithic 3D integration for novel device simulation results. Together, these endeavors chart the course for the next chapter in semiconductor evolution.

Highlighting Key Contributions

Developing advanced semiconductor technology for 5 nm logic transistor nodes and beyond is essential for future high-performance and low-power technology to be used in high-end servers, gaming chips, mobile phones, laptops, etc. To meet transistor performance targets, the innovation of device architecture, along with the introduction of high-mobility channel material and strain engineering, is mandatory.

Sagarika Mukesh and Jingyun Zhang from IBM discuss the integration scheme and challenges of full bottom isolation and multiple threshold voltages in gate-all-around nanosheet FETs (Contributor 1). Additionally, they explore the mobility of electrons and holes as a function of channel geometry, a crucial consideration in designing high-performance gate-all-around nanosheet FETs. To assist circuit designers and process engineers working on advanced semiconductor devices, SangMin Woo et al. developed a compact and accurate simulation model based on artificial neural networks (ANNs). This ANN-based compact model is approximately two times faster than the SPICE simulations of the existing compact model, and its accuracy is demonstrated through simulations of XOR, ring oscillators, and SRAM circuits (Contributor 2).

Emerging nanoscale logic and non-volatile memory (NVM) devices such as resistive, magnetic, and ferroelectric memories are vital to realize neuromorphic computation, which mimics the human brain’s architecture in order to significantly increase a computer’s thinking and responding power. Since the discovery of ferroelectric properties in Hf-based thin films in 2011, they have attracted much attention for their CMOS compatibility and scalability for applications in logic and memory devices. Defects and surface energy are arguably two main categories of impact factors that help stabilize the metastable orthorhombic phase in Hf-based oxides. Tianning Cui et al. discuss the intrinsic parameters used to stabilize the ferroelectric phase of HfO₂ thin films by investigating the separate effects of dopant, oxygen vacancy, and specific surface area on the crystal phase of the films (Contributor 3). Jaewook Yoo et al. describe several types of ferroelectric-based memory devices, including two-terminal-based FTJ, three-terminal-based FeFET, and FeRAM, focusing on their operational mechanisms, features, and potential applications (Contributor 4). Seonjun Choi et al. use ferroelectric materials for practical applications of 3D NAND structures, replacing the charge trapping layer in conventional flash memory with ferroelectric materials. Their TCAD simulation results show that the silicon pillar structure can maximize the operating performance of ferroelectric memory while achieving the advantages of 3D NAND structures (Contributor 5).

In addition, resistive random-access memory based on transition metal oxides has attracted increasing attention as one of the most promising candidates for the next generation of eNVM due to its prominent advantages, including low cost, high integration density, fast switching speed, high endurance, and good CMOS process compatibility. Huikai He et al. propose a simple strategy for regulating the leakage current, forming a voltage, a memory window, and uniformity by varying the thickness of a Ti buffer layer between the resistive switching layer and metal electrode. The Ti buffer layer plays a vital role in engineering the interfacial oxidation reaction, acting as an oxygen-scavenging layer to enhance resistive uniformity (Contributor 6). Wei Na et al. study RRAM devices with a metal–insulator–semiconductor structure, including an HfOx switching layer and Ge or Si bottom electrodes, to achieve a higher memory window with good endurance. A memory window over 10⁵ was achieved with Pd/HfOx/p-Ge RRAM devices, and the conductance mechanism was analyzed in detail. These results suggest that HfOx/Ge RRAM devices are promising candidates for applications of FPGA and neuromorphic computation (Contributor 7).

Regarding Si CMOS technologies, germanium is an attractive choice of channel material for further advanced nodes since it has smaller effective masses for both electrons and holes than Si and SiGe and, as a group XIV element, has high process compatibility with Si. A typical cause of performance degradation in practically scaled devices is an increase in parasitic resistance. The parasitic resistance is composed of interconnecting and contact metal resistance, semiconductor resistance around the source/drain, and contact resistance just at the metal/semiconductor interface. Tomonori Nishimura describes the metal/Ge interface, including the origin of strong Fermi-level pinning (FLP) at the valence band edge of Ge, and proposes a possible method of reducing the Schottky barrier height at this interface. FLP alleviation is achieved by weakening the intrinsic metal-induced gap states at the metal/Ge interface and may be pivotal in designing scaled Ge n-FETs (Contributor 8).

A 3D-stacked device architecture alleviates the challenges involved in traditionally planar scaling transistors while continuously improving the effective chip density and performance. Here, a “monolithic” or “sequential” approach is discussed but not a “packaging” one, where interlayer connectivity is dominated by chip bonding alignment accuracy. This further enables additional functionalities to be implemented in CMOS devices, called “More Than Moore”. Toshiyuki Tabata et al. illustrate the recent progress of ns and μs ultra-violet laser annealing technology, one of the most critical component technologies to realize 3D-integrated CMOS devices, where a new electrically functional Si (or other semiconductor material) layer must be fabricated directly on the underlayer components, either by wafer bonding or deposition. For 3D integration, the thermal budget should be below 500 °C to avoid the performance degradation of underlayer components (Contributor 9). Jaeyong Jeong et al. introduce heterogeneous and monolithic 3D (M3D) integration to maximize the benefits of 3D integration in terms of low power consumption, interconnection delay, and via densities. In particular, they share recent research on the M3D integration of RF devices on Si CMOS circuits and InGaAs photodetectors on Si bottom FETs for realizing future M3D-based mixed-signal systems (Contributor 10). Hyungwoo Kim delivers a comprehensive review of recent trends in metallization, including traditional barrier/liner thickness scaling and new materials and integration schemes. The innovative approaches proposed to date can contribute to scaling requirements not through direct scaling but with architectural innovations such as super vias and buried power rails (Contributor 11).

A transistor (1T) dynamic random-access memory (DRAM) without capacitors has garnered great attention due to its scalability, where 1T-DRAM utilizes the floating body effect of a partially depleted silicon-on-insulator (SOI) to retain memory performance. However, SOI wafers are significantly costly and difficult to fabricate. Geon Uk Kim et al. report a low-cost method for forming SOI-like structures using polycrystalline silicon in a TCAD simulation. By decoupling the channel and the storage layer with separation oxide, the 1T-DRAM achieves a high retention time (Contributor 12). The insulated gate bipolar transistor (IGBT) is widely used as a switching device in inverter circuits for driving motors. To improve the performance of the IGBT, Xiaodong Zhang et al. propose an IGBT with an injection-enhanced p-floating layer in a TCAD simulation, acting as a current amplification stage and suppressing the snapback effect during the turn-on period (Contributor 13).

In conclusion, the diverse array of contributions presented in this special issue represents a collective stride toward the future of semiconductor technology. From innovative device architectures and novel materials to advanced simulation techniques, each paper contributes to the next chapter in semiconductor evolution. As we delve deeper into the intricacies of 3D power scaling, high-mobility channels, and cutting-edge transistor processing, we are not just witnessing incremental advancements; we are shaping the landscape of technology for years to come. The collaborative efforts showcased here pave the way for enhanced performance, efficiency, and functionality in high-end servers, gaming chips, mobile phones, laptops, and beyond.