Data-Driven Constraint Handling in Multi-Objective Inductor Design
Abstract
:1. Introduction
2. Design Procedure of Inductors for DC-DC Converters
3. Statement of the Design Problem
- Lower bound, ;
- Upper bound, ;
- Inductance drop limit, ;
4. Multi-Objective Optimisation Approach
- An outer loop (network), where randomly generated configurations are introduced in the population (exploration);
- An inner loop (clonal selection), where the population is improved by means of local mutations (exploitation).
- Further details about the optimisation algorithm can be found in Appendix A.
- 1.
- First, the geometric consistency is checked (e.g., non-negative area of the core’s windows). An inconsistent configuration is discarded and replaced by a new one if it was randomly generated. Otherwise, if the configuration is a clone (mutated from a feasible configuration), the mutation is gradually reduced until the solution is feasible again.
- 2.
- 3.
- The remaining candidate solutions are evaluated in terms of objectives (volume and total losses).
- The clouds of points in Figure 4 represent all the design configurations explored during a complete run of the optimisation procedure on the test problem, in the objectives space (volume V and total losses P, on the x and y axes, respectively). The colour depends on the feasibility of the configurations and distinguishes those configurations compliant with the design constraints (i.e., good, orange points) from those that are unfeasible (i.e., bad, blue points). Two graphs are reported to further distinguish between parent configurations (Figure 4a) and clones (Figure 4b). It can be noticed that only a small percentage of the configurations generated randomly (parents) is feasible. Clones, instead, have higher chances of complying with the design constraints since they originate from local mutations of feasible configurations.
5. Surrogate Modelling of Constraints for Pre-Selection
5.1. AIS-Based Classifier
5.2. Effects of the Classifier on the Optimisation
- True positives: feasible configurations that are correctly classified as positive.
- False positives: unfeasible configurations wrongly classified as positives. Since they are evaluated with the FP during the optimisation, the incorrect classification implies unnecessary calculation that slows down the procedure.
- True negatives: unfeasible configurations correctly classified as negative, which can be correctly disregarded in the optimisation process.
- False negatives: feasible configurations wrongly classified as negatives, which are therefore disregarded during the optimisation. This is the worst case since it implies discarding solutions potentially belonging to the Pareto Front.
5.3. Evaluation of the Classifier’s Performance
- The high percentage of true negatives (around 97%) in the randomly generated configurations considerably reduces the number of FP evaluations in this phase. Despite the high rate of false positives, the low number of total positives identified by the classifier among the parent results in a significant reduction in the unnecessary evaluations of the FP.
- The good performance in the classification of negatives among parents is motivated by the presence of wide areas of unfeasible configurations in the design space (Figure 5a).
- As previously discussed (Figure 5b), the classification task is much harder in the proximity of the interface between the feasibility region and the rest of the design space. Most configurations generated from local mutations are located in this area. This explains the poor performance of the classifier in the clones. In particular, while around 200,000 FP evaluations are saved by correct classification of unfeasible configurations (true negatives), an equivalent number of feasible configurations are wrongly disregarded.
- The percentage of false positives in clones is smaller than in parents. However, around 150,000 configurations are unnecessarily evaluated.
6. Evaluation of the Surrogate Modelling Approach
- Execution of VIS optimisation method without a classifier ().
- Application of the classifier only on randomly generated configurations ().
- Application of the classifier both on randomly generated and locally mutated configurations. ().
- For each of the presented cases, 30 optimisation executions are performed. The first result is the average number of FP evaluation calls, reported in Figure 7, in which separated results are reported for the classification of parents and clones.
7. Conclusions
Author Contributions
Funding
Conflicts of Interest
Appendix A
- 1.
- An initial population of configurations (antibodies ) is randomly generated.
- 2.
- A memory set is also created, initially empty, where all the non-dominated solutions found during the search are stored.
- 3.
- The memory set is built through a network loop, where for iterations or until a stop criterion is reached:
- (a)
- The fitness f of all antibodies in the current population is evaluated, also including the antibodies eventually present in the memory set.
- (b)
- The current population is improved through a clonal selection loop, where for iterations or until a stop criterion is reached:
- i.
- The antibodies in the current population (parents) are replicated into clones;
- ii.
- Each clone is then locally mutated. The random mutation is evaluated as follows: , where is a mutation amplitude parameter and f the fitness of the parent (lower fitness corresponds to larger mutations);
- iii.
- The fitness of the clones is evaluated, also including the antibodies eventually present in the memory set;
- iv.
- The clone with the highest fitness is selected and it replaces the parent in the next generation if it has higher fitness.
- (c)
- The current population and the memory set are merged and their affinity is calculated.
- (d)
- Network selection is performed, removing antibodies with high affinity. The affinity threshold is evaluated as follows: , where m is the number of objectives and is the desired size of the memory set.
- (e)
- The memory set is updated with the non-dominated solutions, among those that survived the network selection.
- (f)
- A fraction (with respect to the current size of the population) of randomly generated new configurations is introduced in the population to increase the exploration of the design space.
- 4.
- The final memory set is taken as the Pareto set of the problem.
- The values of the parameters adopted in all the runs of the VIS optimisation are shown in Table A1.
Parameter | Value |
---|---|
Initial population size, | 50 |
Number of clones, | 5 |
Desired size of the memory set, | 100 |
Number of network loops, | 50 |
Number of clonal selection loops, | 10 |
Mutation amplitude factor, | 0.02 |
Fraction of new antibodies, | 0.4 |
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Input voltage | 48 V |
Output voltage | 24 V |
Output current | 10 A |
Maximum current ripple (pp) | 30% |
Switching frequency | 50 kHz |
Inductance value | 80 μH |
Variable | Lower Bound | Upper Bound |
---|---|---|
A | 30 mm | 59.2 mm |
B | 8 mm | 22.3 mm |
F | 2 mm | 8 mm |
g | 0 mm | 2 mm |
N | 6 | 100 |
Minimum inductance value, | |
Maximum inductance value, | |
Maximum inductance drop factor, | |
Maximum over-temperature, |
Parents | Clones | |
---|---|---|
True positive (%) | 44 | 67 |
False positive (%) | 56 | 33 |
True negative (%) | 99 | 51 |
False negative (%) | 1 | 49 |
Total positive | ||
Total negative |
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Lorenti, G.; Ragusa, C.S.; Repetto, M.; Solimene, L. Data-Driven Constraint Handling in Multi-Objective Inductor Design. Electronics 2023, 12, 781. https://doi.org/10.3390/electronics12040781
Lorenti G, Ragusa CS, Repetto M, Solimene L. Data-Driven Constraint Handling in Multi-Objective Inductor Design. Electronics. 2023; 12(4):781. https://doi.org/10.3390/electronics12040781
Chicago/Turabian StyleLorenti, Gianmarco, Carlo Stefano Ragusa, Maurizio Repetto, and Luigi Solimene. 2023. "Data-Driven Constraint Handling in Multi-Objective Inductor Design" Electronics 12, no. 4: 781. https://doi.org/10.3390/electronics12040781
APA StyleLorenti, G., Ragusa, C. S., Repetto, M., & Solimene, L. (2023). Data-Driven Constraint Handling in Multi-Objective Inductor Design. Electronics, 12(4), 781. https://doi.org/10.3390/electronics12040781