An Asymmetrical 19-Level Inverter with a Reduced Number of Switches and Capacitors
Abstract
:1. Introduction
2. Proposed 19-Level Inverter
3. The Proposed Generalized Multilevel Inverter
4. Comparison of the Proposed Multilevel Inverter with Other Topologies
5. Multi-Carrier Pulse Width Modulation Technique
6. Calculation of Losses and Efficiency
6.1. The Capacitor Charging Losses
6.2. The Switching Losses
6.3. The Conducting Losses
7. Simulation and Experimental Results
7.1. Simulation Results
7.2. Experimental Results
- (1)
- All gate driver power supplies should be isolated from each other.
- (2)
- The reference signal in the MC-PWM (see Figure 5) must be set on the sample base mode with 1000/5 samples per period and a sample time of 0.0001 s.
- (3)
- A high-power resistor should be applied parallel to each capacitor for discharging their voltage when the test is completed.
8. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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States | S1S2S3S4S5 | T1T2T3T4 | C1C2 | Vout |
---|---|---|---|---|
1 | 11110 | 1010 | D-D | +9 V |
2 | 11100 | 1010 | D-W | +8 V |
3 | 11000 | 1010 | D-W | +7 V |
4 | 01110 | 1010 | D-D | +6 V |
5 | 01100 | 1010 | D-W | +5 V |
6 | 10101 | 1010 | C-C | +4 V |
7 | 10100 | 1010 | W-W | +3 V |
8 | 00110 | 1010 | W-D | +2 V |
9 | 00100 | 1010 | W-W | +V |
10 | 10101 | 1100 | C-C | 0+ |
11 | 10101 | 1100 | C-C | 0− |
12 | 00100 | 0101 | W-W | −V |
13 | 00110 | 0101 | W-D | −2 V |
14 | 10100 | 0101 | W-W | −3 V |
15 | 10101 | 0101 | C-C | −4 V |
16 | 01100 | 0101 | D-W | −5 V |
17 | 01110 | 0101 | D-D | −6 V |
18 | 11000 | 0101 | D-W | −7 V |
19 | 11100 | 0101 | D-W | −8 V |
20 | 11110 | 0101 | D-D | −9 V |
NLevel | First Symmetrical Mode | Second Asymmetrical Mode | Third Asymmetrical Mode | ||||||
---|---|---|---|---|---|---|---|---|---|
Nsw | Nd | NC | Nsw | Nd | NC | Nsw | Nd | NC | |
5 | 7 | 3 | 1 | 7 | 3 | 1 | 7 | 3 | 1 |
15 | 9 | 6 | 2 | -- | -- | -- | -- | -- | -- |
19 | -- | -- | -- | 9 | 6 | 2 | 9 | 6 | 2 |
33 | 11 | 9 | 3 | -- | -- | -- | -- | -- | -- |
47 | -- | -- | -- | 11 | 9 | 3 | -- | -- | -- |
61 | 13 | 12 | 4 | -- | -- | -- | -- | -- | -- |
67 | -- | -- | -- | -- | -- | -- | 11 | 9 | 3 |
93 | -- | -- | -- | 13 | 12 | 4 | -- | -- | -- |
101 | 15 | 15 | 5 | -- | -- | -- | -- | -- | -- |
161 | -- | -- | -- | 15 | 15 | 5 | -- | -- | -- |
155 | 17 | 18 | 6 | -- | -- | -- | -- | -- | -- |
231 | -- | -- | -- | -- | -- | -- | 13 | 12 | 4 |
255 | -- | -- | -- | 17 | 18 | 6 | -- | -- | -- |
Topology | NL | Nsw | Nd | NC | Ngd | VG | TSVpu |
---|---|---|---|---|---|---|---|
[18] | 13 | 7 | 3 | 0 | 7 | 2.16 | 9 |
[20] | 13 | 14 | 0 | 2 | 11 | 2 | 5.33 |
[21] | 17 | 10 | 2 | 2 | 10 | 2 | 5.5 |
[22] | 17 | 10 | 2 | 2 | 10 | 2 | 5.5 |
[23] | 13 | 11 | 1 | 1 | 10 | 1.5 | 6.3 |
[24] | 13 | 18 | 0 | 2 | 15 | 2 | 5 |
[25] | 17 | 18 | 2 | 4 | 14 | 2 | 6 |
[26] | 19 | 12 | 6 | 4 | 12 | 2.2 | 5.8 |
[27] | 19 | 12 | 1 | 2 | 10 | 1.8 | 6.66 |
Pro. | 19 | 9 | 6 | 2 | 9 | 2.25 | 7.2 |
First input DC-source | u1 = 60 v |
Second input DC-source | u2 = 20 v |
Peak output voltage | 180 v |
Processor | DSP TMS320F28379D |
Capacitors | C1 = C2 = 4700 μF |
IGBT | IRG4IBC30S |
Diode | MBRF20100CT |
Driver/optocoupler | HCPL-3120 |
Current sensor | Resistive divider (0.1 Ω, 40 w) |
Voltage sensor | Resistive divider (5 × 100 kΩ) |
Sample time | 10 μs |
Switching frequency | 5 kHz |
Output frequency | 50 Hz |
Resistive load | R = 300 Ω, 150 Ω |
Resistive-Inductive load | R = 300 Ω, L = 22 mH |
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Sagvand, F.; Siahbalaee, J.; Koochaki, A. An Asymmetrical 19-Level Inverter with a Reduced Number of Switches and Capacitors. Electronics 2023, 12, 338. https://doi.org/10.3390/electronics12020338
Sagvand F, Siahbalaee J, Koochaki A. An Asymmetrical 19-Level Inverter with a Reduced Number of Switches and Capacitors. Electronics. 2023; 12(2):338. https://doi.org/10.3390/electronics12020338
Chicago/Turabian StyleSagvand, Farzad, Jafar Siahbalaee, and Amangaldi Koochaki. 2023. "An Asymmetrical 19-Level Inverter with a Reduced Number of Switches and Capacitors" Electronics 12, no. 2: 338. https://doi.org/10.3390/electronics12020338
APA StyleSagvand, F., Siahbalaee, J., & Koochaki, A. (2023). An Asymmetrical 19-Level Inverter with a Reduced Number of Switches and Capacitors. Electronics, 12(2), 338. https://doi.org/10.3390/electronics12020338