A Family of Five-Level Pseudo-Totem Pole Dual Boost Converters

Abstract

In this paper, based on the pseudo-totem pole (PTP) circuit, a family of five-level PTP dual boost converters (PDBC) is proposed. A dual boost converter has some unique advantages, such as having no risk of bridge arm shoot-through and no problems related to switch body diode reverse recovery; thus, it has a good potential for applications. First, the derivation process, working principle, modulation and strategy of the topology are analyzed. Further, the number of power devices, switch voltages and current stress of the proposed topology is analyzed. Finally, a representative five-level PDBC experimental prototype is designed with AC input 220 V/50 Hz, DC output 400 V/1 kW, and peak efficiency of 98.27%. The experimental results show that the five-level PDBC proposed in this paper has higher efficiency and the correctness of its topology is verified.

1. Introduction

With the development of power electronics technology, the neutral point clamped (NPC) multi-level converter has attracted more and more scholars’ attention [1,2]. Multi-level NPC converters have the advantages of high efficiency, high power density, low total harmonic distortion (THD) and low voltage and current stress [3,4,5]. Therefore, multi-level NPC converters are widely used in medium and high power, medium voltage applications [6,7,8,9], such as electric vehicles (EVs), motor drives, electrical railway traction, and DC-bus microgrids [10,11,12,13].

Compared to an IGBT, a power MOSFET has some excellent characteristics, such as high frequency operation andlow switching and conduction losses. Therefore, power MOSFETs are widely used in low-power converters to improve efficiency and reduce volume. However, due to the poor reverse recovery characteristics of the body diode, those that are MOSFET-based have a risk of device failure, which is related to the phase-leg shoot, and this may cause false triggering of the gate voltage. Therefore, conventional H-bridge converters often use IGBTs [14,15,16,17]. The dual boost/buck converter can avoid the shoot-through problem effectively, and the freewheeling current flows through the independent diode to resolve the MOSFET body diode reverse recovery problem [14,15,16,17,18,19,20,21]. However, due to the two inductance structures of the dual boost/buck converter, the volume and weight of the converter will increase. With this in mind, the multi-level dual boost/buck converter has been proposed in [16,17,22], to reduce the size and weight of this type of topology.

The bridgeless converter has a high power factor (PF), low THD and high efficiency. This type includes the basic bridgeless converters, bidirectional-switch bridgeless converters, totem pole bridgeless converters and PTP bridgeless converters [22,23,24]. Among these, the PTP bridgeless converter has a simple structure, few semiconductor devices conducting in the series loop and a natural dual-boost structure. In order to increase the power density and reduce the THD, the PTP bridgeless converter must work at a higher frequency. Moreover, all the active devices in the circuit carry a DC voltage, which causes high voltage stress [3].

Figure 1 shows two common five-level converter topologies. Figure 1a is conventional five-level converter (CFLC), which is widely used in bidirectional power flow scenarios such as vehicle to grid (V2G) technologies. However, the number of switches is large; thus, this can be further optimized to reduce the number of switches. Figure 1b is a unidirectional five-level converter proposed in [25], which uses only one NPC bridge arm in the CFLC to reduce the number of switches. However, there is no topology derivation process. In [4], a new five-level converter with high power density is proposed and the current stress is analyzed; however, the number of active devices is large, and the cost is high. In [14,16], the PTP bridgeless structure is adopted to achieve a five-level, dual-buck, grid-connected inverter, and these papers summarize a topology structure method to expand the circuit. However, the utilization of these two input inductors is low.

Based on the above analysis, the bridge arm of the topology proposed in [25] is used as the prototype to obtain new five-level bridge arms. By cascading the five-level bridge arms with the three-level PTP circuit, a family of five-level PDBCs is proposed. The proposed PDBC optimizes the three-level PTP converter to address the large volume and large switching losses and to retain the dual boost structure; thus, it has high reliability.

The structure of this paper is as follows. Section 2 derives the PDBC in detail and analyzes the working principle. Section 3 designs the control and modulation strategy of PDBC. In Section 4, the voltage and current stress are analyzed. Section 5 conducts experimental verification on PDBC. Finally, Section 6 concludes the paper.

2. Topological Derivation and Operating Principle

2.1. Topological Derivation

Figure 2 shows the three most commonly used clamping bridge arm structures in five-level converters. A new five-level converter can be obtained by cascading these three clamping bridge arm structures with a three-level circuit.

In this paper, the bridge arm shown in Figure 2b is used to generate a new bridge arm, as shown in Figure 3. For ease of description, the bridge arms are numbered below each bridge arms, i.e., A1, A2. Firstly, the two diodes on the right side of A4 are replaced with MOSFETs to get A1*. Then, S₂ and S₄ of A1* are removed and reconnected to get a new bridge arm A2, as shown in Figure 3a. In the same way, S₁ and S₃ of A1* are removed and reconnected to obtain a new bridge arm, A3, as shown in Figure 3b.

Through the bridge arm transformation in Figure 3, new bridge arms A2 and A3 are derived. Figure 4 shows a family of five-level PTP dual boost converters, which are named as PDBC-I, PDBC-II and PDBC-III. It can be seen in Figure 4 that the PTP dual boost converter is cascaded with Figure 2a, A2, and A3 to generate the PDBCs.

Compared to the traditional five-level converter, a family of PDBCs proposed in this paper reduces the number of MOSFETs by four, so it can effectively reduce the converter loss. It is worth mentioning that the three power flow converters proposed in this paper can all achieve bidirectional power flow after a slight circuit modification.

2.2. Operating Principle

Based on the above analysis, this paper uses the PDBC-II as an example for the working mode analysis. Figure 5 shows the key waveforms of one power cycle, which are corresponding to the six working modes in Figure 6. For ease of analysis, it is assumed that the circuit works in continuous conduction mode (CCM), the inductances and capacitors are large enough, the capacitor voltage U_C1 = U_C2 = U_dc/2 and the DC voltage, U_dc, remains constant. Figure 6 shows the six working modes of PDBC-II, which correspond to 0, ±0.5U_dc and ±U_dc. The six working modes are analyzed as follows.

In Working mode 1, during [t₀, t₁] shown in Figure 5, the grid voltages are u_g > 0, u_aN = 0 and u_bN = u_g. In this mode, the current path is shown in Figure 6a. As shown in Figure 6a, the switch S₁ is ON, the diode D₄ is ON and the other active components are OFF. The capacitors C₁ and C₂ are discharging to the load R_L.

In Working mode 2, during [t₁, t₂] shown in Figure 5, the grid voltages are u_g > 0 and u_aN = u_bN = U_dc/2. In this mode, the current path is shown in Figure 6b. As shown in Figure 6b, the switch S₃ is ON, the body diodes of S₂ and S₄ are ON, the diode D₁ is ON and the other active components are OFF. The capacitor C₁ is charging and C₂ is discharging to the load R_L.

In Working mode 3, during [t₂, t₃] shown in Figure 5, the grid voltages are u_g > 0 and u_aN = u_bN = U_dc. In this mode, the current path is shown in Figure 6c. As shown in Figure 6c, the body diode of S₂ is ON, the diodes D₁ and D₄ are ON and the other active components are OFF. The capacitors C₁ and C₂ are charging, and the AC power supplies to the load R_L.

In Working mode 4, during [t₃, t₄] shown in Figure 5, the grid voltages are u_g < 0, u_bN = u_g and u_bN = 0. In this mode, the current path is shown in Figure 6d. As shown in Figure 6d, the switch S₂ is ON, the body diode of S₃ is ON, the diode D₃ is ON and the other active components are OFF. The capacitors C₁ and C₂ are discharging to the load R_L.

In Working mode 5, during [t₄, t₅] shown in Figure 5, the grid voltage u_g < 0 and u_aN = u_bN = −U_dc/2. In this mode, the current path is shown in Figure 6e. As shown in Figure 6e, the switch S₄ is ON, the body diodes of S₁ and S₃ are ON, the diode D₂ is ON and the other active components are OFF. The capacitor C₂ is charging and C₁ is discharging to the load R_L.

In Working mode 6, during [t₅, t₆] shown in Figure 5, the grid voltages are u_g < 0 and u_aN = u_bN = −U_dc. In this mode, the current path is shown in Figure 6f. As shown in Figure 6f, the body diodes of S₁ and S₃ are ON, the diodes D₂ and D₃ are ON, and the other active components are OFF. The capacitors C₁ and C₂ are charging, and the AC power supplies to the load R_L.

Based on the six working mode analyses above, the switching pulse distribution of the PDBC-II is summarized in

Table 1. Switching pulse distribution of PDBC-II.

Mode	ig	S1	S2	S3	S4	C1	C2	uaN	ubN
1	>0	1	0	0	0	↓	↓	0	ug
2	>0	0	0	1	0	↑	↓	Udc/2	Udc/2
3	>0	0	0	0	0	↑	↑	Udc	Udc
4	<0	0	1	0	0	↓	↓	ug	0
5	<0	0	0	0	1	↓	↑	−Udc/2	−Udc/2
6	<0	0	0	0	0	↑	↑	−Udc	−Udc

. Where “0” and “1” represent switching off and on, “↑” and “↓” represent capacitor charging and discharging, respectively. It can be seen from Table 1 that the PDBC-II has at most one switch ON in each mode, so the PDBC-II has a lower conduction loss.

3. Control and Modulation Strategy

3.1. Control Strategy

In this paper, a double closed-loop control system suited for PDBCs is designed; both the voltage outer loop and the current inner loop adopt the PI controller. The control block diagram of the PDBCs is shown in Figure 7. The transfer function of the PI link in Figure 7 can be expressed as Equation (1),

$$G_{\mathrm{pi}}=({\mathrm{k}}_{\mathrm{p}}\cdot \mathrm{s}+{\mathrm{k}}_{\mathrm{i}})/s,$$

(1)

where k_p and k_i are the proportional and integral coefficients, respectively.

The voltage outer loop is used to keep the output voltage U_dc stable; this output is the reference value of the current inner loop. Firstly, the difference between the DC side voltage, U_dc, and its reference value, U_dc*, is sent into the PI controller to obtain an error signal. Then, the error signal is multiplied by the phase information of the grid voltage u_g. As a result, the input reference signal, i_g*, of the current inner loop is obtained.

The current inner loop is used to ensure that the waveform of i_g is sinusoidal and controls the power factor close to 1. Firstly, the difference between the AC side current, i_g, and the reference signal, i_g*, (the output of the voltage outer loop) is sent to the PI controller. Then, the output of the PI controller is multiplied by kU_dc*. Finally, its output is the difference between this product and the grid voltage, u_g, to get the PWM reference signal, v_ref.

The neutral point (NP) balance of the DC side capacitor is attained by the phase delay control method in this paper. Firstly, the difference between the voltage signals of the capacitors C₁ and C₂ is compared to the reference value. Then, the result is sent to the PI controller to obtain the correction signal, which is added to the modulation wave after limiting the amplitude. Therefore, the NP voltage balance is achieved by adjusting the capacitor charging and discharging time.

3.2. Modulation Strategy

In this paper, the multi-carrier PWM modulation strategy is used to generate a switching pulse distribution for the proposed PDBCs. The PDBC-II is used as an example to illustrate the switching pulse distribution and bridge arm voltages u_aN, u_bN of the multi-carrier PWM modulation strategy, as shown in Figure 8, where v_c1(t), v_c2(t), v_c3(t), v_c4(t) and v_ref(t) represent four carrier signals and the reference signal, respectively. The reference signal, v_ref(t), is compared to v_c1(t), v_c2(t), v_c3(t) and v_c4(t) to obtain the switching pulse waveform of the switches S₁, S₂, S₃ and S₄, respectively.

In the positive half-cycle of the PWM modulation strategy, the duty cycle can be derived from Equations (2)–(6), below. For these Equations, U_g,max, T_on and T_off are the amplitude of AC voltage and the turn on and off times of the switch, respectively. The modulation ratio M and duty ratio D can be defined as follows:

$$M=U_{\mathrm{g},\max }/U_{\mathrm{dc}}$$

(2)

and

$$D=T_{\mathrm{on}}/\left(T_{\mathrm{on}}+T_{\mathrm{off}}\right).$$

(3)

When 0 < v_ref(t) < 0.5, the PDBCs operate alternately in Working modes 1 and 2. At this time, the inductance volt-second balance has the following relationship:

$$\left(u_{\mathrm{g}}-0.5U_{\mathrm{dc}}\right)\cdot T_{\mathrm{on}}=\left(U_{\mathrm{dc}}-u_{\mathrm{g}}\right)\cdot T_{\mathrm{off}}.$$

(4)

The duty cycle D₁ is derived from Equations (2)–(4):

$$D_1=1-2M\sin \left(wt\right).$$

(5)

Similarly, when 0.5 < v_ref(t) < 1, the PDBCs operate alternately in Working modes 2 and 3. The duty cycle D₂ can be obtained as follows:

$$D_2=2-2M\sin \left(wt\right).$$

(6)

When the PDBCs operate in the positive half-cycle, the resulting duty cycle change curve, based on Equations (5) and (6), is shown in Figure 9,where the green curve represents the duty cycle D₁, the yellow curve represents the duty cycle D₂ and θ₁ and θ₂ are the angles of alternation between v_c1(t) and v_c2(t), respectively.

It is assumed that, the amplitude of v_ref(t) is 1 (after normalization) and the θ₁ and θ₂ can be calculated as follows:

$${\mathsf{\theta }}_1=\arcsin 0.5=\frac{\pi }{6}$$

(7)

$$D_2=2-2M\sin \left(wt\right).$$

(8)

4. Performance Analysis

4.1. Voltage Stress Analysis

Based on the working mode analysis of Figure 6, the switch and diode voltage stresses of the three PDBCs are summarized, as shown in

Table 2. Voltage stress of three PDBCs.

Components	PDBC-I	PDBC-II	PDBC-III
S1,2	Udc	Udc	Udc
S3,4	Udc/2	Udc/2	Udc/2
D1,2	Udc	Udc	Udc
D3	Udc	Udc/2	Udc
D4	Udc	Udc	Udc/2

. It can be seen from Table 2 that part of the components voltage stress on the three-level bridge is reduced by half. In addition, the PDBC-II and PDBC-III have three components with voltage stresses of reduced by half, while the PDBC-I has only two components with voltage stresses reduced by half. Therefore, in terms of cost, PDBC-II and PDBC-III have lower costs compared to PDBC-I.

4.2. Current Stress Analysis

To estimate the conduction loss of the switches and diodes, it is necessary to calculate the average and the root mean square (RMS) of the current flowing through the switches and diodes. In this section, the PDBC-II is used as the example in which the current stress analysis is conducted. Figure 10 shows the current stress simulation waveform of PDBC-II in the Matlab/Simulink environment. It is clear, from Figure 9 and Figure 10, that the switching times of the duty cycles D₁ and D₂ are T_g/12 and 5T_g/12 (T_g is one power frequency cycle), respectively. Based on Figure 10, the theoretical derivation of the average value and RMS value of the current flowing through the semiconductor device can be calculated using Equation (9) through (18). For the following calculations, it is assumed that the AC side current is a sine wave, the DC side voltage remains unchanged, and the switching frequency f_s is much greater than the grid frequency f_g.

The current RMS and average of the diodes D₁ and D₂ are calculated using Equation (9):

$$\{\begin{array}{l}{I}_{{}_{\mathrm{D}1,2,\mathrm{rms}}}^{{}^2}=\frac{2}{T_{\mathrm{g}}}\left[{\displaystyle {\int }_0^{\frac{T_{\mathrm{g}}}{12}}\left(1-D_1\right)\cdot i_{\mathrm{g}}{}^2}dt+{{\displaystyle {\int }_{\frac{T_{\mathrm{g}}}{12}}^{\frac{T_{\mathrm{g}}}{4}}\left(\frac{i_{\mathrm{g}}+0.5I_{\mathrm{g},\max }}{2}\right)}}^{2}dt\right]\\ I_{\mathrm{D}1,2,\mathrm{avg}}=\frac{2}{T_{\mathrm{g}}}\left[{\displaystyle {\int }_0^{\frac{T_{\mathrm{g}}}{12}}\left(1-D_1\right)\cdot i_{\mathrm{g}}}dt+{\displaystyle {\int }_{\frac{T_{\mathrm{g}}}{12}}^{\frac{T_{\mathrm{g}}}{4}}\left(\frac{i_{\mathrm{g}}+0.5I_{\mathrm{g},\max }}{2}\right)}dt\right]\end{array}.$$

(9)

Substituting Equation (5) into Equation (9), the current RMS and average of diodes D₁ and D₂ can be obtained:

$$\{\begin{array}{l}{I}_{\mathrm{D}1,2,\mathrm{rms}}=\frac{\sqrt{6}{I}_{\mathrm{g},\max }}{24\sqrt{\pi }}\cdot \sqrt{6\pi +15\sqrt{3}+\left(128-72\sqrt{3}\right)M}\\ I_{\mathrm{D}1,2,\mathrm{avg}}=\frac{I_{\mathrm{g},\max }}{12\pi }\cdot \left[\pi +3\sqrt{3}+\left(2\pi -3\sqrt{3}\right)M\right]\end{array}.$$

(10)

The current RMS and average of the MOSFET S₁ and S₂ are calculated using Equation (11):

$$\{\begin{array}{l}{I}_{{}_{\mathrm{S}1,2,\mathrm{rms}}}^{{}^2}=\frac{2}{T_{\mathrm{g}}}\left[{\displaystyle {\int }_0^{\frac{T_{\mathrm{g}}}{12}}{D}_1\cdot i_{\mathrm{g}}{}^2}dt+{{\displaystyle {\int }_{\frac{7T_{\mathrm{g}}}{12}}^{\frac{3T_{\mathrm{g}}}{4}}\left(\frac{i_{\mathrm{g}}+0.5I_{\mathrm{g},\max }}{2}\right)}}^{2}dt\right]\\ I_{\mathrm{S}1,2,avg}=\frac{2}{T_{\mathrm{g}}}\left[{\displaystyle {\int }_0^{\frac{T_{\mathrm{g}}}{12}}{D}_1\cdot i_{\mathrm{g}}}dt+{\displaystyle {\int }_{\frac{7T_{\mathrm{g}}}{12}}^{\frac{3T_{\mathrm{g}}}{4}}\left|\frac{i_{\mathrm{g}}+I_{\mathrm{g},\max }}{2}\right|}dt\right]\end{array}.$$

(11)

Substituting Equation (5) into Equation (11), the current RMS and average of the MOSFET S₁ and S₂ can be obtained:

$$\{\begin{array}{l}{I}_{\mathrm{S}1,2,\mathrm{rms}}=\frac{\sqrt{6}{I}_{\mathrm{g},\max }}{24\sqrt{\pi }}\cdot \sqrt{14\pi -21\sqrt{3}+\left(72\sqrt{3}-128\right)M}\\ I_{\mathrm{S}1,2\mathrm{avg}}=\frac{I_{\mathrm{g},\max }}{12\pi }\cdot \left[12-\pi -3\sqrt{3}+\left(3\sqrt{3}-2\pi \right)M\right]\end{array}.$$

(12)

The current RMS and average of MOSFET S₃ is calculated using Equation (13):

$$\{\begin{array}{l}{I}_{{}_{\mathrm{S}3,\mathrm{rms}}}^{{}^2}=\frac{4}{T_{\mathrm{g}}}\left[{\displaystyle {\int }_0^{\frac{T_{\mathrm{g}}}{12}}{D}_1\cdot i_{\mathrm{g}}{}^2}dt+{\displaystyle {\int }_{\frac{T_{\mathrm{g}}}{12}}^{\frac{T_{\mathrm{g}}}{4}}{D}_2\cdot i_{\mathrm{g}}{}^2}dt+{\displaystyle {\int }_{\frac{T_{\mathrm{g}}}{2}}^{\frac{3T_{\mathrm{g}}}{4}}{i}_{\mathrm{g}}{}^{2}dt}\right]\\ I_{\mathrm{S}3,\mathrm{avg}}=\frac{2}{T_{\mathrm{g}}}\left[{\displaystyle {\int }_0^{\frac{T_{\mathrm{g}}}{12}}{D}_1\cdot i_{\mathrm{g}}}dt+{\displaystyle {\int }_{\frac{T_{\mathrm{g}}}{12}}^{\frac{T_{\mathrm{g}}}{4}}{D}_2\cdot i_{\mathrm{g}}}dt+{\displaystyle {\int }_{\frac{T_{\mathrm{g}}}{2}}^{\frac{3T_{\mathrm{g}}}{4}}\left|i_{\mathrm{g}}\right|dt}\right]\end{array}.$$

(13)

Substituting Equations (5) and (6) into Equation (13), the current RMS and average of MOSFET S₃ can be obtained:

$$\{\begin{array}{l}{I}_{\mathrm{S}3,\mathrm{rms}}=\frac{I_{\mathrm{g},\max }}{2\sqrt{3\pi }}\cdot \sqrt{3\sqrt{3}+10\pi -32M}\\ I_{\mathrm{S}3,\mathrm{avg}}=\frac{I_{\mathrm{g},\max }}{\pi }\cdot \left(\sqrt{3}+2-\pi M\right)\end{array}.$$

(14)

The current RMS and average of MOSFET S₄ is calculated using Equation (15):

$$\{\begin{array}{l}{I}_{{}_{\mathrm{S}4,\mathrm{rms}}}^{{}^2}=\frac{4}{T_{\mathrm{g}}}\left[{\displaystyle {\int }_0^{\frac{T_{\mathrm{g}}}{12}}{D}_1\cdot i_{\mathrm{g}}{}^2}dt+{\displaystyle {\int }_{\frac{T_{\mathrm{g}}}{12}}^{\frac{T_{\mathrm{g}}}{4}}{D}_2\cdot i_{\mathrm{g}}{}^2}dt\right]\\ I_{\mathrm{S}4,\mathrm{avg}}=\frac{4}{T_{\mathrm{g}}}\left[{\displaystyle {\int }_0^{\frac{T_{\mathrm{g}}}{12}}{D}_1\cdot i_{\mathrm{g}}}dt+{\displaystyle {\int }_{\frac{T_{\mathrm{g}}}{12}}^{\frac{T_{\mathrm{g}}}{4}}{D}_2\cdot i_{\mathrm{g}}}dt\right]\end{array}.$$

(15)

Substituting Equations (5) and (6) into Equation (15), the current RMS and average of MOSFET S₄ can be obtained:

$$\{\begin{array}{l}{I}_{\mathrm{S}4,\mathrm{rms}}=\frac{I_{\mathrm{g},\max }}{2\sqrt{3\pi }}\cdot \sqrt{3\sqrt{3}+10\pi -32M}\\ I_{\mathrm{S}4,\mathrm{avg}}=\frac{I_{\mathrm{g},\max }}{\pi }\cdot \left(\sqrt{3}+2-\pi M\right)\end{array}.$$

(16)

The current RMS and average of diodes D₃ and D₄ current is calculated using Equation (17):

$$\{\begin{array}{l}{I}_{{}_{\mathrm{D}3,4,\mathrm{rms}}}^{{}^2}=\frac{2}{T_{\mathrm{g}}}\left[{\displaystyle {\int }_0^{\frac{T_{\mathrm{g}}}{12}}\left(1-D_1\right)\cdot i_{\mathrm{g}}{}^2}dt+{\displaystyle {\int }_{\frac{T_{\mathrm{g}}}{12}}^{\frac{T_{\mathrm{g}}}{4}}\left(1-D_2\right)\cdot i_{\mathrm{g}}{}^2}dt\right]\\ I_{\mathrm{D}3,4,\mathrm{avg}}=\frac{4}{T_{\mathrm{g}}}\left[{\displaystyle {\int }_0^{\frac{T_{\mathrm{g}}}{12}}\left(1-D_1\right)\cdot i_{\mathrm{g}}}dt+{\displaystyle {\int }_{\frac{T_{\mathrm{g}}}{12}}^{\frac{T_{\mathrm{g}}}{4}}\left(1-D_2\right)\cdot i_{\mathrm{g}}}dt\right]\end{array}.$$

(17)

Substituting Equations (5) and (6) into Equation (17), the current RMS and average of diodes D₃ and D₄ can be obtained:

$$\{\begin{array}{l}{I}_{\mathrm{D}3,4,\mathrm{rms}}=\frac{I_{\mathrm{g},\max }}{2\sqrt{6\pi }}\cdot \sqrt{32M-3\sqrt{3}-4\pi }\\ I_{\mathrm{D}3,4,\mathrm{avg}}=\frac{I_{\mathrm{g},\max }}{2\pi }\cdot \left(\pi M-\sqrt{3}\right)\end{array}.$$

(18)

Figure 11 shows the change curve of the current average and RMS of the switches and diodes with the modulation ratio, M, after normalization of I_g,max. It can be seen from Figure 11 that the current RMS value and average for each of the components have the same trend. Since I_g,max are normalized, the trend shown in Figure 11 is also applicable under different power levels, which is of great significance for studying the working principle of the rectifier.

To verify the correctness of the current stress formula developed in this paper, the current stress value of the switches and diodes is measured in the Matlab/Simulink environment under a 1 kW power rate. Figure 12 shows the comparison between the calculated value and the simulated value of the current stress. It can be seen from Figure 12, the calculated current stress in this paper is consistent with the simulated value, which verifies the correctness of the current stress formula.

4.3. Loss Analysis

Based on the above current stress analysis, this section analyzes the loss and efficiency of the proposed PDBCs. The losses of the MOSFET mainly include conduction losses and switching losses. When the MOSFET is on-state, the on-state resistance, r_ds, results in the conduction losses. The conduction losses P_con can be calculated as (19), where I_S,rms is the RMS value of the current flowing through the MOSFET, which can be obtained from the current stress analysis:

$$P_{\mathrm{con}}=I_{\mathrm{S},\mathrm{rms}}{}^2\cdot r_{\mathrm{ds}}.$$

(19)

During the drain current and voltage conversion processes of the MOSFET, the switching losses are generated. These can be calculated using Equation (20), where U_in, I_o, t_on, t_off, and f_s are the RMS value of the input voltage, the output current, the switching process drain current and voltage conversion crossover time and the switching frequency, respectively:

$$P_{\mathrm{sw}}=0.5U_{\mathrm{in}}\cdot I_{\mathrm{o}}\cdot \left(t_{\mathrm{on}}+t_{off}\right)f_{\mathrm{s}}.$$

(20)

Similarly, the power losses of the diode in a cycle consists mainly of static losses and dynamic losses. For the static losses, since the fast recovery diode is employed in this paper, there are only on-state losses considered. The dynamic losses of the diode can be calculated with Equation (21), where U_f is the forward conduction voltage, I_D,avg is the average value of the diode:

$$P_{\mathrm{Son}}={\displaystyle {\int }_0^{T_{\mathrm{g}}}u\cdot idt}/T_{\mathrm{g}}=U_{\mathrm{f}}\cdot I_{\mathrm{D},\mathrm{avg}}.$$

(21)

Compared to the reverse recovery time, t_r, the forward recovery time, t_f, is negligible; therefore, the turn-on losses can be ignored. The turn-off losses can be calculated using Equation (22), where U_rp and I_rp are the reverse peak voltage and current, t_b is the reverse current fall time:

$$P_{\mathrm{Doff}}={\displaystyle {\int }_{t_0}^{t_2}{u}_{\mathrm{F}}\left(t\right)\cdot i_{\mathrm{F}}\left(t\right)}dt/T_{\mathrm{S}}=0.5U_{\mathrm{rp}}{I}_{\mathrm{rp}}{t}_{\mathrm{b}}{f}_{\mathrm{s}}$$

(22)

In this paper, the MOSFETs and diodes employ IRFP450 and RHRP3060, respectively. According to the data sheets, the parameters for IRFP450 and RHRP3060 are shown in

Table 3. Component parameters.

Components	Parameters	Values
IRFP450	On-state resistance, rds	0.4 Ω
	On-delay time, td(on)	17 ns
	Rise time, tr	47 ns
	Turn-off delay time, td(off)	92 ns
	Fall time, tf	44 ns
RHRP3060	Conduction voltage, Uf	1.7 V
	Reverse peak voltage, Urp	600 V
	Reverse peak current, Irp	250 μA
	Reverse current fall time, tb	18 ns

. The switching frequency is f_s = 20 kHz.

Based on Equation (9) through (22), the losses of the proposed three PDBCs and the CFLC at different output powers are calculated. According to the results of the loss calculations, the efficiency diagrams at different output power rates are generated, as shown in Figure 13. From this, it can be seen that the four circuits reach peak efficiency at approximately 300 W. However, when the output power is over 300 W, the efficiency declines slowly as the output power increases. The peak efficiency of the PDBC-I is 98.27%, which is the highest in the four circuits. In addition, as the output power level increases, the efficiency of the PDBC-I reaches the highest of the four circuits. Therefore, the PDBC-I is more suitable at a higher power rate. Figure 13b shows the experimental efficiency and theoretical efficiency of the PDBC-II circuit, and the efficiency analysis is expressed in the Figure 13b. The maximum experimental efficiency is approx. 96.5%, which is lower than the theoretical efficiency. Since there are actual circuits that exist as auxiliary circuits (drive circuit, sampling circuit, et al.), the actual loss is higher than those in the theoretical analysis results. Nevertheless, in the theoretical calculation and practical experimental results, the trend of overall efficiency distribution is consistent.

5. Experimental Verification

In order to verify the feasibility of the PDBC proposed in this paper and the correctness of the theoretical analysis, PDBC-II [shown in Figure 4b] is selected for corresponding experimental verification, as shown in Figure 14. The experimental circuit design includes an EMI circuit, auxiliary power supply, main power circuit, signal sampling circuit, MOSFET drive circuit and protection control circuit. The controller employs DSP28335 and the MOSFETs and diodes employ IRFP450 and RHRP3060, respectively; the experimental circuit parameters are shown in

Table 4. Main parameters.

Parameters	Label	Value
Input filter inductors	L1, L2	2 mH
DC-side capacitors	C1, C2	1000 μF
Input voltage	ug	RMS 220 V
Output voltage	Udc	400 V
Rated output power	Po	1000 W
Grid frequency	fg	50 Hz
Switching frequency	fs	20 kHz

.

Figure 15 shows the PDBC-II steady-state experimental waveforms of the input and output sides at 1 kW rated power. Figure 15a shows the voltage waveforms of the single-phase AC power supply voltage, u_g, the input side current, i_g, the DC side voltage, U_dc, and U_C1 and U_C2. As seen from Figure 15a, the input power supply voltage, u_g, is in phase with the input side current, i_g, and it is sufficiently consistent to achieve power factor correction. The DC side voltage, U_dc, is stable at 400 V, and the capacitor voltages U_C1 and U_C2 remain dynamically balanced at 200 V. Figure 15b shows the bridge arm voltage u_aN, u_bN waveform and the input inductor current i_L1, i_L2 waveform. As can be seen from Figure 15b, the waveform of inductor current i_L1 phase is ahead 180° of the inductor current i_L2. Similarly, the bridge arm voltage u_aN, u_bN waveform changes in positive and negative half-cycles alternately, which is consistent with Figure 6 and Table 1.

Figure 16 shows the PDBC-II switching pulse distribution experimental waveform. As can be seen from Figure 16, the switches S₁–S₄ have a short, high-frequency switching time. As a result, the switching losses of PDBC-II are relatively low. In addition, the switches S₃ and S₄ symmetrically action in positive and negative half-cycles, which is consistent with the switching pulse distribution of Table 1.

Figure 17 shows the PDBC-II voltage and current stress experimental waveforms of the switches at 1 kW rated power. Figure 17a shows the voltage stress waveforms of the switches S₁–S₄. It can be seen from Figure 17a that the maximum voltage stress of the four switches is U_S1 = U_S2 ≈ 400 V and U_S3 = U_S4 ≈ 200 V; i.e., the partial voltage stress is halved, which is consistent with the voltage stress analysis in Table 2. Figure 17b shows the waveform of the inductor current, diode D₁ current, i_D1 and the switch S₁ current, i_S1. As can be seen here, the waveform of the switch current i_S1 is enveloped by the waveform of the current i_L1 of the inductor L₁ in the positive half cycle. In addition, the currents i_D1 and i_S1 change at high frequencies during the [0, T_g/12] and [5T_g/12, T_g/2] (where T_g is the grid period), which is the same as the simulation waveforms in Figure 10.

Figure 18 shows the THD test results of PDBC-II at 1 kW rated power. As can be seen here, at the switching frequency of 20 kHz, the THD of PDBC-II is 3.2%, which meets the IEC 6100-3-2 standard.

6. Conclusions

In this paper, combining the three-level PTP circuit and the five-level NPC bridge arm, a family of PDBCs is proposed by transforming the NPC bridge arm. The proposed circuit reduces the volume of the filter inductor to increase the power density of the circuit and improves the working efficiency of the circuit. Through comparative analyses of voltage and current stress and loss, the following conclusions are drawn.

(1)

The experimental results show that the PDBCs proposed in this paper have good input and output waveforms at low switching frequency. Therefore, the PDBCs can improve overall efficiency by reducing switching losses.

(2)

The efficiency of the five PDBCs proposed in this paper is higher than that of a CFLC. The PDBC-I has the smallest loss and the highest efficiency, with a peak efficiency of 98.27%, and its overall performance is the best.

(3)

Compared with the conventional three-level PTP circuit, the five PDBCs proposed in this paper have higher power density, and the voltage stress of some devices is reduced by half. In addition, the PDBC-II and PDBC-III have more devices with voltage stresses halved; thus, their cost is lower.