# FPGA-Based Optimization of Industrial Numerical Machine Tool Servo Drives

## Abstract

**:**

## 1. Introduction

## 2. Specificity of Control Systems for Industrial Machine Tools

#### 2.1. The Structure of a Distributed Control System

#### 2.2. Real-Time Ethernet

## 3. Experimental Research

#### 3.1. Architecture and Fundamental Properties of FPGA Devices

#### 3.2. Properties and Architecture of an Electric Servo Drive Controller

#### 3.3. Methods of Control Algorithm Implementation on FPGA

#### 3.4. The Applied Soft-Core Superscalar Architecture

- $\mathrm{PolyInit}\phantom{\rule{3.33333pt}{0ex}}n,m,Addr$—is a dedicated instruction for hardware acceleration of the LTSE algorithm. It implements the initialization of the n-th order LTSE with the division of the approximation domain into ${2}^{m}$ segments. The coefficients of the polynomials used in the approximation are listed in the two-dimensional array indicated as the last argument of the instruction.
- M1_A $Addr$—this is the operation of addressing the first of the two memory blocks to prepare for the read operation in the next clock cycle. The symbol Addr denotes the address of the variable placed in the M1 memory block. The corresponding instruction for the second memory block is labeled M2_A.
- M1_RI $\mathrm{R}a$—is the actual operation of reading from memory to the general register with the index $a=0\dots 15$ and simultaneous addressing of the next memory location by address increment. The corresponding instruction for the second memory block is M2_RI.
- $\mathrm{R}o=\mathrm{R}a\ast \mathrm{R}b({i}_{a},{i}_{b},{i}_{o})$—fixed-point multiplication with scaling, where: $a,b,o=0\dots 15$ are the indexes of the universal registers identifying the first and second arguments and the result register, while ${i}_{a},{i}_{b},{i}_{o}$ are the i parameters defining the format of the processed fixed-point numbers, following the Fxi_n notation [3]. In this notation, the ‘i’ parameter describes the position of the binary point counting to the right, starting from the left side of the binary word. In the research described in this paper, 32-bit words were used to represent the values of processed signals. In this case, the value of n was 32. However, 16-bit words were used to represent constant parameters, so, in that case, the value of n was 16.This fixed-point multiplication is performed by the FX-MULT unit shown in Figure 8. The first part of the operation is integer multiplication, which results in a 48-bit number written to the internal register (REG) of the FX-MULT unit. To obtain the expected output format, this result will be shifted to the right by the number of positions expressed by Formula (1). This integer value is determined during the code compilation stage and placed in the SCALE COEFFICIENT field of the binary instruction intended to be executed by the FX-MULT unit.$${s}_{M}=(32-{i}_{a})+(16-{i}_{b})-(32-{i}_{o})$$
- $\mathrm{R}a+=\mathrm{R}b({i}_{a},{i}_{b})$—these are integer addition operations where the second argument is automatically scaled to the format of the first argument. The subtraction operation looks similar. This operation is shown in Figure 9 and has the predetermined requirement that ${i}_{a}\ge {i}_{b}$. In this case, the “SCALE COEFFICIENT” field contained in the code of the instruction describes the binary left shift value. This value is determined by Formula (2) at the code compilation stage.$${s}_{A}={i}_{a}-{i}_{b}.$$

#### 3.5. Algorithm Implementation Details

Listing 1. Fragment of C-code for LTSE algorithm implementation on a DSP unit. | |

1 | #define POLY_ORDER 5 |

2 | float LTSE_sin ( float x ) |

3 | { |

4 | unsigned int segIndex ; |

5 | /* Convert to integer format and use the three |

6 | most significant bits as the segment index . */ |

7 | segIndex = x * ONE_OVER_TWO_PI_FX1_16 ; |

8 | segIndex = ( segIndex >> 13) & 0x0007u ; |

9 | /* The Horner ’ s scheme . */ |

10 | float sum = LTSE_Coeff [ segIndex ] [ 0 ] ; // y0 |

11 | x −= LTSE_Coeff [ segIndex ] [ 0 ] ; |

12 | int i ; |

13 | for ( i=POLY_ORDER; i >=1; i −−) |

14 | { |

15 | sum = sum ∗ x + LTSE_Coeff [ segIndex ] [ i ] ; |

16 | } |

17 | return sum; |

18 | } |

Listing 2. Fragment of FXU code for LTSE algorithm implementation on SC-SS unit. | |

1 | PolyIni t 5 , 3 , LTSE_Coeff ; M1_A x ; |

2 | M1_RI R0 ; // Load the argument and calculate the segment index . |

3 | M2_RI R6 ; // Load the value of x0 . |

4 | R0 −= R6 ; // Calculate the value of z . |

5 | R3 = R0∗R0 ( 2 , 2 , 2 ) ; M2_RI R7 ; // Calculate the value of z^2 and load the value of y0 . |

6 | R1 = R0 ; R2 = R0 ; M2_RI R8 ; // Load the value of C1 . |

7 | R4 = R1∗R8 ( 2 , 2 , 2 ) ; R1 = R1 ∗ R3 ( 2 , 2 , 2 ) ; M2_RI R8 ; // Use C1 , load C2 |

8 | R5 = R2∗R8 ( 2 , 2 , 2 ) ; R2 = R2 ∗ R3 ( 2 , 2 , 2 ) ; M2_RI R8 ; // Use C2 , load C3 |

9 | R7 += R4 ( 2 , 2 ) ; R4 = R1∗R8 ( 2 , 2 , 2 ) ; R1 = R1∗R0 ( 0 , 2 , 2 ) ; M2_RI R8 ; // Use C3 , load C4 |

10 | R7 += R5 ( 2 , 2 ) ; R5 = R2∗R8 ( 2 , 0 , 2 ) ; R2 = R2∗R0( −2 , 0 , 2 ) ; M2_RI R8 ; // Use C4 , load C5 |

11 | R7 += R4 ( 2 , 2 ) ; R4 = R1∗R8( 2 , −2 , 2 ) ; // Use C5 |

12 | R7 += R5 ( 2 , 2 ) ; |

13 | R7 += R4 ( 2 , 2 ) ; // Result is in register R7 . |

#### 3.6. Analysis of the Obtained Results

## 4. Conclusions

- Description of the architecture, specific features, and requirements imposed on control systems of modern industrial CNC machines.
- Identifying areas where the control system can be developed to improve machining precision, introduce new functionalities, and enhance diagnostic and service operations.
- Diagnosis of the limitations of controllers typically used in servo drives based on microcontrollers or signal processors collaborating with application-specific integrated circuits (ASICs) regarding the feasibility of implementing the proposed new solutions.
- Designing and implementing a solution based on FPGA technology to eliminate the above-mentioned limitations. This solution involves proper configuration and utilization of the SC-SS unit for hardware–software processing of the servo drive control algorithm, as well as integrating the SC-SS unit and the RTE module within a common FPGA structure.
- Designing and conducting comprehensive experimental studies on three distinct digital platforms. Two of the evaluated platforms are integrated into the control systems of existing CNC machines available in the commercial market. The tests conducted on these platforms exhibit high reliability due to their execution under real operational conditions of the machine tool control system.
- Conducting a rigorous analysis of the obtained results, considering the achieved processing efficiency of the controllers, real-time communication interface delays, the amount of consumed electrical power, the complexity of the electronic printed circuit board, and the cost of digital components.

## Funding

## Data Availability Statement

## Conflicts of Interest

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**Figure 1.**Modern industrial machine tools: (

**a**) HSM milling machine, (

**b**) WaterJet cutter and (

**c**) laser fiber cutter.

**Figure 4.**Photos of a compact electric servo drive controller built on the basis of the FPGA system.

**Figure 7.**Description of the functions of individual fields of the 128-bit instruction word in the proposed configuration of the SC-SS unit.

FPGA Part Number | DSP Slices | CLB Slices | BRAMs | Approx. Price [USD] |
---|---|---|---|---|

XC6SLX9 | 16 | 1430 | 32 | 30 |

XC6SLX45 | 58 | 6822 | 116 | 110 |

XC6SLX150 | 180 | 23,038 | 268 | 400 |

XC6VLX240T | 768 | 37,680 | 832 | 4k |

XC6VSX475T | 2016 | 74,400 | 2128 | 20k |

Selected Parameters | MCU | DSP | FPGA |
---|---|---|---|

The amount of consumed electrical power [W] | $1.2$ | $2.4$ | $1.4$ |

Approximate cost of the key digital components [USD] | 60 | 91 | 120 |

**Table 3.**Processing time of selected fragments of the servo drive control algorithm implemented on various digital platforms. A lower value means higher performance.

Servo Code Functional Block | MCU | DSP | FPGA (SC-SS) |
---|---|---|---|

Sine and cosine | 1.18 μs | 0.23 μs | 0.31 μs |

Clarke and Park | 0.33 μs | 0.09 μs | 0.18 μs |

Inv. Park and SVM | 0.84 μs | 0.21 μs | 0.61 μs |

Dual-channel PI | 0.98 μs | 0.30 μs | 0.48 μs |

Data transfer delay 28 B/256 B | 1.40 μs/12.80 μs | 0.77 μs/7.04 μs | 0.10 μs/0.81 μs |

The sum of the above 28 B/256 B | 4.73 μs/16.13 μs | 1.60 μs/7.87 μs | 1.68 μs/2.39 μs |

Features | MCU/DSP + ASICs | FPGA |
---|---|---|

Processing performance (total) | medium to high | high (SC-SS) to very high (FHD) |

Design comfort | high | limited (SC-SS) low (FHD) |

Compactness of the device | no | yes |

Development potential | limited | large |

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**MDPI and ACS Style**

Przybył, A.
FPGA-Based Optimization of Industrial Numerical Machine Tool Servo Drives. *Electronics* **2023**, *12*, 3585.
https://doi.org/10.3390/electronics12173585

**AMA Style**

Przybył A.
FPGA-Based Optimization of Industrial Numerical Machine Tool Servo Drives. *Electronics*. 2023; 12(17):3585.
https://doi.org/10.3390/electronics12173585

**Chicago/Turabian Style**

Przybył, Andrzej.
2023. "FPGA-Based Optimization of Industrial Numerical Machine Tool Servo Drives" *Electronics* 12, no. 17: 3585.
https://doi.org/10.3390/electronics12173585