Phase-Shifted Energy Balance Control for Multilevel Inverters in Grid-Connected PV Systems

Abstract

Cascaded multilevel converters are promising candidates for grid-connected PV systems, but low-frequency ripples may exist in a DC link. Such ripples are not just inherent; they can occur due to environmental factors, such as variations in a certain range of irradiance of the PV. To address this issue, this article proposes a clock phase-shifted (CPS) energy balance control method for grid-connected cascaded multilevel inverters for photovoltaic (PV) systems. The proposed control scheme can prevent the low-frequency ripple of the DC link propagating to the power grid. Furthermore, it is feasible in principle and no adjustment of the control parameters is needed. The simulation and experimental results verify the effectiveness and feasibility of the proposed approach.

1. Introduction

Motivated by environmental concerns, the promotion of distributed generation (DG) from renewable resources in power grids, such as solar and wind, is rapidly increasing [1,2]. As the cost per watt of PV systems has continuously reduced, the installed capacity of grid-connected solar PV energy conversion systems has increased substantially in recent years [3]. Thus, multilevel inverters are being investigated as an interesting option for grid-connected PV systems. Among the available multilevel converter topologies [4], the cascaded multilevel topology—in particular, the novel CSD multilevel topology proposed in [5]—is particularly attractive for grid-connected PV applications for the following reasons. 1. The required output voltage level can be achieved without a transformer. 2. The DC link voltages can be independently controlled, which is more suitable for the PV modules operate under mismatching conditions such as in the case of partial shadowing. 3. Compared to other cascaded multilevel inverter topologies [6,7,8], the novel CSD multilevel topology proposed in [5] can produce the same voltage levels with a lower number of switches and remove the high-voltage spikes by adding a spike remove switch.

However, the cascaded topology tends to require more rigorous control methods, particularly working in situations that accommodate for the motor drives in PV systems. The conventional phase-shifted PWM (PS-PWM), whose ability to suppress low-frequency fluctuations on the input side is weak, will undoubtedly lead to low-order harmonics pollution in the power grid, which causes distortions of the grid currents [9,10]. To resolve this problem, the most direct way is to increase the value of the capacitor of the DC link or add a passive filter [11,12], which will lead to a reduction in the system reliability. Active filtering methods have been proposed based on power electronic devices, which suppress low-frequency ripples by adding DC active power filters in the DC port of each cascaded unit [13,14]. Additionally, DC–DC converters have also been introduced between the DC link and each cascaded unit. By using specific control methods, the intermediate capacitance is forced to take almost all the double-frequency power, thus achieving the goal of the ripple suppression of low-frequency input currents [15,16]. However, these methods present certain disadvantages related to the volume of the whole system, cost or structural complexity. In medium-voltage (MV) motor drives, the low-frequency pulsating power is reduced by replacing the half-bridge submodules (SMs) with full-bridge submodules. However, this undoubtedly increases the number of switches [17]. A new control strategy based on model predictive control (MPC) was proposed in [18]; using this strategy, the capacitor voltage ripple can be suppressed. In [19], combined with the intercross control structure, wherein the d-q currents are controlled by the feedforward decoupling control structure, the low-frequency voltage ripple can be suppressed in cascaded H-bridge (CHB) multilevel converters for large-scale grid-connected PV systems.

This work aimed to eliminate the low-frequency harmonic interferences caused by the low-frequency harmonic voltage ripples in the DC link. Thus, the proposed control method is useful as it helps to avoid sensitivity to environmental factors, such as light, temperature, etc. This is especially true for the PV system. This article is a conference extended version of [20] and includes a more detailed theoretical analysis of the proposed control method based on the energy balance, a more advanced (17-level) simulation and experimental verification of the proposed control scheme. The remainder of this article is organized as follows. Section 2 introduces the CSD multilevel topology. And based on the CSD topology, the control equation of the proposed control method is analyzed. The design and implementation of the proposed CPS energy balance control method are illustrated in Section 3. Section 4 and Section 5 present the simulation and experimental results. Conclusions are provided in Section 6.

2. Deriving the Control Equation Based on the CSD Multilevel Topology

Figure 1 shows the block diagram of the PV CSD multilevel inverter with the proposed CPS energy balance control method. In Figure 1, the PV panels carry out the task of maximum power point tracking (MPPT). Because the goal of this research was to present a novel control method for the inverter, the MPPT stage was not implemented but emulated by DC sources with fluctuations, reflecting the low-harmonic voltage ripple.

As shown in Figure 1, the CSD topology comprises an n cascaded switched-diode converter, a spike removal switch ${\mathrm{S}}_{\mathrm{g}}$ and a full-bridge inverter, where n is the number of cascaded basic units. The basic unit 1 shown in Figure 1 consists of a PV string and a capacitor, which are emulated by a DC voltage source with fluctuations, a switch ${\mathrm{S}}_{11}$ with its internal reverse diode and a diode ${\mathrm{D}}_{11}$. Then, $u_{\mathrm{o}1}$ of the basic unit 1 will be one of two values, i.e., $u_{\mathrm{c}1}$ when ${\mathrm{S}}_{11}$ conducts and 0 when ${\mathrm{S}}_{11}$ is turned off. The spike-removal switch ${\mathrm{S}}_{\mathrm{g}}$ provides a path for the reverse load current. It is connected between unit 2 and unit n and occurs when ${\mathrm{S}}_{11}$ is on and the other switches are off.

Table 1. Values of $i_{\mathrm{g}}$ with respect to switch states of the second stage [20].

State	Switches States				${\mathit{u}}_{\mathbf{o}}$	$\mathbf{Condition}$
	${\mathrm{S}}_1$	${\mathrm{S}}_2$	${\mathrm{S}}_3$	${\mathrm{S}}_4$
1	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{off}$	$\mathrm{on}$	$i_{\mathrm{g}}$	$i_{\mathrm{gref}}⩾0$
2	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{on}$	$\mathrm{off}$	$-i_{\mathrm{g}}$	$i_{\mathrm{gref}}<0$

shows the switch states of the second stage. As shown in Table 1, the positive and negative halves of output waveforms are detected during the second stage of the multilevel inverter by comparing the reference current $i_{\mathrm{gref}}$ with zero. Thus, the proposed CPS energy balance control method is designed for just the first stage, which only considers the positive state. The main principle of the proposed control method is to force the grid current to be equal to a desired value.

The following control equation is based on cascaded unit 1, as shown in Figure 2, which is the shaded part in Figure 1. For cascaded unit 1, the energy balance means that, during the $n^{\mathrm{th}}$ switching cycle $[(n-1)T_{\mathrm{s}},n{T}_{\mathrm{s}})$, where $T_{\mathrm{s}}$ represents the switching cycle, the energy injected into the circuit is kept equal to the sum of the energy fed into the grid $W_{\mathrm{g}1}\left(n\right)$, the stored energy of $L_1$ and $L_2$ as $\Delta W_{\ell }\left(n\right)$ and that of the capacitor C as $\Delta W_{\mathrm{c}}\left(n\right)$:

$$W_{\mathrm{in}1}\left(n\right)=W_{\mathrm{g}1}\left(n\right)+\Delta W_{\ell }\left(n\right)+\Delta W_{\mathrm{c}}\left(n\right)(n=1,2,\cdots )$$

(1)

The circuit in Figure 2 can be seen as a buck converter, where $u_{\mathrm{c}1}$ emulates the PV panels. As a buck converter, during the $n^{\mathrm{th}}$ switching cycle, cascaded unit 1 operates in two states:

State 1: −${\mathrm{S}}_{11}$ is on for duration $t_{\mathrm{on}1}\left(n\right)$ and, in this switching state, the energy is injected into the circuit and $i_{\ell }$ flows through the loop ($u_{\mathrm{c}1}\to {\mathrm{S}}_{11}\to {\mathrm{L}}_1\to \mathrm{C}\Vert {\mathrm{L}}_2$ and $u_{\mathrm{g}}\to u_{\mathrm{c}1}$). $L_1$ and $L_2$ are charged, the grid is fed energy and $u_{\mathrm{o}1}$ is derived using (2):

$$u_{\mathrm{o}1}\left(t\right)=u_{\mathrm{c}1}(t\in [(n-1)T_{\mathrm{s}},(n-1)T_{\mathrm{s}}+t_{\mathrm{on}1}\left(n\right))$$

(2)

State 2: −${\mathrm{S}}_{11}$ is off for duration $t_{\mathrm{off}1}\left(n\right)$ and, in this switching state, no energy is fed into the circuit; however, $i_{\ell }$ flows through the loop (${\mathrm{D}}_{11}\to \mathrm{L}\to \mathrm{C}\Vert \mathrm{R}\to {\mathrm{D}}_{11}$). $L_1$ and $L_2$ are discharged, the grid is fed energy and $u_{\mathrm{o}1}$ is obtained using

$$u_{\mathrm{o}1}\left(t\right)=0(t\in [(n-1)T_{\mathrm{s}}+t_{\mathrm{on}1}\left(n\right),n{T}_{\mathrm{s}})$$

(3)

According to the above state analysis, the values of $W_{\mathrm{in}1}\left(n\right)$, $W_{\mathrm{grid}1}\left(n\right)$ during the nth switching cycle can be obtained as follows:

$$W_{\mathrm{in}1}\left(n\right)={\int }_{(n-1)T_{\mathrm{s}}}^{(n-1)T_{\mathrm{s}}+t_{\mathrm{on}1}\left(n\right)}{u}_{\mathrm{o}1}\left(t\right)i\left(t\right)dt$$

(4)

substituting $i=|i_{\ell }\left(t\right)|$ into (4) results in:

$$W_{\mathrm{in}1}\left(n\right)={\int }_{(n-1)T_{\mathrm{s}}}^{(n-1)T_{\mathrm{s}}+t_{\mathrm{on}1}\left(n\right)}{u}_{\mathrm{c}1}\left(t\right)\left|i_{\ell }\left(t\right)\right|dt$$

(5)

$$W_{\mathrm{g}1}\left(n\right)={\int }_{(n-1)T_{\mathrm{s}}}^{(n-1)T_{\mathrm{s}}+T_{\mathrm{s}}}|{\displaystyle \frac{1}{n}}{u}_{\mathrm{g}}\left(t\right)\left|\right|i_{\mathrm{gref}}\left(t\right)|dt$$

(6)

Additionally, the purpose of this control mechanism is to ensure that the grid current $i_{\mathrm{g}}\left(n\right)$ is equal to the reference grid current $i_{\mathrm{gref}}$; thus, $i_{\mathrm{g}}$ can be substituted by $i_{\mathrm{gref}}$, which is regarded as a constant value in a switching cycle. Then, $u_{\ell 2}$ can be calculated as follows:

$$u_{\ell 2}=L{\displaystyle \frac{d{i}_{\mathrm{g}}}{dt}}=L{\displaystyle \frac{d{i}_{\mathrm{gref}}}{dt}}=0$$

(7)

Then, $u_{\mathrm{c}}$ is calculated as follows:

$$u_{\mathrm{c}}=u_{\ell 2}+u_{\mathrm{g}}=u_{\mathrm{g}}$$

(8)

where $u_{\mathrm{g}}$ is the grid voltage, which can also be regarded as a constant value in a switching cycle; thus, $i_{\mathrm{c}}$ can be obtained in the following way:

$$i_{\mathrm{c}}=C{\displaystyle \frac{d{u}_{\mathrm{c}}}{dt}}=C{\displaystyle \frac{d{u}_{\mathrm{g}}}{dt}}=0$$

(9)

Then, $i_{\ell 1}$ is calculated as follows:

$$i_{\ell 1}=i_{\mathrm{c}}+i_{\mathrm{g}}=i_{\mathrm{g}}$$

(10)

From (10), it can be seen that $i_{\ell 1}$ is also regarded as a constant value since $i_{\mathrm{g}}$ can be substituted by $i_{\mathrm{gref}}$ as mentioned above. Then, $u_{\ell 1}$ can be obtained as follows:

$$u_{\ell 1}=L{\displaystyle \frac{d{i}_{\ell 1}}{dt}}=0$$

(11)

In a buck converter, the inductors work in the entire cycle during each switching cycle n; as a result, the stored energy of the inductor is calculated using (12):

$$\begin{array}{cc}\hfill \Delta W_{\ell }\left(t\right)& =\Delta W_{\ell 1}+\Delta W_{\ell 2}\hfill \\ \hfill & ={\int }_{(n-1)T_{\mathrm{s}}}^{(n-1)T_{\mathrm{s}}+T_{\mathrm{s}}}{u}_{\ell 1}{i}_{\ell 1}dt+{\int }_{(n-1)T_{\mathrm{s}}}^{(n-1)T_{\mathrm{s}}+T_{\mathrm{s}}}{u}_{\ell 2}{i}_{\ell 2}dt\hfill \end{array}$$

(12)

By substituting (7) and (11) into (12), $\Delta W_{\ell }\left(n\right)$ can be derived as follows:

$$\Delta W_{\ell }\left(n\right)=0$$

(13)

Similarly, $\Delta W_{\mathrm{c}}\left(n\right)$ can be obtained as $\Delta W_{\mathrm{c}}\left(n\right)=0$.

Thus, $\Delta W_{\ell }\left(n\right)$ and $\Delta W_{\mathrm{c}}\left(n\right)$ in (1) can be ignored and, combining the aforementioned state analysis, the energy conservation in the circuit can be realized by controlling $u_{\mathrm{o}1}$, which is expressed in (14):

$$\begin{array}{c}\hfill {\int }_{(n-1)T_{\mathrm{s}}}^{n{T}_{\mathrm{s}}}{u}_{\mathrm{o}1}\left(t\right)|i_{\ell }\left(t\right)|dt=|u_{\mathrm{g}}\left|\right|i_{\mathrm{gref}}\left(t\right)|T_{\mathrm{s}}(n=1,2,\cdots )\end{array}$$

(14)

3. The Design and Implementation of the Proposed CPS Energy Balance Control Method

The control Equation (14) can be implemented using comparison and integration, as shown in Figure 2. The control implementation for cascaded unit 1 is described as follows: at the beginning of a switching cycle, when the pulse of clock 1 arrives, ${\mathrm{S}}_{11}$ is turned on and the integrator starts working, whose value $W_{\mathrm{int}1}\left(k\right)$ increases from its initial value. $W_{\mathrm{int}1}\left(t\right)$ is compared with the control reference $W_{\mathrm{g}1}$ instantaneously. At the instant when $W_{\mathrm{int}1}\left(t\right)$ reaches $W_{\mathrm{g}1}$, the output of the comparator changes to a low level, which turns off ${\mathrm{S}}_{11}$. Then, ${\mathrm{S}}_{11}$ is switched from the on state to the off state. ${\mathrm{S}}_{11}$ is switched off until the arrival of the next clock pulse, which resets the integrator and starts the ${(n+1)}^{\mathrm{th}}$ switching cycle.

As shown in Figure 1, $u_{\mathrm{o}1}$ can be replaced by $\overline{u}$, which is the average value of all the values of the DC link ($u_{\mathrm{c}1}$, $···$, $u_{\mathrm{c}1}$, $u_{\mathrm{cn}}$); then, (14) can be rewritten as follows:

$$\begin{array}{c}\hfill {\int }_{(n-1)T_{\mathrm{s}}}^{n{T}_{\mathrm{s}}}\overline{u}\left(t\right)|i_{\ell }\left(t\right)|dt=|u_{\mathrm{g}}\left|\right|i_{\mathrm{gref}}\left(t\right)|T_{\mathrm{s}}(n=1,2,\cdots )\end{array}$$

(15)

Thus, the input value of all the reset integrators can be obtained using (15). Additionally, the controls of the other cascaded units are similar to that of cascaded unit 1, but with a phase-shift for $T_{\mathrm{s}}/n$ of the clock pulse. Furthermore, the spike removal switch ${\mathrm{S}}_{\mathrm{g}}$, which is connected between unit 2 and unit n, is controlled by operations when ${\mathrm{S}}_{11}$ is on and ${\mathrm{S}}_{21}$ to $S_{\mathit{n}1}$ is off.

4. Simulation Results

In order to verify the feasibility and performances of the proposed control method, a 5-level and a 17-level CSD topology were developed using MATLAB/Simulink. During the simulation, the MPPT stage was not implemented but simulated by DC sources with fluctuations. A comparative study using a conventional PS-PWM control method is presented to evaluate the performances of the proposed method. The PS-PWM grid-connected system was designed using the SISO tool of MATLAB with phase and amplitude margins of ${32.7}^{\circ }$ and 7.61 dB, respectively.

4.1. Simulation Results of the 5-Level Topology

The diagram of a 5-level CSD topology is shown in Figure 3. It comprises a two-cascaded switched-diode converter, a spike removal switch ${\mathrm{S}}_{\mathrm{g}}$ and a full-bridge inverter. The spike removal switch ${\mathrm{S}}_{\mathrm{g}}$ is connected between E and F and operates when ${\mathrm{S}}_{11}$ is on and ${\mathrm{S}}_{21}$ is off. The circuit parameters are listed in

Table 2. Circuit parameters of the 5-level CSD topology.

${\mathit{u}}_{\mathbf{c}1}={\mathit{u}}_{\mathbf{c}2}$	${\mathit{L}}_1$	${\mathit{L}}_2$	C	${\mathit{u}}_{\mathbf{g}}$	${\mathit{f}}_{\mathbf{c}}$
$50\mathrm{V}$	$4\mathrm{mH}$	$2\mathrm{mH}$	$2.2\mathsf{\mu }F$	$80\mathrm{V}$	$2500\mathrm{Hz}$

Where $80\mathrm{V}$ is the amplitude of $u_{\mathrm{g}}$, and its frequency is $50\mathrm{Hz}$.

.

Figure 4 and Figure 5 show the simulation results of the operation of the PV cascaded multilevel grid-connected inverter with the proposed control method. From Figure 4, it can be observed that, as the sum of the output value of all the cascaded units, $u_{\mathrm{AB}}$ and the current i of the first-stage have zero and positive values. Figure 5 shows the waveform of $u_{\mathrm{CD}}$, which is a 5-level stepped waveform. The waveform of $i_{\mathrm{g}}$ in Figure 5 illustrates that, after the $L-C-L$ filter, it is sinusoidal and in phase with the grid voltage.

The THD of the stepped output voltage waveform $u_{\mathrm{CD}}$ of the 5-level multilevel inverter is 38.39%, as shown in Figure 6. The frequencies of the main harmonics are twice the switching frequency ($2500\mathrm{Hz}$) and its multiples. After the $L-C-L$ filter, the THD of $i_{\mathrm{g}}$ is 3.09%, as shown in Figure 7. Additionally, the calculation result of the power factor is 99.98%, which means that the power factor is almost unity.

From these results, it is clear that the proposed CPS energy balance control method is feasible for the CSD multilevel inverter for the grid-connected PV system.

Figure 8 show the 5-level simulation results of the suppression ability against second-order harmonics in a DC link, which is realized by adding second-frequency harmonic ripples into the DC link voltages of each cascaded unit. Figure 8 illustrates the results under the case where the DC link is added with a second-harmonic voltage ripple, which has an amplitude of $8\mathrm{V}$. Although the distortion caused by this harmonic is not obvious from the waveform, the FFT analysis of Figure 9 and Figure 10 illustrate that $i_{\mathrm{g}}$ using PS-PWM contains corresponding harmonics to those of the DC link voltage, whose THD has increased to 4.17%. In contrast, the THD of $i_{\mathrm{g}}$ using the proposed control method is 3.17%, with a slight increase.

Although the harmonics that the PV system may contain are mainly the second-harmonic voltage ripples, other low-frequency harmonics may also be caused by environmental factors; for example, the irradiance level varies in a certain range. Thus, third-harmonic voltage ripples with an amplitude of $8\mathrm{V}$ are added in DC links of the 5-level topology. The simulation results are shown in Figure 11. From the waveform in Figure 11a, it can be seen that, using the proposed control method, $i_{\mathrm{g}}$ remains a consistent output, and the FFT analysis of Figure 12 illustrates that the THD is 3.18%, with a slight increase. In contrast, the waveform when using the PS-PWM control method is distorted obviously, as shown in Figure 11b. Additionally, from the FFT analysis of Figure 13, it can be observed that the corresponding harmonics propagate from the DC link to the power grid, leading the THD to increase to 5.17%.

4.2. Simulation Results of the 17-Level Topology

The 17-level CSD topology is similar to that of the 5-level topology shown in Figure 3. However, it comprises an eight-cascaded switched-diode converter, a spike removal switch ${\mathrm{S}}_{\mathrm{g}}$ and a full-bridge inverter. The spike removal switch ${\mathrm{S}}_{\mathrm{g}}$ is connected between unit 2 and 8 and works when ${\mathrm{S}}_{11}$ is on and all the other switches are off. The circuit parameters are listed in

Table 3. Circuit parameters of 17-level CSD topology.

${\mathit{u}}_{\mathbf{c}1}={\mathit{u}}_{\mathbf{c}2}=\dots ={\mathit{u}}_{\mathbf{c}8}$	${\mathit{L}}_1$	${\mathit{L}}_2$	C	${\mathit{u}}_{\mathbf{g}}$	${\mathit{f}}_{\mathbf{c}}$
$50\mathrm{V}$	$1.6\mathrm{mH}$	$0.8\mathrm{mH}$	1.1 $\mathsf{\mu }$F	$360\mathrm{V}$	$2500\mathrm{Hz}$

Where $360\mathrm{V}$ is the amplitude of $u_{\mathrm{g}}$, and its frequency is $50\mathrm{Hz}$.

.

Figure 14 and Figure 15 show the simulation results of the operation of the 17-level CSD cascaded multilevel grid-connected inverter with the proposed control method. From Figure 14, it can be observed that, as the sum of the output value of all the cascaded units, $u_{\mathrm{AB}}$ and the current i of the first stage has zero and positive values. Additionally, Figure 15 shows the waveform of $u_{\mathrm{CD}}$, which is a 17-level stepped waveform. The waveform of $i_{\mathrm{g}}$ in Figure 15 illustrates that, after the $L-C-L$ filter, it is sinusoidal and in phase with the grid voltage.

The THD of the stepped output voltage waveform $u_{\mathrm{CD}}$ of the 17-level multilevel inverter is 7.88%, as shown in Figure 16. The frequencies of the main harmonics are eight times the switching frequency ($2500\mathrm{Hz}$) and its multiples. Compared with the THD of $u_{\mathrm{CD}}$ of the 5-level multilevel inverter, the THD is lower and the frequencies that the main harmonics focus on move backward. Figure 17 shows the THD of $i_{\mathrm{g}}$, which is 1.36%. Additionally, the calculation result of the power factor is 99.982%, which means that the power factor is close to unity.

From these results, it is clear that the proposed CPS energy balance control method is feasible for the CSD multilevel inverter for the grid-connected PV system.

Figure 18 illustrates the results of the case where the DC link is added with a second-harmonic voltage ripple, which has an amplitude of $8\mathrm{V}$. Although the distortion caused by this harmonic is not obvious, as shown in the waveforms, the FFT analysis of Figure 19 and Figure 20 illustrates that $i_{\mathrm{g}}$ using PS-PWM contains corresponding harmonics to those of the DC link voltage, for which the THD increased to 2.92%. In contrast, the THD of $i_{\mathrm{g}}$ using the proposed control method is 1.49%, with a slight increase.

Figure 21 illustrates the results of the case where the DC link is added with a third-harmonic voltage ripple, which has an amplitude of $8\mathrm{V}$. From the waveform in Figure 21a, it can be seen that, using the proposed control method, $i_{\mathrm{g}}$ is a consistent output, and the FFT analysis of Figure 22 illustrates that the THD is 1.41%, with a slight increase. In contrast, the waveform when using the PS-PWM control method is distorted clearly, as shown in Figure 21b. Additionally, from the FFT analysis of Figure 23, it can be observed that corresponding harmonics propagate from the DC link to the power grid, leading to the THD increasing to 4.25%.

5. Experimental Verification

According to the parameters listed in Table 2, a 5-level experimental prototype was built, as shown in Figure 24. In the experiment, a real-time implementation of the hardware-in-the-loop (HIL) system was used to verify the proposed CPS energy balance control method. The model of a 5-level CSD topology was developed in the electromagnetic transient simulation software StarSim, and ran on a PXI-FPGA-based real time HIL system with a time step of $1\times {10}^{-3}$. The HIL testing system parameters were the same as the ones in the simulation tests. The control methods were implemented using the RTlab 5600 platform. The sampling period of the controller and the switching frequency were selected as $20\mathsf{\mu }$s and $2.5\mathrm{kHz}$, respectively. The connection of the HIL simulation system and RTlab 5600 was implemented by using many IO channels. The oscilloscope measured the output voltage and grid current of the 5-level CSD topology.

Figure 25 shows the experimental results of the 5-level topology using the proposed control method. The stepped voltage, grid voltage and current are depicted. It can be observed that the experimental results are consistent with the simulation results in Figure 5. A 5-level staircase waveform was implemented, the grid current was sinusoidal and synchronization took place with the grid voltage. The results of the FFT analysis illustrate that the THD is 40.47% of $u_{\mathrm{CD}}$ and 4.09% of $i_{\mathrm{g}}$. The power factor is calculated as 98.28%.

Figure 26 and Figure 27 show the comparison results of the prevention of low-frequency ripples of the DC link propagating to the power grid. From the results, it can be demonstrated that the experimental results are consistent with the simulation results shown in Figure 26 and Figure 27, meaning that $i_{\mathrm{g}}$ using PS-PWM contains corresponding harmonics from the fluctuations in the DC link. In contrast, when using the proposed control method, there are almost no new harmonics propagated to $i_{\mathrm{g}}$. These results illustrate that the proposed control method has a superior ability and can prevent the low-frequency ripple of the DC link propagating to the power grid.

6. Conclusions

Based on the energy balance principle in the circuit, a CPS energy balance control method was proposed for PV-cascaded multilevel grid-connected inverters in this paper. At first, the control principle is introduced and the control equation was analyzed and derived. By shifting the phase of the clock pulse of each cascaded unit, the control method was implemented using a comparator and integrator. The analysis and results illustrate that it has a simple structure and is simple to implement. Taking the 5-level and 17-level prototypes as examples, the feasibility and performance of the method were tested and verified by performing simulations and experiments. The results reveal that the proposed CPS energy balance control method can obtain staircase-like voltage waveforms and a grid sinusoidal input current with a low harmonic distortion. Moreover, compared to the PS-PWM method, the proposed CPS energy balance control method has a superior ability in the prevention of low-frequency ripples of the DC link propagating to the power grid. These results provide new insights for the control of multilevel inverters of grid-connected PV applications. In this study, we assessed the proposed CPS energy balance control method’s ability to prevent low-frequency ripples in the DC link; in the future, its ability to alleviate the inter-bridge power imbalance and tracking ability of the reference current will be studied.