A Unified FPGA Realization for Fractional-Order Integrator and Differentiator
Abstract
:1. Introduction
2. Literature Review of GL-Based Fractional Operators Implementations
3. Proposed Generic Hardware Realization of Fractional-Order GL-Based Integrator and Differentiator
3.1. Binomial Coefficients Generation
3.2. Generation
3.3. Fixed-Window Hardware Implementation:
4. Results and Discussion
5. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
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Ref | Diff./Integ. | Application | Generality | Approaches | q Range | Window Size | ||||
---|---|---|---|---|---|---|---|---|---|---|
Diff. | Int. | |||||||||
MATLAB | Hardware | MATLAB | Hardware | |||||||
[22] | ✓ | — | chaotic systems | ✓ | — | ✓ | — | fixed window | 0 ≤ | 20,40,30 |
[23] | ✓ | ✓ | fractional order systems | ✓ | — | ✓ | — | fixed-linear, fixed-quadratic and pwl | < ≤ | 64,512,20 |
[30] | ✓ | — | oscillators | ✓ | — | ✓ | — | fixed window | < ≤ 1 | 256 |
[29] | ✓ | ✓ | FOPID controller | ✓ | — | ✓ | — | fixed window-linear | — | 32,512,1024 |
[18] | ✓ | ✓ | — | ✓ | — | ✓ | — | fixed window-linear | — | 32 |
[25] | ✓ | — | chaotic systems | — | ✓ | — | ✓ | fixed window-linear | 0 < ≤ | 32 |
[26] | — | — | chaotic systems | — | ✓ | — | ✓ | fixed window | < ≤ 1 | 28,56 |
[27] | — | — | chaotic systems | — | ✓ | — | ✓ | fixed window | < ≤ 1 | 16,32 |
[31] | ✓ | ✓ | — | — | — | — | — | — | — | — |
L = 32 | L = 512 | L = 1024 | |
---|---|---|---|
Derivative | | | |
Integral | | | |
L = 32 | L = 512 | L = 1024 | |
---|---|---|---|
Derivative | | | |
Integral | | | |
L = 32 | L = 512 | L = 1024 | |
---|---|---|---|
Derivative | | | |
Integral | | | |
The proposed Design | 0.22 | 1.7 | 0.05 | 1.4 |
[29] | 0.22 | 1.8 | 0.01 | 1.5 |
Logic Utilization | No. of Slice LUTs | No. of Slice Registers | Maximum Frequency (MHz) | DSP Multipliers |
---|---|---|---|---|
Proposed Design (L = 20) | 22,968 (36%) | 1072 (1%) | 9.328 | 64 (26%) |
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Monir, M.S.; Sayed, W.S.; Madian, A.H.; Radwan, A.G.; Said, L.A. A Unified FPGA Realization for Fractional-Order Integrator and Differentiator. Electronics 2022, 11, 2052. https://doi.org/10.3390/electronics11132052
Monir MS, Sayed WS, Madian AH, Radwan AG, Said LA. A Unified FPGA Realization for Fractional-Order Integrator and Differentiator. Electronics. 2022; 11(13):2052. https://doi.org/10.3390/electronics11132052
Chicago/Turabian StyleMonir, Mohamed S., Wafaa S. Sayed, Ahmed H. Madian, Ahmed G. Radwan, and Lobna A. Said. 2022. "A Unified FPGA Realization for Fractional-Order Integrator and Differentiator" Electronics 11, no. 13: 2052. https://doi.org/10.3390/electronics11132052
APA StyleMonir, M. S., Sayed, W. S., Madian, A. H., Radwan, A. G., & Said, L. A. (2022). A Unified FPGA Realization for Fractional-Order Integrator and Differentiator. Electronics, 11(13), 2052. https://doi.org/10.3390/electronics11132052