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Peer-Review Record

Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates

Electronics 2022, 11(10), 1658; https://doi.org/10.3390/electronics11101658
by Aibin Yan 1, Runqi Liu 1, Zhengfeng Huang 2,*, Patrick Girard 3 and Xiaoqing Wen 4
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Reviewer 3: Anonymous
Reviewer 4: Anonymous
Electronics 2022, 11(10), 1658; https://doi.org/10.3390/electronics11101658
Submission received: 5 April 2022 / Revised: 8 May 2022 / Accepted: 11 May 2022 / Published: 23 May 2022
(This article belongs to the Section Quantum Electronics)

Round 1

Reviewer 1 Report

This paper presents the QCA designs of T Flip Flop and Polar Encoder with some XOR and XNOR gates. It has been fluently written, and the subject of the paper is interesting. However, copyright rules must be followed precisely and more technical explanations must be incorporated within the paper.

Here are my comments and questions:

1- First and foremost, the second proposed XOR gate, Fig. 2(c), is almost identical to the previous design given in Ref. No. 3. Although the new one has two fewer cells, it exactly follows the same structure/logic as the one in Ref. No. 3 does. Therefore, it cannot be considered to be a “new design”. It might be considered as an “enhanced model” of the previous design. The authors are certainly required to strictly follow the copyright rules and clearly state this issue within their paper. Any (even small) similarity between the structures of the proposed and previous designs must clearly be designated.

2- The explanations given for the proposed XOR/XNOR gates and Flip Flops are limited to the number cells, area occupation, and clock zones. However, the related sections lack a detailed description of how exactly these circuits work. More technical information is needed.

3- Figs. 1, 2, and 4: The input and output cells do not have labels.

4- A T Flip Flop has only one input signal, i.e. T. However, there are two input cells within the designs depicted in Fig. 4.

5- The circuits shown in Fig. 4 look like “T latches”.  Why do the authors call them “level-sensitive Flip Flops”? In a level-sensitive Flip Flop, the output signal is synchronized with either the “high” or “low” level of an external clock. The internal clocks of the QCA technology must not be confused with the global clock signal utilized in sequential circuits. Please comment on this issue.

6- If we consider the circuits shown in Fig. 4 to be “level-sensitive Flip Flops”, the question will be whether we can design an “edge-sensitive Flip Flop” or not?

7- There is a little distortion in the output signals of Fig. 5, and they are not very strong. It might make the circuit sensitive to noise.

8- There is a fact that the QCA technology is subject to missing, misaligned, and rotated cells. This is the reason why QCA circuit designers usually add redundant cells to make their designs more reliable. On the contrary, at the beginning of the proposed design illustrated in Fig. 4(b), there are some single cells unattached to any adjacent (side by side) cells. It seems that it might make the whole circuit vulnerable to missing cells.

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

  1. Usually XOR/XNOR gates are simply implemented by basic gates or directly' however, in this work, authors used a sequential logic T-Flip-Flop to implement XOR/XNOR.  So, the proposed XOR/XNOR might be a question why not using basic logic or directly?
  2. Line 45, author mentioned that the T-Flip-flop is a combinational circuit. Author may check if it is correct or should be sequential circuit?
  3. This work is based on just a simulation; so, it is hard to make a decision on the energy consumption. Author may include if there is any fabrication work.
  4. Line 189, author mentioned "layout design"; author should include which layout tool is used to design and how the used this software to simulate this gate.
  5. Usually layout is designed for fabrication. However, authors have not included any fabrication results.
  6. Section 4 (line 210) can be deleted.

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

In this manuscript, the authors have Designs of Level-Sensitive T Flip-Flops and Polar Encoders based on the novel XOR/XNOR Gates. The thesis of the manuscript is focused on designing XOR/XNOR gates based on the explicit interaction between cells. I recommended the publication with major revision of this manuscript after addressing the comments below : -   1. Explanation of fig 5 (a) and (b) are not proper. Why does a small change occur on every pulse? 2. In abstract the author claims stable output and lower energy dissipation but in Fig 5 (a) and (b), However output is not stable at the edge of clock. 3. Why are clocks 90 degrees out of phase  to ensure the correct transmission of signals?

Author Response

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Author Response File: Author Response.pdf

Reviewer 4 Report

The paper presents XOR-based arithmetic circuits and the following can be mentioned:

- The proposed XOR and XNOR gates are not novel and already developed in the following paper, so the authors must mention the following paper as the reference and clarify that all extended circuits in the proposed work are based on the below reference:

  • Ahmed, S., & Naz, S. F. (2020). Notice of violation of IEEE publication principles: Design of cost efficient modular digital QCA circuits using optimized XOR gate. IEEE Transactions on Circuits and Systems II: Express Briefs.‏
- The paper's contribution is too short, so the authors should add more description and information about circuits based on the main (XOR) reference so they can use the below reference:
  • Bagherian Khosroshahy, et al. (2021). Novel Feynman-Based Reversible and Fault-Tolerant Nano-communication Arithmetic Architecture Based on QCA Technology. SN Computer Science, 2(6), 1-14.‏
- The authors should add an evaluation part about the latest state-of-the-art  XOR gates, and discuss the advantages and disadvantages of previous XOR gates:
  • Chabi, A. M., et al. (2017). Towards ultra-efficient QCA reversible circuits. Microprocessors and Microsystems, 49, 127-138.‏
  • Moaiyeri, M. H., et al. (2017). Quantum-dot cellular automata circuits with reduced external fixed inputs. Microprocessors and microsystems, 50, 154-163.‏
  • Rahmani, A. M., et al. (2022). Design and Power Analysis of an Ultra-high Speed Fault-tolerant Full-adder Cell in Quantum-dot Cellular Automata. International Journal of Theoretical Physics, 61(2), 1-19.‏
- Moreover, the paper should briefly discuss clocking mechanisms in QCA.   - The paper used crossover in the proposed extended designs, yet the paper missed to talk about crossover methods. In the below author can find four crossover methods and details about all methods descriptions and advantages on the papers.
  • Shin, S.-H., et al., Wire-crossing technique on quantum-dot cellu- lar automata, in: Proceedings 2nd International Conference on Next Generation Computer and Information Technology, 2013, pp. 52-57.
  • Sam Daliri, M., et al. A 3D universal structure based on molecular-QCA and CNT technologies, J. Mol. Struct. 1119 (2016) 86-95.
  • Bhanja, S., et al. (2006, March). Novel designs for thermally robust coplanar crossing in QCA. In 2006 Design, Automation and Test in Europe (Vol. 1, pp. 6-pp). IEEE Computer Society.‏
  • Gin, A., et al. (1999). An alternative geometry for quantum-dot cellular automata. Journal of Applied Physics, 85(12), 8281-8286.

Author Response

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Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

The paper has been improved significantly.  

Author Response

Thank you very much for your evaluation of this paper.

Reviewer 2 Report

Authors should clearly describe in result discussion section as well as conclusion section that this work is based on simulation results using ....simulation tool and if they have plan to proof their result by fabrication, they should include with their future fabrication plan. If they dont have fabrication plan in future, still they should explain what are the requirement if someone wants to fabricate using their simulation results.

 

Author Response

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Author Response File: Author Response.pdf

Reviewer 4 Report

- The main idea of reference [24] is with the number of "fixed inputs"; however, the authors missed to add this criteria in comparison tables 3, 5, 6, 7 and 9.

- The authors should re-design the proposed layout in figures 8, 11, 14 and 17 based on reference [5]. Then, it is expected to gain better results, which can be added as side-by-side comparison in corresponding tables.

- The formatting of newly added references (in yellow) does not match with other references in the manuscript. The authors are advised to use Google Scholar or tools like Zotero or EndNote to get consistent formatting for all references.

- Some of the references ([22], [24] and [25]) are not mentioned in the text, please address accordingly.

Author Response

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Author Response File: Author Response.pdf

Round 3

Reviewer 4 Report

The requested edits have been performed.

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