A New Converter for Non-Isolated PV Systems

Abstract

A new converter for the non-isolated PV (photovoltaic) system is presented in this paper. It has the advantage that the input terminal of the proposed converter is connected to the output negative terminal. In this way, the parasitic capacitance is bypassed to eliminate the undesirable leakage current. The proposed converter can achieve the step-up voltage with four switches only. Aside from that, the carried-based modulation is used, and the control structure is simple. The article analyzes the working modes and control strategy of the proposed converter. In addition, a comparative analysis is provided. The feasibility of the proposed converter under different working modes is verified by simulation. Finally, the digital control prototype with DSP plus FPGA is established and the experimental tests are carried out. The experimental results verify the effectiveness of the proposed converter.

1. Introduction

In recent years, the PV power system has received widespread attention due to its pollution-free and renewable advantages [1,2]. It is mainly composed of a PV array and a power converter. The PV converter is an indispensable link in the solar power generation system. Whether the system contains a transformer is a key factor to distinguish PV grid-connected power systems, including the isolated and non-isolated ones [3,4]. The traditional, isolated PV inverter connects the transformer between the PV array and the grid to achieve electrical isolation. However, the overall structure is large, difficult to transport, and expensive with low efficiency [5]. Considering the above-mentioned problems, the non-isolated inverter system has been proposed. It does not contain a transformer, and thus it is small in size, low in cost, and low in energy loss [6,7,8]. Basically, the non-isolated inverters mainly have two structures [9]. Single-stage non-isolated inverter systems convert photovoltaic dc output to ac output through the traditional standard inverter structure. The advantages are simplified structure, low cost, low loss, and low difficulty in implementation [10], but this structure has higher requirements for the output voltage of the photovoltaic array, higher requirements for photovoltaic energy conversion on the DC input side, and corresponding difficulties in energy conversion efficiency and circuit design. Increasingly, it will also bring problems such as leakage current. Considering the two-stage non-isolated inverter, this circuit structure usually adds a boost circuit in the front stage of the inverter, and a chopper circuit such as a boost circuit is often used as its boost circuit. This type of circuit can output the voltage of the photovoltaic array and boost the voltage through the circuit structure and modulation method to improve the energy conversion efficiency, and then convert it to the ac voltage required by the load through the inverter structure. The advantage of this kind of circuit is that it can realize the decoupling of the front stage and the back stage by constructing the circuit. The overall circuit control is simple, the volume is light, and the interference is small. However, due to the increase in the number of stages, the stability of the combination of the two stages and the energy conversion efficiency is restricted [11,12,13]. Non-isolated inverters also have disadvantages, that is, the leakage current caused by parasitic capacitance, which can lead to personal safety threats, grid harmonics, and other problems [14]. Therefore, the premise of ensuring the stability of the overall performance of the inverter system arises. Next, improving the inverter system’s ability to suppress leakage current has become a key point of non-isolated inverters.

Literature [15] proposed a two-stage integrated double-ended common-ground inverter. This inverter circuit can be combined with a full-bridge inverter and a boost converter. The negative terminal of the photovoltaic side and the negative terminal of the grid side can be combined. The ends are connected, which is a dual-end common-ground topology. This topology combines two switching converters into one topology. Due to the existence of the boost converter, the photovoltaic array needs to reduce the current ripple of the low-frequency input, but its shortcomings are also obvious. The number of switches is large, and the overall system needs to be reduced by 3 consisting of one inductor and three capacitors. The overall loss of the system will increase as the number of components increases. In [16], a four-switch non-isolated inverter is proposed. This topology is composed of four switches. The circuit structure of this topology is relatively simple, but the boosting capability is insufficient. A five-switch boost inverter topology is proposed in [17]. The main advantage is that the negative terminal of the input side and the negative terminal of the output side are connected. This circuit is composed of five switches. The voltage capability is better, but due to the larger ripple in the circuit, the switch in this circuit has higher voltage stress, which limits its practical application. In [18], a non-isolated efficient H7 inverter is proposed. The topology is interesting with experimental verification, but it is not able to achieve the step-up voltage capability with seven switches.

This paper proposes a new non-isolated inverter topology with step-up voltage capability with four switches only. The rest of the paper is organized as follows. Section 2 analyzes the proposed topology in different modulation modes and working modes. Section 3 provides the simulation and digital-control experimental results. The conclusion is reached in Section 4.

2. Proposed Converter

2.1. Circuit Configuration

The proposed converter is shown in Figure 1. It consists of a dc input source V_in, an input inductor L₁, a diode D₂, and a capacitor C₁. Switches S₁, S₂, S₃, and S₄ form an H-bridge circuit, which is connected in series on the input side of the circuit. A diode D₁ in the same direction is the input inductor current. The existence of this diode can ensure the unidirectional conductivity of the power supply and ensure the stable output waveform.

The inverter circuit proposed in this paper is shown in Figure 1. It can be seen from the figure that the negative terminal of the photovoltaic array on the input side of the circuit is connected to the negative terminal of the output side load to form a double-ended common ground inverter topology. Analysis shows that this type of topology can achieve the effect of completely suppressing the leakage current by realizing a constant common-mode voltage. In one cycle, the inductance must experience a current discontinuous or continuous state, which means the output current will be distorted at the zero-crossing point. Therefore, this topology ensures a standard output waveform by connecting a diode in series on the input inductor side, while ensuring that the power supply achieves unidirectional conductivity. At the same time, due to the existence of the front-end circuit and capacitor, the problem that the gain of this type of circuit is less than 1 can be solved. Moreover, the circuit structure is simple, including only four switches. Therefore, under the premise of ensuring a simple circuit structure, the proposed converter achieves the leakage current elimination, as well as the step-up voltage capability.

In order to theoretically support the above-mentioned novelty and contribution of the article, the theoretical analysis is conducted as follows. First all of, the leakage current is relevant to the parasitic capacitance and the voltage across it, which is determined by the common mode voltage [19].

As shown in Figure 2, the leakage current through the parasitic capacitance of C_pv is related to the common-mode voltage of U_CM. By neglecting the impact of the grid voltage, the following equation can be obtained.

$$i{=\mathrm{C}}_{\mathrm{pv}}\frac{d{U}_{\mathrm{CM}}}{dt}$$

(1)

In the conventional H4 converter, the common-mode voltage is time-varying [20], and the leakage current is high. That is why different interesting converters such H5, H6, and Heric are proposed to reduce the leakage current. The idea behind these converters is based on the control algorithm that the common-mode voltage is regulated to be constant. In this way, the leakage current would be zero theoretically, as predicted by Equation (1). However, the impact of the grid voltage cannot be ignored in practice. Therefore, the new method should be further investigated. It should be noted that the proposed converter in this paper has the unique feature that the terminal A of input is connected to that B of output, as shown in Figure 1. That it, the voltage $U_{\mathrm{Cpv}}$ across the parasitic capacitance of C_pv is zero. According to $i{=\mathrm{C}}_{\mathrm{pv}}(d{U}_{\mathrm{Cpv}}/dt)$, the proposed converter achieves the leakage current elimination.

2.2. Modulation

The inverter circuit adopts the SPWM modulation method. The modulation method is shown in Figure 3a. d₁ is switch S₁ modulation wave, d₃ is switch S₃ modulation wave, and d₁ and d₃ are two modulation waves with the same amplitude and 180° phase difference. The carrier is a triangular carrier with a carrier of 0 to 1. The volt-second balance expression for the inductance L₁ column in one cycle is:

$$V_{in}{d}_3{T}_s+\left(V_{in}-V_{c_1}\right)d_{L_1}=0$$

(2)

Among them, $V_{C1}$ is the voltage across the capacitor C₁, is $d_3$ the duty cycle of switch S₃, $d_{L1}$ and is the time of the inductor L₁ in the discharge cycle. From this topology, it can be known that the inductor L₁ is working in an intermittent working state, and then is known $d_{L1}<\left(1-d_3\right)T_s$.

When the load voltage is greater than zero in the positive half cycle, it can be seen from the working mode that the switches S₁ and S₃ are on at the same time. At this time, the capacitor C₁ is charged by the inductor L₁ and the input source. The voltage at both ends shows a trend of change.

The second modulation method is improved pulse width modulation. The modulation method is shown in Figure 3b, in which the driving signals of the switching S₂ and the switching S₁ are complementary, and the driving signals of the switching S₃ and the switching S₄ are complementary.

As can be seen from Figure 3b, $M_a<(1-M_1)，M_a<M_2$ and from the analysis of the inductor current diagram, in this modulation mode, when the load voltage is in the positive half cycle or the negative half cycle, only one inductor is in the intermittent working state, and $M_a$ is the distance from $M_1$ to the highest point of modulating wave $d_1$.

It can be seen from the figure that the modulation wave of switch S₁ is consistent with the modulation wave in the SPWM modulation mode, and the modulation wave of switch S₃ is the offset of the amplitude M₁ and M₂, and $d_1(t),d_3(t)$ the expression is:

$$\{\begin{array}{c}{d}_1(t)=\{\begin{array}{c}{M}_a\sin \left(2\pi \frac{t}{T_s}\right)+M_1,0<t<\frac{T_s}{2}\\ M_a\sin \left(2\pi \frac{t}{T_s}\right)+M_2,\frac{T_s}{2}<t<T_s\end{array}\\ d_3\left(t\right)=\{\begin{array}{c}{M}_1,0<t<\frac{T_s}{2}\\ M_2,0<t<\frac{T_s}{2}\end{array}\end{array}$$

(3)

2.3. Operating Mode

In order to ensure that this circuit has the principle of an inverter and boost performance, its working mode is now analyzed. It can be seen from the circuit structure that when switch S₁ is turned on, switch S₂ should be in the off state, and when switch S₃ is turned on, switch S₄ should be in the off state. In order to realize the standard inverter mode, there are only two switches each time. Each switch tube is turned on. It can be seen from the above that the circuit presents four working modes; in turn, the S₁ and S₃ are on, the S₂ and S₄ are off; the S₂ and S₃ are on, the S₁ and S₄ are off; the S₂ and S₄ are turned on, the S₁ and S₃ are off; the S₁ and S₄ are on, the S₂ and S₃ are off. Therefore, the driving signals of switch S₁ and switch S₂ are complementary, and the driving signals of switch S₃ and switch S₄ are complementary.

In addition, the working status of the switch is also specifically distinguished according to whether the load side voltage is a positive or negative half cycle. The details are as follows. When the load voltage is in the positive half cycle, the S₁ and S₃ are all on, and switch S₁ is on, switch S₃ is off, and switches S₁ and S₃ are all off. When the load voltage is in the negative half cycle, switches S₁ and S₃ are all on, switch S₁ is off, switch S₃ is on, and switch S₁ and switch S₃ are all off. According to the above analysis, the working mode of the inverter circuit is shown in Figure 4. Due to the difference of the positive and negative half-cycle of the load voltage, there will be differences in the capacitor charging and discharging forms under the same switching mode. Now we will analyze it in detail.

The working mode is as follows. When the load side voltage is in the positive half cycle, the inverter operating mode and the capacitor and inductor charging and discharging forms in the circuit are as follows, where $V_0$ is the load voltage, $V_{in}$ is the input voltage, and $I_{C1},I_{C2}$ is the voltage flowing through the capacitor C₁ and the capacitor C₂. The current $I_{L1}$ is the inductor current on the input side and the current $I_0$ on the load side.

Working mode 1: The switches S₂ and S₄ are kept in the on state, and the switches S₁ and S₃ are kept in the off state, as shown in Figure 4a. At this time, the inductor L₁ is discharged, and the capacitor C₂ is charged at this time. According to Kirchhoff’s law of voltage and current, this mode can be expressed by the following formula:

$$\{\begin{array}{c}{V}_{in}=V_{L_1}+V_{C_1}\\ V_{C_1}=V_{C_2}\end{array}$$

(4)

$$\{\begin{array}{c}{I}_{L_1}=I_{C_1}+I_{C_2}\\ I_{L_f}=I_{C_f}+I_0\end{array}$$

(5)

Working mode 2: The switches S₁ and S₄ are kept in the on state, and the switches S₂ and S₃ are kept in the off state, as shown in Figure 4b. The input source charges the capacitor C₁ through the inductor L₁, the input source charges the load side through switch S₁, and at the same time charges the capacitor C₂. According to Kirchhoff’s law of voltage and current, this mode can be expressed by the following formula:

$$\{\begin{array}{c}{V}_{in}=V_{L_1}+V_{C_1}\\ V_{L_f}+V_{C_f}=V_{C_1}\\ V_{C_1}=V_{C_2}\end{array}$$

(6)

$$\{\begin{array}{c}{I}_{L_1}=I_{C_1}+I_{L_f}+I_{C_2}\\ I_{L_f}=I_{C_f}+I_0\end{array}$$

(7)

Working mode 3: The switches S₁ and S₃ are kept in the on state, and the switches S₂ and switch S₄ are kept in the off state, as shown in Figure 4d. The input source charges the inductor L₁ through switch S₃ and diode D₁, and capacitor C₁ charges the load side at this time. At this time, the inductor L₁ is in a charged state, and the capacitor C₁ is in a discharged state. According to Kirchhoff’s voltage and current law, this mode can be represented as:

$$\{\begin{array}{c}{V}_{in}=V_{L_1}\\ V_{L_f}=V_0\end{array}$$

(8)

$$\{\begin{array}{c}{I}_{C_1}=I_{L_f}\\ I_{L_f}=I_{C_f}+I_0\end{array}$$

(9)

When the load side voltage is in the negative half cycle, the working mode of the circuit and the charging and discharging forms of the capacitors and inductors in the circuit are as follows:

Working mode 1: The switches S₂ and S₄ remain in the on state, and the switches S₁ and S₃ remain in the off state, as shown in Figure 4a. At this time, the inductor L₁ is in a discharged state, and the capacitor C₂ is in a discharged state. In this working mode, the loop voltage and current expressions are consistent with the load voltage in the positive half cycle.

Working mode 2: The switches S₂ and S₃ are kept in the on state, and the switches S₁ and S₄ are kept in the off state, as shown in Figure 4c. At this time, the inductor L₁ is in a charged state, and the capacitors C₁ and C₂ are in a discharged state. According to Kirchhoff’s law of voltage and current, this mode can be expressed by the following formula:

$$\{\begin{array}{c}{V}_{in}=V_{L_1}\\ V_{C_2}=V_{L_f}+V_0\end{array}$$

(10)

$$\{I_{L_f}=I_{C_f}+I_0$$

(11)

Working mode 3: The switches S₁ and S₃ remain in the on state, and the switches S₂ and S₄ remain in the off state, as shown in Figure 4d. At this time, the inductor L₁ is in a charged state, and the capacitor C₁ is in a discharged state. In this working mode, the loop voltage and current expressions are consistent with the load voltage in the positive half cycle.

2.4. Parameter Design

According to the above analysis of the working mode, the inductor L₁ is charged by the input power. By combining the expression in the working mode and the inductor voltage expression, the current ripple of the inductor L₁ can be calculated, and the ripple expression is:

$$\Delta i_{L_1}=\frac{V_{in}{d}_3{T}_s}{L_1}$$

(12)

Among them, $d_3,\Delta i_{L1}$ represents the on-time of switch S₃, the current ripple of the inductor L₁, and a switching cycle time. Therefore, the inductance L₁ can be obtained by the following formula:

$$L_1=\frac{V_{in}{d}_3{T}_s}{\Delta i_{L_1}}$$

(13)

According to the above-mentioned working mode analysis and loop expression, the voltage ripple of the capacitors C₁ and C₂ is affected by the current of the inductor L₁ and the duty cycle of switch S₃ and switch S₄. Therefore, the capacitance calculation formula is:

$$\{\begin{array}{c}{C}_1=\frac{i_{L_1}{d}_3{T}_s}{\Delta V_{C_1}}\\ C_2=\frac{i_{L_1}{d}_4{T}_s}{\Delta V_{C_2}}\end{array}$$

(14)

Among them, $\Delta V_{C1},\Delta V_{C2}$ are the voltage ripples of capacitors C₁ and C₂, respectively.

Through the above analysis, in the simulation and experiment, the inductance L₁ is set to 5 $mH$, the capacitor C₁ is set to 30 $\mu F$, and the capacitor C₂ is set to 50 $\mu F$.

2.5. Comparative Study

Table 1. Comparative study of the different converters.

Topology	Switch	Step-Up Capability	Leakage Current
H4 + boost converter converter	5	Yes	High
H5 converter	5	No	Small
H6 converter	6	No	Small
oH5 converter	6	No	Very Small
Proposed converter	4	Yes	Zero

shows the comparative study of the proposed converter against the existing non-isolated converter with the leakage current suppression capability.

From Table 1, it can be observed that the conventional H4 + boost converter has five switches with step-up voltage capability. However, the leakage current is high, which limits its application in a non-isolated PV system. For H5 and H6 converters, the number of switches is 5 and 6, respectively, but they are not able to achieve the step-up voltage capability. Compared to H5 and H6 converters, the leakage current is smaller, due to the clamped switch during the switching commutation. Nevertheless, it needs 6 switches to achieve it for oH5 converter. In addition, it has no step-up voltage capability. For the proposed converter, it only needs four switches. Meanwhile, it has the step-up voltage capability. Aside from that, the leakage current is zero, due to the fact that the terminal of input is connected to that of the output. In summary, the proposed converter has the advantages of fewer switches, zero leakage current, as well as step-up voltage capability.

3. Simulation Results

In order to verify the feasibility of the proposed inverter, the time-domain simulation is carried out in MATLAB/Simulink. The simulation parameters are shown in

Table 2. Simulation parameters.

Parameter	Values
Input voltage Vin	70 V
output voltage RMS	110 V/50 Hz
Input inductance L1	5 mH
Capacitance C1	30 μF
Capacitance C2	50 μF
Capacitance Cf	20 μF
Inductance Lf	2 mH

. In the simulation, the input voltage is designed to be 70 V, and the output voltage RMS value is 110 V. In order to facilitate the design of the experimental device parameters, in the design and selection of the inductive capacitor device parameters, the value of the inductor current ripple is set to $\Delta i_L=20\%i_L$ and the voltage ripple is set as $\Delta V_C=7\%V_C$. The calculation of the inductance and capacitance value is based on the parameter design part of the previous section.

Figure 5 shows the output current waveform, output voltage waveform, and FFT analysis of the proposed inverter circuit. The RMS value of the output voltage is 110 V, and the RMS of the output current is 1.1 A. Through fast Fourier analysis (FFT) analysis, THD = 2.53%, less than 5%, meet the design requirements. Figure 6 shows the voltage stress waveforms of switch S₁, switch S₂, switch S₃, and switch S₄, and the current stress waveform diagrams of switch S₁ and switch S₄. The switch voltage stress is about 320 V, and the current stress is less than 12 A. When selecting the switch, considering the voltage and current margin twice, the switch withstand voltage is higher than 640 V and the withstand current is higher than 24 A, so the model produced by Infineon is 1KWK40T1202, and its collector and emitter can withstand 1200 V With DC voltage and the current withstand capability can reach 40 A, which meets the requirements of the experimental design.

4. Experimental Results

In order to further verify the effectiveness of the inverter circuit, an experimental platform was built for it, and experimental verification was carried out. In the experiment, the input voltage was maintained at 70 V, and the load was 100 Ω. In order to meet the actual experimental environment requirements, the switch tubes were all selected as 1KWK40T1202 IGBTs.

First, the inverter circuit was tested under a 70 V input voltage. Figure 7a shows the voltage and current stress waveforms of switch S₁ when the effective value of the output voltage is 110 V. Figure 7b shows the voltage and current stress waveforms of switch S₄. Due to the characteristics of the circuit structure, the stresses of switch S₃ and switch S₄ are similar. Figure 7c is the output voltage waveform and the output current waveform and the voltage stress waveform of switch S₂. Figure 7d is the voltage and current stress waveform of the capacitor C₂, which can be seen from the figure. The experimental results are in agreement with the simulation results, and the circuit gain can reach 2.2 times at this time.

In order to further verify the effectiveness of the proposed inverter under the input voltage variation, the input voltage is increased to 100 V. The experimental results are shown in Figure 8. Figure 8a shows the voltage and current stress waveform at both ends of switch S₁, and Figure 8b is switch S₄. Figure 8c shows the voltage and current waveforms at both ends of the inductor L₁. Figure 8d shows the voltage and current waveforms at both ends of the capacitor C₂. The above waveform shows that the circuit gain can reach 1.55 times at this time, which again verifies the effectiveness of the proposed converter.

5. Conclusions

This paper has presented a new non-isolated dual-grounded converter. The leakage current can be eliminated by the dual-ground structure of the converter, that is, the input terminal is connected to the output negative terminal. In addition, the converter can achieve the step-up voltage even with the input voltage variation. Experimental verification is also provided to verify the effectiveness of the proposal in this paper. In summary, compared with the existing methods, the proposed converter is simple with less switches, and the modulation is easy to implement. Aside from that, the leakage current is eliminated with step-up voltage capability. Therefore, it is attractive for non-isolated PV systems.