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Article

Synthesis of Self-Checking Circuits for Train Route Traffic Control at Intermediate Stations with Control of Calculations Based on Weight-Based Sum Codes

by
Dmitry V. Efanov
1,*,
Artyom V. Pashukov
2,
Evgenii M. Mikhailiuta
1,
Valery V. Khóroshev
2,
Ruslan B. Abdullaev
3,
Dmitry G. Plotnikov
1,
Aushra V. Banite
1,
Alexander V. Leksashov
1,
Dmitry N. Khomutov
1,
Dilshod Kh. Baratov
3 and
Davron Kh. Ruziev
3
1
Laboratory “Industrial Stream Data Processing Systems”, Higher School of Mechanical Engineering, Material and Transport Institute, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, Russia
2
“Automation, Remote Control and Communication on Railway Transport” Department, Russian University of Transport, Moscow 127994, Russia
3
“Automation and Remote Control” Department, Tashkent State Transport University, Tashkent 100167, Uzbekistan
*
Author to whom correspondence should be addressed.
Computation 2024, 12(9), 171; https://doi.org/10.3390/computation12090171
Submission received: 1 July 2024 / Revised: 31 July 2024 / Accepted: 23 August 2024 / Published: 26 August 2024

Abstract

:
When synthesizing systems for railway interlocking, it is recommended to use automated models to implement the logic of railway automation and remote control units. Finite-state machines (FSMs) can be implemented on any hardware component. When using relay technology, the functional safety of electrical interlocking is achieved by using uncontrolled (safety) relays with a high coefficient of asymmetry of failures in types 1 → 0 and 0 → 1. When using programmable components, the use of backup and diverse protection methods is required. This paper presents a flexible approach to synthesizing FSMs for railway automation and remote control units that offer both individual and route-based control. Unlike existing solutions, this proposal considers the pre-failure states of railway automation and remote control units during the finite-state machine synthesis stage. This enables the implementation of self-checking and self-diagnostic modules to manage automation units. By increasing the number of states for individual devices and considering the states of interconnected objects, the transition graphs can be expanded. This expansion allows for the synthesis of the transition graph of the control subsystem and other systems. The authors used a field-programmable gate array (FPGA) to implement a finite-state machine. In this case, the proposal is to encode the states of a finite-state machine using weight-based sum codes in the residue class ring based on a given modulus. The best coverage of errors occurring at the outputs of the logic converter in the structure of the FSM can be ensured by selecting the weighting coefficients and the value of the module. This paper presents an example of synthesizing an FPGA-based FSM using state encoding through modular weight-based sum codes. The operation of the synthesized device was modeled. It was found to operate according to the same algorithm as the real devices. When synthesizing self-checking and self-controlled train control devices, it is recommended to consider the solutions proposed in this paper.

1. Introduction

Railway automation equipment and systems are used to safety control train traffic at stations [1]. Such systems can be implemented on different components. For instance, the majority of railway stations in Russia have electrical interlocking systems for switches and signals that rely on electromagnetic relays [2]. There are technical solutions in which a part of the circuits, known as the “type-setting group”, responsible for inputting control commands, is based on microelectronic and microprocessor technology. Another part, called the “executive group”, which implements technological control algorithms, is based on relays. Fully microelectronic and microprocessor systems are also available [3]. For instance, the characteristics of interlocking equipment for controlling railway crossings via field-programmable gate arrays (FPGAs) are detailed in [4]. Reference [5] discusses the features of synthesizing track receivers for track circuits, which are sensors used to determine the location of mobile units, on FPGAs. Reference [6] examines a technique for generating self-checking control units for railway switches on FPGAs. These units are equipped with information that connects with monitoring systems designed to assess their technical condition, similar to the system presented in [7]. Additional devices, such as programmable logic controllers and microprocessors [8], are utilized for railway automation’s circuit solutions.
Criteria describing the logic of functioning of interdependent railway automation devices are used when synthesizing control circuits for automation units at stations. For instance, in contemporary electrical interlocking systems, a route is established by pressing the start and end buttons, which flip-flops the railway switches along the route to move automatically. Once all traffic safety criteria are met, a permissive indication is illuminated at the railway signal that encloses the aforementioned route. Thus, when controlling automation units at the station, logic chains of states are used. At the same time, the devices and systems of railway automation and remote control implement finite-state machines (FSMs).
Reference [9] states that relay systems should be deterministic automata. With this in mind, a methodology has been developed for testing railway automation and remote control relay systems using an integrated model of distributed systems, temporal formalism, and the Dedan tool. Relay train control systems are typically asynchronous FSMs. This fact limits their operations. For example, there may be delays in turning relays on or off, or issues with data encoding. These limitations have been noted in previous research [10].
FSM models are frequently used to test systems that implement logical dependencies. For instance, in [11], an electrical interlocking verification is described by means of the FSM model. In this case, the verifier analyzes the contents of the control table for any conflicting settings.
Reference [12] is relevant for promising projects in the field of synthesizing train control systems. It highlights the correlation between living organisms and the operation of FSMs. The authors developed a DNA FSM. A programmable allosteric DNAzyme strategy was developed to build an FSM that can dynamically respond to successive stimulus signals. The results of the work are interesting in terms of the synthesis of FSMs describing the logic behind train traffic control.
In general, any station can be described by a set of standard templates corresponding to the track development. It is not a challenging task to delineate the logical criteria for allocating and executing the routes, mirroring the approach taken in [13]. This approach employs mathematical logic for station-based train traffic control groups. It should be acknowledged that guaranteeing the dependability and safety of railway automation systems through established methods [14,15] is imperative when synthesizing them.
In such works, authors do not consider synthesizing an FSM with self-checking and self-control properties. The use of automata theory is limited to verifying the logic of functioning and control algorithms. This is due to its peculiar application. They do not perform functions that require error detection. This paper presents a methodology for synthesizing self-checking devices for railway automation and remote control. The methodology is based on the FSM model that allocates protective and pre-failure states.

2. Research Objective

Railway automation devices and electrical switch and signal interlocking systems can be represented by a Mealy machine [16,17]:
A = <Χ, Q, Z, Q1, φ, χ>
where X X 1 , X 2 , . . . , X r is the set of input variables;
Q Φ , Ψ , Ω , Δ is a set of the machine states, ( Φ Φ 1 , Φ 2 , . . . , Φ n is a set of efficient and serviceable states, Ψ Ψ 1 , Ψ 2 , . . . , Ψ m is a set of pre-failure serviceable states, Ω Ω 1 , Ω 2 , . . . , Ω k is a set of inoperable protective states, and Δ Δ 1 , Δ 2 , . . . , Δ l is a set of inoperable dangerous states causing a threat of an accident or catastrophe);
Z Z 1 , Z 2 , , Z p is a set of output states;
Q 1 Q is the initial state of the machine;
φ is a transition function that maps the set Χ × Q to the set Q–φ: Χ × QQ;
χ is a transition function that maps the set Χ × Q to the set Z–χ: Χ × QZ.
A methodology for synthesizing self-checking circuits for FPGA-based railway automation and remote control is required. It should consider possible transitions to pre-failure states.

3. General Research Approaches and Methodology

The target of this study is railway automation and remote control systems employed at intermediate railway stations. The scope of this study is the synthesis of control algorithms, with particular consideration given to the interdependencies between switches and signals. Concurrently, the control algorithms consider not only the typical operation of the devices but also their transitions to the so-called pre-failure and protective states.
This study revealed that the FSM model is an effective means of describing the operational logic of railway automation and remote control devices at intermediate railway stations. The complexity lies in the formation of the transition graph of the FSM, which must take into account the states of all devices. It is therefore most efficient to synthesize individual graphs by station route. It should be noted that the number of routes at intermediate stations is relatively limited. It can be reasonably deduced that the transition graph may not contain a substantial number of states.
A standard methodology is employed to synthesize an FSM. However, in order to safeguard the device from faults and errors resulting from stuck-at failures and malfunctions, it is determined that widely underutilized weight-based sum codes in the residue class ring using a specified modulus should be applied. The selection of a weight-based sum code with a specific modulus value and particular error detection characteristics for the information characters of the codewords is dependent upon the number of states, memory cells, and outputs of the device in question. This methodology enables the synthesis of a self-controlled FSM with the capacity to indicate transitions, which is crucial for the operational tasks of the final device. Indeed, it permits the digital simulation of its operation in parallel with the completion of the primary tasks. Such a solution is conducive to subsequent integration with the control systems of the upper hierarchy, specifically the centralized traffic control system.
This paper sets forth the fundamental principles of device synthesis employing programmable components, specifically field-programmable gate arrays (FPGAs). The example of a simple, standard railway station demonstrates how to synthesize a device using a table of routes, interdependencies of switches and signals, and a set of states of railway trackside devices.
This paper does not address the issues of reliability and safety associated with the implementation of upper-level railway automation and remote control systems. These issues are discussed in detail elsewhere. The attainment of a high degree of reliability and safety is contingent upon the utilization of redundancy, diverse protection, and technical diagnostic methodologies.

4. Requirements for the Operating Logic of Railway Trackside Equipment

When implementing a train control system, it is essential to ensure the safety control of switches and signals, which are interdependent. The trackside automation and remote control mechanical units serve as the final control equipment. Any given circuit for their operation can be pre-modelled as an FSM. It is required to describe the finite-state machine logic and move from a verbal description to the synthesis of an FPGA-based self-checking device.
There are interdependencies between trackside units of railway automation and remote control. Both individual and group (route) control devices operate at stations. The concept of a “route” is fundamental in the construction of electrical interlocking.
A route is a structured method for a rolling stock’s following by train or shunting order at a station. There are two types of routes: train routes and shunting routes.
A train route is a route intended for the movement of a rolling stock along the stretches and through stations along prepared routes for receiving, departing, or passing trains.
A shunting route is a designated track for locomotives, with or without cars, to move within the station territory and conduct shunting operations, including departure for the stretch if necessary.
When setting a route, the navigation and security switches are locked to exclude conflicting (secant) routes. Once the route is locked, a permissive indication is activated at the signal that locks the route.
To set a train route in the electrical interlocking, it is necessary to specify the departure and destination points. In certain systems, it may be necessary to manually adjust the switches to the desired positions. In most cases, the route is automatically set by inputting the departure and destination points and intermediate points for longitudinal station on the station’s mnemonic diagram into the automated workstation (AWS) control technology window. To set a shunting route in an electrical interlocking, it is required to specify all intermediate points, typically certain shunting signals.
To comprehend the process of implementing a route, let us consider the most basic intermediate station. Figure 1 displays the plan for a single-line station. There are more than a thousand of such stations across post-Soviet territories. They serve as technologically equipped facilities for crossing and overtaking operations.
The aforementioned station comprises four switches and six output, two input, and two shunting signals. Table 1 and Table 2 present a comprehensive overview of all train and shunting routes connected to this station. The following tables display the interdependencies between routes, switches, and signals for train and shunting routes. Table 3 shows the interdependencies of signal indications.
The following designations are accepted in Table 3: Computation 12 00171 i003 is the red signal indication; Computation 12 00171 i001 is the yellow signal indication; Computation 12 00171 i002 is the green signal indication; Computation 12 00171 i004 is the “Two yellow, upper flashing” signal indication; Computation 12 00171 i004 is the “Two yellow” signal indication.
To devise a control system for the switches and signals at the intermediate station, it is imperative to synthesize control circuits for individual railway automation units independently and then make their information interface with each other.
When implementing route control, it is important to consider all processes that take place during traffic control at the station. Two notable procedures include the route locking and its subsequent release. In this scenario, the release may occur as a result of either train passage or artificial means (no train passage). This happens when the station attendant cancels the route. There are separate descriptions of these processes during synthesis.
The following parameters are utilized to set the route:
  • Route type (train or shunting);
  • Departure point (the signal from which the route starts);
  • Destination point (the signal to which or beyond which the route is constructed).
Where practicable, stations with alternative routes will display a variation option. There is no such route for the station considered in Figure 1.
There are only 12 train routes and 12 shunting routes for the station shown in Figure 1. Each route can be defined as a system state in which control signals are transmitted to trackside automation equipment and remote control mechanical devices.
As previously stated, the route can be released manually or during the train passage. When artificially releasing the route, it is necessary to consider the route type and the condition of the track section in front of the railway signal from which the route is being constructed. This step is required to postpone the route cancellation.
During the passage of the train, the route is released according to the following rules [18]:
  • The first section in the train route is released when the approach section is released, this section is occupied, the next section is occupied, and this section is released and remains free for at least 6 s;
  • The first section in shunting routes is released when this section is occupied, the next one is occupied, and this section is released and remains free for at least 6 s;
  • Any section that is not the first one is released when this section is occupied, the next one is occupied, and this section is released and remains free for at least 6 s;
  • If the approach section was not released during the train route, then the route will be released after the train arrives at the route destination point.
The delay in releasing is essential to prevent a temporary loss of shunt sensitivity.
These conditions must be taken into account when synthesizing the railway automation and remote control schemes.

5. Principles of Forming the Transition Graph for an FSM

The input data required for the even bottleneck route locking system are as follows:
  • x1 is the route type (0—not specified; 1—train; 2—shunting);
  • x2 is the route departure point (0—not specified; 1—E; 2—O1; 3—O2; 4—O3; 5—S2);
  • x3 is the route destination point (0—not specified; 1—O; 2—O1; 3—O2; 4—O3; 5—S2);
  • x4 is the track and switch point section occupancy along the route (0—occupied; 1—free);
  • x5 is switch point position 2 (0—plus position; 1—minus position; 2—no control);
  • x6 is switch point position 4 (0—plus position, 1—minus position, 2—no control);
  • x7 is the track and switch point sections locking (0—released; 1—locked);
  • x8 is switch point locking 2 (0—released; 1—locked);
  • x9 is switch point locking 4 (0—released; 1—locked);
The following are the output data required for the system:
  • z1 is switch point state 2;
  • z2 is switch point state 4;
  • z3 is railway signal state E (0—forbidding indication; 1—permissive indication; 2—no indication);
  • z4 is railway signal state O1 (0—forbidding indication; 1—permissive indication; 2—no indication);
  • z5 is railway signal state O2 (0—forbidding indication; 1—permissive indication; 2—no indication);
  • z6 is railway signal state O3 (0—forbidding indication; 1—permissive indication; 2—no indication);
  • z7—is railway signal state S2 (0—forbidding indication; 1—permissive indication; 2—no indication);
Table 4 shows the system states when the route is locked in an even bottleneck.
There are non-binary numbers in the “Parameter Vector” column. In this case, similar parameters, such as signal numbers, are combined. Signal numbers are described by separate variables when implemented on the FPGA. For example, if the departure point of the route is the railway signal O, then the variable responsible for this signal will be assigned “1”, and the rest will be assigned “0”. The same applies to the route destination point. Figure 2 shows the transition graph for a single route.
It should be mentioned that the complete system will comprise multiple transition graphs functioning together. This is because the route-setting process for all possible travel options is identical, involving the selection of the departure and destination points, route preparation, and route locking. For instance, Figure 3 displays the transition graph for two routes.
As can be observed in Figure 3, states Q3 and Q15, which correspond to the second route, have been incorporated. Thus, the addition of new states enables the construction of a transition graph for the entire bottleneck or station.
This paper presents a technique for synthesizing the transition graph of an FSM for a train traffic control system, taking into account route dependencies.
The Synthesizing Process for an FSM Transition Graph Involves the Following Stages:
  • For an intermediate station, a switch points and signals interdependencies table is acquired from technical documentation [19].
  • For each individual route, a graph is created that includes the following states:
    • Initial state (in this case, there are no routes at the station);
    • Route preparation state (one state for each route);
    • Route locking state (one state for each route);
    • Protective state;
    • A state of the system in which one or more of the control devices go into a pre-failure state.
At this stage, it is appropriate to specify the initial and protective states for a single route. For the rest, these states can remain unspecified, as they will be combined further.
Cascade connection of all graphs is performed. All states with identical names, whether initial or protective, are combined into a single state, which serves as the origin or destination for state transitions.
If there are multiple routes available, the graph will be supplemented with transitions that connect the states corresponding to a locked route and a new non-conflicting route. If multiple routes cannot be set at a station simultaneously, this step is omitted.
If monitoring is required, additional states can be incorporated to denote the presence of a particular malfunction. This can be applied to both system malfunctions and malfunctions in trackside equipment, using the concept proposed in [20,21]. This will enable the implementation of intelligent control functions in instances of protective and hazardous failures in railway automation equipment.
An example below illustrates FPGA-based device synthesis.

6. FPGA-Based FSM Synthesis

In order to prevent the transfer of switches that are not included in the route, they also need to be controlled. This means that they must hold the position they are in after releasing the route.
Table 4 was updated to include new states for routes that do not have switches included in them. The updated states are shown in Table 5. All vectors are also represented in binary form.
The synthesis process will be carried out in a graphical editor on D flip-flops [22].
Let us compile and minimize the table of FSM transitions and outputs (see Table 6).
The term A* is used to designate all vectors that are not utilized for transition from a specific state in the control system, as it cannot skip any state.
The table is then encoded. Each state is mapped to a binary set. The set “000” corresponds to the protective state. Table 7 shows the codeword formation rules, and Table 8 is the encoded transition table.
Once the table of transitions and outputs has been encoded, the functions for activating the memory cells are defined. Table 9 provides the rules derived from the D-flip-flop operation logic when transitioning between states at time points t − 1 (previous clock cycle) and t (current clock cycle), based on logical principles.
The flip-flop activation functions (Table 10) are obtained using the data from Table 9.
All code vectors corresponding to the intersections of A* and yi are denoted by A**.
Write out the input sets where the functions YDi = 1:
YD1 = {6970, 6972, 7547, 7549}
YD2 = {6977, 6978, 7489, 7491}
YD3 = {0, 1, 4, 5, 64, 65, 68, 69, 128, 129, 132, 133, 192, 193, 196, 197, 256, 257, 260, 261, 320, 321, 324, 325, 384, 385, 388, 389, 448, 449, 452, 453, 7489, 7491, 7547}
Figure 4 shows a block diagram of a finite-state machine that controls trackside equipment in order to set two routes. There are no outputs Z8–Z11 in the figure since these entities do not contribute to determining the routes being examined, and their functionalities are negligible.
The operation of the FSM during the route setting, locking, and return to the initial state is demonstrated in Figure 5 (up to the red line). As can be observed, the system initially arranges the route by positioning the switches. Then, it locks certain route sections, followed by the necessary signal activation. The figure also illustrates the process of transitioning the system to a protective state (from the red line) and returning it to its original state (from the green line) when input data that do not align with the system’s logic are received. It is also noteworthy that the transition of the system to a protective state is also possible when setting a route. A route’s switch losing control serves as an example.
Table 11 shows the parameters of the control system designed using the Cyclone V FPGA [23]. In the FPGA, only three blocks are occupied. It is evident that separate logic cells are occupied in each block (logic utilization (in ALMs)) when viewed in detail. The number of cells occupied in each block may vary. In this case, the number varies from 0 to 10. The same applies to input/output pins. They are shown in brown text in the figure.
An internal control scheme is synthesized for the resulting FSM. The error correction code used is the modulo M = 4 with weights [w1, w2, w3] = [1, 2, 3]. Since the weighting coefficients form a series of natural numbers and M = m + 1, where m is the number of digits in the data vector [24], this code will be able to detect all single errors in the data vector.
The weights of each data vector can be found by using the formula i = 1 m w i f i , where fi represents the value of the i-th function that describes the information character. Then, the smallest non-negative deduction modulo M = 4 should be found, and the resulting number should be represented in binary form. Table 12 lists the values of the control functions for the outputs of the memory cells.
Write out the input sets, where the functions gi = 1:
g1 = {0, 1, 4, 5, 64, 65, 68, 69, 128, 129, 132, 133, 192, 193, 196, 197, 256, 257, 260, 261, 320, 321, 324, 325, 384, 385, 388, 389, 448, 449, 452, 453, 6977, 6978}
g2 = {0, 1, 4, 5, 64, 65, 68, 69, 128, 129, 132, 133, 192, 193, 196, 197, 256, 257, 260, 261, 320, 321, 324, 325, 384, 385, 388, 389, 448, 449, 452, 453, 6970, 6972, 7489, 7491}
Finding the encoder functions (Table 13).
Represent the g*i functions in disjunctive normal form (DNF):
g 1 * = Y D 1 ¯ Y D 2 Y D 3 ¯     Y D 1 ¯   Y D 2 ¯ Y D 3
g 2 * = Y D 1 ¯ Y D 3       Y D 1 Y D 2 ¯   Y D 3 ¯ .
Similarly, the internal control circuit for the output converter is synthesized. For this purpose, a weighted code modulo M = 8 with weighting coefficients [w1, w2, w3, w4, w5, w6, w7] = [1, 2, 3, 4, 5, 6, 7] is used [24]. Table 14 displays the control function values for the output vector of the finite-state machine, similar to Table 12.
Write out the input sets, where the functions gi = 1:
g1 = {6970, 6972, 7547, 7549}
g2 = Ø
g3 = {6970, 6972, 6977, 6978}
Find the encoder functions (Table 15). All unused sets are denoted as A***.
Represent the gi* functions in full disjunctive normal form (DNF):
g 1 * = Z 1 Z 2 ¯ Z 3 Z 4 Z 5 ¯ Z 6 Z 7 Z 1 Z 2 ¯ Z 3 Z 4 Z 5 Z 6 ¯ Z 7
g 2 * = 0
g 3 * = Z 1 ¯   Z 2 ¯ Z 3 Z 4 ¯   Z 5 ¯ Z 6 Z 7 ¯ Z 1 Z 2 ¯ Z 3 Z 4 Z 5 ¯ Z 6 Z 7
Figure 6 shows the block diagram of an FSM with embedded control circuits.
Note that the Z*1 and Z*2 functions are two-rail when operating correctly ( Z 1 * = Z 2 * ¯ ). In the event of a malfunction, both signals become equal. Table 16 and Table 17 show the parameters of both synthesized embedded control circuits. They also take into account the synthesis of each control circuit on a separate chip. Synthesizing the control circuit on a single chip reduces the number of pins.
In order to create a system that can set routes for the entire station, it is essential to incorporate the unaccounted route states into the FSM design. It is worth noting that the design’s complexity does not increase linearly. For instance, two routes necessitated six states and six distinct transition conditions. At the same time, only three flip-flops were necessary. Eight states are required for three routes. However, the number of flip-flops will remain unchanged. For the maximum number of routes in the example under consideration (26), 54 states are required. Six flip-flops are required to encode them. ECCs may become more complicated with the increase in the number of states.

7. Discussion

In the process of synthesizing train traffic control systems at intermediate stations, it is recommended that consideration be given to the numerous technical states of control objects. In this context, the control and monitoring objects encompass trackside railway automation and remote control equipment, including electric switch mechanisms, signals, train position control sensors, crossing automatics, and other pertinent components. The aforementioned facilities exhibit a limited range of technical states. Furthermore, the devices are interdependent, which results in their operation being closely integrated. All of these factors influence the various technical states of the system.
This paper outlines a methodology for synthesizing a train traffic control system. This is achieved by forming graphs for individual station traffic routes in a sequential manner and then combining them using the same states in different subgraphs. Some of the most evident benefits of this methodology are the ability to contemplate logical transitions between states, the potential to expand the range of states and incorporate protective and pre-failure states, the incorporation of functions for monitoring device operation, and, in the future, the control of analog parameters. This configuration renders the control system more akin to an adaptive automated control system rather than one that, in the event of a fault, exclusively enters protective states until the damage is rectified. This enables the potential for controlling the pre-failure states, thus preventing the attainment of protective failure states. This has the effect of enhancing the efficacy of the implementation of the train schedule and mitigating the risks of its disruption.
It is important to consider the limitations of the FSM model when used for the synthesis of control devices at railway stations. One such limitation is that the number of logical variables increases with the growth in the number of routes at stations, as well as with the growth in the number of states. Consequently, the challenge of implementing a set of interconnected FSMs arises. As a result, the implementation of an FSM for traffic control at large stations, comprising over 20–30 switches, is often challenging and, in some cases, unfeasible. Nevertheless, the number of small stations consistently outnumbers that of other station types within the railway networks. This is where the principles of typical system design for small intermediate stations can be developed.
With regard to the means of FSM protection and self-checking, it should be noted that this paper presents only the methodology for the synthesis of a protected FSM. This involves the encoding of states and the arrangement of embedded control circuits by the weight-based sum code. The selection of code is based on an evaluation of the capacity of the set of states and the lengths of data vectors formed by logical variables. This paper presents an illustrative example of the selection of the weight-based code for encoding. It should be noted that other stations and facilities may necessitate the utilization of a distinct weight-based code characterized by disparate parameters. However, it is always feasible to construct a protected FSM. From the standpoint of developing a secure, commercially available solution, this research paper did not provide additional elaboration. Instead, it was assumed that the methods for implementing safe control systems, which have been well developed, would be used after synthesizing the control model [1,4,5,8,10].
In the future, an interesting solution would be the creation of an adaptive train traffic control system. Such a system would monitor analog parameters, control pre-failure states, and transmit data to the dispatching system, with automatic confirmation of changes in train traffic. However, these issues fall outside the scope of this paper.

8. Conclusions

This paper proposes a method for synthesizing finite-state machines for railway automation and remote control units. This method enables the synthesis of self-checking structures that can transit to pre-failure and protective states. These functions enable the integration of control and state monitoring tools, providing timely intervention in the event of device malfunctions. This reduces the likelihood of train schedule disruptions and failures.
The logical descriptions of the functioning and mutual alignment of intermediate station facility control systems represent the complexity of their synthesis. The issue of providing a logical description is less challenging for intermediate stations compared to those with a more complex topology. However, even in this case, it is possible to use typical implementations of finite-state machines for individual railway automation and remote control units.
The creation of an FSM to manage train traffic at stations may transpire in two distinct approaches. The first approach involves describing the conditions for transitioning between states for every possible object at the station and outlining the means of controlling them. It will be a single FSM. The second method involves creating models of FSMs for each automation unit. These models are then combined by constructing transition graphs, as demonstrated in this paper. This method is recommended since it enables the removal of states in individual device finite-state machines that are not necessary for analysis.
The potential for incorporating self-diagnostics and monitoring into these FSMs is worth considering. In order to monitor the operation of any railway automation installation and to document both pre-failure states and failures, internal states can be defined. This can be achieved, among other methods, by broadening a range of diagnostic parameters when fitting automation devices with external monitoring sensors. An instance of such integration is presented in [6]. Incorporating states into the transition graph of an FSM that considers pre-failure states and failures enables the subsequent implementation of both a control system and an embedded diagnostic system. This diagnostic system makes it possible to simulate the operation of the unit during its intended use. It facilitates the rapid identification and correction of any malfunction. Thus, the control system and diagnostic system are combined, offering the potential to create a digital copy of the control system [2]. Further research can be conducted in this area.
A drawback to consider is that when dealing with actual railway automation and remote control systems, the FSM graphs may contain a high number of states, especially if diagnostic functions are added. Therefore, it is essential to consider the issues of finite-state machine decomposition when synthesizing an automaton model for routes [25].
The synthesis of self-checking devices in railway automation and remote control with the possibility of transitioning to protective and pre-failure states enables the implementation of a train traffic control system resistant to external destabilizing factors.

Author Contributions

Conceptualization, A.V.P. and D.V.E.; methodology, D.V.E.; validation, D.V.E., D.N.K., D.K.B. and D.K.R.; formal analysis, D.G.P. and A.V.B.; investigation, A.V.P. and D.V.E.; writing—original draft preparation, A.V.P., E.M.M. and D.V.E.; writing—review and editing, D.V.E. and V.V.K.; visualization, A.V.P., R.B.A., E.M.M. and A.V.L.; supervision, D.V.E.; project administration, D.V.E. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the Ministry of Science and Higher Education of the Russian Federation as part of the World-class Research Center program: Advanced Digital Technologies (contract No. 075-15-2022-311 dated 20 April 2022).

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data are contained within the article.

Conflicts of Interest

The authors declare no conflicts of interest.

References

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Figure 1. Single-line passing track plan.
Figure 1. Single-line passing track plan.
Computation 12 00171 g001
Figure 2. Transition graph for a single route.
Figure 2. Transition graph for a single route.
Computation 12 00171 g002
Figure 3. Transition graph for two routes.
Figure 3. Transition graph for two routes.
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Figure 4. Block diagram of a D-flip-flop-based FSM.
Figure 4. Block diagram of a D-flip-flop-based FSM.
Computation 12 00171 g004
Figure 5. A finite-state machine operation simulation. The red line in the Figure indicates the moment of completion of the finite state machine operation when the route is set, followed by its closure and return to the initial state. The green line in the Figure characterizes the moment of completion of the transfer of the system to the protective state (from the red line) and back (from the green line) upon receipt of input data that do not correspond to the logic of the system operation.
Figure 5. A finite-state machine operation simulation. The red line in the Figure indicates the moment of completion of the finite state machine operation when the route is set, followed by its closure and return to the initial state. The green line in the Figure characterizes the moment of completion of the transfer of the system to the protective state (from the red line) and back (from the green line) upon receipt of input data that do not correspond to the logic of the system operation.
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Figure 6. Block diagram of an FSM with embedded control circuits.
Figure 6. Block diagram of an FSM with embedded control circuits.
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Table 1. Table of train routes.
Table 1. Table of train routes.
RouteRoute NumberRoute NameTraffic LightRailway Switch Points
2413
Even yard neck
section
1Reception to T1E++
2Reception to T2E
3Reception to T3E+
4Dispatch from T1O2++
5Dispatch from T2O1
6Dispatch from T3O3+
Odd yard neck
section
7Reception to T1O ++
8Reception to T2O +
9Reception to T3O
10Dispatch from T1E1 ++
11Dispatch from T2E2 +
12Dispatch from T3E3
Notes. 1. The symbol “+” indicates the normal (“positive”) position of the arrow; 2. The symbol “−” indicates the translated (“minus”) position of the arrow.
Table 2. Table of shunting routes.
Table 2. Table of shunting routes.
RouteRoute NumberRoute NameRoute-Defining Railway Switch Point Electric Mechanism
Even
yard neck section
From
signal
S213To T1+2 +4
S214To T2−2
S215To T3+2 −4
O116Beyond the signal S2+2 +4
O317Beyond the signal S2−2
O218Beyond the signal S2+2 −4
Odd yard neck sectionFrom
signal
S119To T1+1 +3
S120To T2+1 −3
S121To T3−1
E122Beyond the signal S1+1 +3
E223Beyond the signal S1+1 −3
E324Beyond the signal S1−1
Table 3. Table of interdependencies of signal indications.
Table 3. Table of interdependencies of signal indications.
Route NameMovement Direction Is Up
Railway Signal Indications
EE1E2E3
Reception to T1Computation 12 00171 i001Computation 12 00171 i003
Reception to T2Computation 12 00171 i004 Computation 12 00171 i003
Reception to T3Computation 12 00171 i004 Computation 12 00171 i003
Pass through T1Computation 12 00171 i002Computation 12 00171 i002;Computation 12 00171 i001
Pass through T2Computation 12 00171 i004 Computation 12 00171 i002;Computation 12 00171 i001
Pass through T3Computation 12 00171 i004 Computation 12 00171 i002;Computation 12 00171 i001
Dispatch from T1 Computation 12 00171 i002;Computation 12 00171 i001
Dispatch from T2 Computation 12 00171 i002;Computation 12 00171 i001
Dispatch from T3 Computation 12 00171 i002;Computation 12 00171 i001
Route NameMovement Direction is Down
Railway Signal Indications
OO1O2O3
Reception to T1Computation 12 00171 i001Computation 12 00171 i003
Reception to T2Computation 12 00171 i004 Computation 12 00171 i003
Reception to T3Computation 12 00171 i004 Computation 12 00171 i003
Pass through T1Computation 12 00171 i002Computation 12 00171 i002;Computation 12 00171 i001
Pass through T2Computation 12 00171 i004 Computation 12 00171 i002;Computation 12 00171 i001
Pass through T3Computation 12 00171 i004 Computation 12 00171 i002;Computation 12 00171 i001
Dispatch from T1 Computation 12 00171 i002;Computation 12 00171 i001
Dispatch from T2 Computation 12 00171 i002;Computation 12 00171 i001
Dispatch from T3 Computation 12 00171 i002;Computation 12 00171 i001
Table 4. Table of states when locking a route.
Table 4. Table of states when locking a route.
StateInput Parameter Vectors
<x1 x2 … x9>
Notation for
the Parameter
Vectors Set
Output Vector <z1 z2z7>Notation for
the Output
Vectors Set
Q1—The route is released0 0 0 ~ ~ ~ 0 0 0X1~ ~ 0Z1
Route track preparation
Q2—Reception from E to T11 1 2 1 0 0 0 0 0X21 1 0 0 0 0 0Z2
Q3—Reception from E to T21 1 3 1 1 ~ 0 0 0X32 ~ 0 0 0 0 0Z3
Q4—Reception from E to T31 1 4 1 0 1 0 0 0X41 2 0 0 0 0 0Z4
Q5—Dispatch from T1 beyond E1 2 1 1 0 0 0 0 0X51 1 0 0 0 0 0Z5
Q6—Dispatch from T2 beyond E1 3 1 1 1 ~ 0 0 0X62 ~ 0 0 0 0 0Z6
Q7—Dispatch from T3 beyond E1 4 1 1 0 0 0 0 0X71 2 0 0 0 0 0Z7
Q8—From S2 to T12 5 2 1 0 0 0 0 0X81 1 0 0 0 0 0Z8
Q9—From S2 to T22 5 3 1 1 ~ 0 0 0X92 ~ 0 0 0 0 0Z9
Q10—From S2 to T32 5 4 1 0 1 0 0 0X101 2 0 0 0 0 0Z10
Q11—From T1 beyond signal S22 2 5 1 0 0 0 0 0X111 1 0 0 0 0 0Z11
Q12—From T2 beyond signal S22 3 5 1 1 ~ 0 0 0X122 ~ 0 0 0 0 0Z12
Q13—From T3 beyond signal S22 4 5 1 0 1 0 0 0X131 2 0 0 0 0 0Z13
Route locking
Q14—Reception from E to T11 1 2 1 0 0 1 1 1X145 5 1 0 0 0 0Z14
Q15—Reception from E to T21 1 3 1 1 ~ 1 1 1X156 ~ 1 0 0 0 0Z15
Q16—Reception from E to T31 1 4 1 0 1 1 1 1X165 6 1 0 0 0 0Z16
Q17—Dispatch from T1 beyond E1 2 1 1 0 0 1 1 1X175 5 0 1 0 0 0Z17
Q18—Dispatch from T2 beyond E1 3 1 1 1 ~ 1 1 1X186 ~ 0 0 1 0 0Z18
Q19—Dispatch from T3 beyond E1 4 1 1 0 0 1 1 1X195 6 0 0 0 1 0Z19
Q20—From S2 to T12 5 2 1 0 0 1 1 1X205 5 0 0 0 0 1Z20
Q21—From S2 to T22 5 3 1 1 ~ 1 1 1X216 ~ 0 0 0 0 1Z21
Q22—From S2 to T32 5 4 1 0 1 1 1 1X225 6 0 0 0 0 1Z22
Q23—From T1 beyond signal S22 2 5 1 0 0 1 1 1X235 5 0 1 0 0 0Z23
Q24—From T2 beyond signal S22 3 5 1 1 ~ 1 1 1X246 ~ 0 0 1 0 0Z24
Q25—From T3 beyond signal S22 4 5 1 0 1 1 1 1X255 6 0 0 0 1 0Z25
Q26—Protective state Ω i * X26~ ~ 0 0 0 0 0Z26
Note: The symbol Ω* represents a set of vectors, Ω * = Ω \ Ω + , where Ω denotes the entire set of code vectors and Ω+ indicates the state code vectors used in the finite-state machine.
Table 5. State table for setting two routes.
Table 5. State table for setting two routes.
StateInput Parameter
Vectors
Notation for
the Parameter
Vectors Set
Output Vector Values Notation for
the Parameter
Vectors Set
Q1—The route is released00 000 000 ~ ~~ ~~ 0 0 0X1001 001 0 0 0 0 0Z1
Route track preparation
Q2—Reception from E to T101 001 010 1 00 00 0 0 0X2001 001 0 0 0 0 0Z2
Q4—Reception from E to T201 001 100 1 00 00 0 0 0X4001 010 0 0 0 0 0Z’3
Route locking
Q14—Reception from E to T101 001 010 1 00 00 1 1 1X14101 101 1 0 0 0 0Z14
Q16—Reception from E to T201 001 100 1 01 00 1 1 1X16101 110 1 0 0 0 0Z15
Q26—Protective state Ω i * X26000 000 0 0 0 0 0Z26
Note: The symbol Ω* represents a set of vectors, Ω * = Ω \ Ω + , where Ω denotes the entire set of code vectors and Ω+ indicates the state code vectors used in the finite-state machine.
Table 6. Minimized table of FSM transitions and outputs.
Table 6. Minimized table of FSM transitions and outputs.
Qx1x2x3x4x5x6x7x8x9x10
0000
000
000
0000
001
000
0000
010
000
0000
011
000
0000
100
000
0000
101
000
0000
110
000
0000
111
000
1101
101
000
1110
100
111
1101
100
111
1110
101
111
A*
1 (Q1)(1), Z1(1), Z1(1), Z1(1), Z1(1), Z1(1), Z1(1), Z1(1), Z12, Z23,Z46, Z266, Z266, Z26
2 (Q2)6, Z266, Z266, Z266, Z266, Z266, Z266, Z266, Z26(2), Z26, Z264,Z146, Z266, Z26
3 (Q4)6, Z266, Z266, Z266, Z266, Z266, Z266, Z266, Z266, Z26(3),Z46, Z265, Z166, Z26
4 (Q14)1, Z11, Z11, Z11, Z11, Z11, Z11, Z11, Z16, Z266, Z26(4), Z146, Z266, Z26
5 (Q16)1, Z11, Z11, Z11, Z11, Z11, Z11, Z11, Z16, Z266, Z266, Z26(5), Z166, Z26
6 (Q26)1, Z11, Z11, Z11, Z11, Z11, Z11, Z11, Z1(6), Z26(6), Z26(6), Z26(6), Z26(6), Z26
Table 7. State encoding.
Table 7. State encoding.
QEncoded State
1001
2010
3011
4100
5101
6000
Table 8. Encoded transition table of an FSM.
Table 8. Encoded transition table of an FSM.
Qx1x2x3x4x5x6x7x8x9x10
0000
000
000
0000
001
000
0000
010
000
0000
011
000
0000
100
000
0000
101
000
0000
110
000
0000
111
000
1101
101
000
1110
100
111
1101
100
111
1110
101
111
A*
001(001)(001)(001)(001)(001)(001)(001)(001)010011000000000
010000000000000000000000000(010)000100000000
011000000000000000000000000000(011)000101000
100001001001001001001001001000000(100)000000
101001001001001001001001001000000000(101)000
000001001001001001001001001(000)(000)(000)(000)(000)
Table 9. Table of definition of the YD functions’ values.
Table 9. Table of definition of the YD functions’ values.
y(t ‒ 1)y(t)
01
000
111
Table 10. The YD-flip-flop truth table inclusion functions.
Table 10. The YD-flip-flop truth table inclusion functions.
Decimal Number of a Binary Vectorx1x2x3x4x5x6x7x8x9x10 y1y2y3YD1YD2YD3z1z2z3z4z5z6z7z8z9z10z11
00000000000 00000100000000000
10000000000 00100100000000000
20000000000 01000000000000000
30000000000 01100000000000000
40000000000 10000100000000000
50000000000 10100100000000000
640000001000 00000100000000000
650000001000 00100100000000000
660000001000 01000000000000000
670000001000 01100000000000000
680000001000 10000100000000000
690000001000 10100100000000000
1280000010000 00000100000000000
1290000010000 00100100000000000
1300000010000 01000000000000000
1310000010000 01100000000000000
1320000010000 10000100000000000
1330000010000 10100100000000000
1920000011000 00000100000000000
1930000011000 00100100000000000
1940000011000 01000000000000000
1950000011000 01100000000000000
1960000011000 10000100000000000
1970000011000 10100100000000000
2560000100000 00000100000000000
2570000100000 00100100000000000
2580000100000 01000000000000000
2590000100000 01100000000000000
2600000100000 10000100000000000
2610000100000 10100100000000000
3200000101000 00000100000000000
3210000101000 00100100000000000
3220000101000 01000000000000000
3230000101000 01100000000000000
3240000101000 10000100000000000
3250000101000 10100100000000000
3840000110000 00000100000000000
3850000110000 00100100000000000
3860000110000 01000000000000000
3870000110000 01100000000000000
3880000110000 10000100000000000
3890000110000 10100100000000000
4480000111000 00000100000000000
4490000111000 00100100000000000
4500000111000 01000000000000000
4510000111000 01100000000000000
4520000111000 10000100000000000
4530000111000 10100100000000000
69681101100111 00000000000000000
69691101100111 00100000000000000
69701101100111 01010010110110000
69711101100111 01100000000000000
69721101100111 10010010110110000
69731101100111 10100000000000000
69761101101000 00000000000000000
69771101101000 00101000100100000
69781101101000 01001000100100000
69791101101000 01100000000000000
69801101101000 10000000000000000
69811101101000 10100000000000000
74881110101000 00000000000000000
74891110101000 00101100101000000
74901110101000 01000000000000000
74911110101000 01101100101000000
74921110101000 10000000000000000
74931110101000 10100000000000000
75441110101111 00000000000000000
75451110101111 00100000000000000
75461110101111 01000000000000000
75471110101111 01110110111010000
75481110101111 10000000000000000
75491110101111 10110110111010000
-A **00000000000000
Table 11. Parameters of the finite-state machine designed.
Table 11. Parameters of the finite-state machine designed.
FamilyCyclone V
Device5CEBA2F17A7
Logic utilization (in ALMs)14
Total registers16
Total pins17
Table 12. Finding control functions at memory cell outputs.
Table 12. Finding control functions at memory cell outputs.
Decimal Number of a Binary Vectorx1x2x3x4x5x6x7x8x9x10y1y2y3YD1YD2YD3rr (mod4)g1g2
00000000000 0000013311
10000000000 0010013311
20000000000 0100000000
30000000000 0110000000
40000000000 1000013311
50000000000 1010013311
640000001000 0000013311
650000001000 0010013311
660000001000 0100000000
670000001000 0110000000
680000001000 1000013311
690000001000 1010013311
1280000010000 0000013311
1290000010000 0010013311
1300000010000 0100000000
1310000010000 0110000000
1320000010000 1000013311
1330000010000 1010013311
1920000011000 0000013311
1930000011000 0010013311
1940000011000 0100000000
1950000011000 0110000000
1960000011000 1000013311
1970000011000 1010013311
2560000100000 0000013311
2570000100000 0010013311
2580000100000 0100000000
2590000100000 0110000000
2600000100000 1000013311
2610000100000 1010013311
3200000101000 0000013311
3210000101000 0010013311
3220000101000 0100000000
3230000101000 0110000000
3240000101000 1000013311
3250000101000 1010013311
3840000110000 0000013311
3850000110000 0010013311
3860000110000 0100000000
3870000110000 0110000000
3880000110000 1000013311
3890000110000 1010013311
4480000111000 0000013311
4490000111000 0010013311
4500000111000 0100000000
4510000111000 0110000000
4520000111000 1000013311
4530000111000 1010013311
69681101100111 0000000000
69691101100111 0010000000
69701101100111 0101001101
69711101100111 0110000000
69721101100111 1001001101
69731101100111 1010000000
69761101101000 0000000000
69771101101000 0010102210
69781101101000 0100102210
69791101101000 0110000000
69801101101000 1000000000
69811101101000 1010000000
74881110101000 0000000000
74891110101000 0010115101
74901110101000 0100000000
74911110101000 0110115101
74921110101000 1000000000
74931110101000 1010000000
75441110101111 0000000000
75451110101111 0010000000
75461110101111 0100000000
75471110101111 0111014000
75481110101111 1000000000
75491110101111 1011014000
-A**0000000
Table 13. Finding the first encoder functions.
Table 13. Finding the first encoder functions.
YD1 YD2 YD3.g*1g*2
0 0 000
0 0 111
0 1 010
0 1 101
1 0 001
1 0 100
1 1 0~~
1 1 1~~
Table 14. Finding control functions at the FSM outputs.
Table 14. Finding control functions at the FSM outputs.
Decimal Number of a Binary Vectorx1x2x3x4x5x6x7x8x9x10y1y2y3z1z2z3z4z5z6z7rr (mod8)g1g2g3
00000000000 000000000000000
10000000000 001000000000000
20000000000 010000000000000
30000000000 011000000000000
40000000000 100000000000000
50000000000 101000000000000
640000001000 000000000000000
650000001000 001000000000000
660000001000 010000000000000
670000001000 011000000000000
680000001000 100000000000000
690000001000 101000000000000
1280000010000 000000000000000
1290000010000 001000000000000
1300000010000 010000000000000
1310000010000 011000000000000
1320000010000 100000000000000
1330000010000 101000000000000
1920000011000 000000000000000
1930000011000 001000000000000
1940000011000 010000000000000
1950000011000 011000000000000
1960000011000 100000000000000
1970000011000 101000000000000
2560000100000 000000000000000
2570000100000 001000000000000
2580000100000 010000000000000
2590000100000 011000000000000
2600000100000 100000000000000
2610000100000 101000000000000
3200000101000 000000000000000
3210000101000 001000000000000
3220000101000 010000000000000
3230000101000 011000000000000
3240000101000 100000000000000
3250000101000 101000000000000
3840000110000 000000000000000
3850000110000 001000000000000
3860000110000 010000000000000
3870000110000 011000000000000
3880000110000 100000000000000
3890000110000 101000000000000
4480000111000 000000000000000
4490000111000 001000000000000
4500000111000 010000000000000
4510000111000 011000000000000
4520000111000 100000000000000
4530000111000 101000000000000
69681101100111 000000000000000
69691101100111 001000000000000
69701101100111 0101011011215101
69711101100111 011000000000000
69721101100111 1001011011215101
69731101100111 101000000000000
69761101101000 000000000000000
69771101101000 001001001091001
69781101101000 010001001091001
69791101101000 011000000000000
69801101101000 100000000000000
69811101101000 101000000000000
74881110101000 000000000000000
74891110101000 001001010080000
74901110101000 010000000000000
74911110101000 011001010080000
74921110101000 100000000000000
74931110101000 101000000000000
75441110101111 000000000000000
75451110101111 001000000000000
75461110101111 010000000000000
75471110101111 0111011101204100
75481110101111 100000000000000
75491110101111 1011011101204100
-A **000000000000
Table 15. Finding the first encoder functions.
Table 15. Finding the first encoder functions.
z1z2z3 z4 z5 z6 z7g*1g*2g*3
0 0 0 0 0 0 0000
0 0 1 0 0 1 0001
0 0 1 0 1 0 0000
1 0 1 1 0 1 1101
1 0 1 1 1 0 1100
A ***~~~
Table 16. ECC parameters for monitoring indoor units.
Table 16. ECC parameters for monitoring indoor units.
FamilyCyclone V
Device5CEBA2F17A7
Logic utilization (in ALMs)10
Total registers0
Total pins22
Table 17. ECC parameters for monitoring PV.
Table 17. ECC parameters for monitoring PV.
FamilyCyclone V
Device5CEBA2F17A7
Logic utilization (in ALMs)9
Total registers0
Total pins28
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Efanov, D.V.; Pashukov, A.V.; Mikhailiuta, E.M.; Khóroshev, V.V.; Abdullaev, R.B.; Plotnikov, D.G.; Banite, A.V.; Leksashov, A.V.; Khomutov, D.N.; Baratov, D.K.; et al. Synthesis of Self-Checking Circuits for Train Route Traffic Control at Intermediate Stations with Control of Calculations Based on Weight-Based Sum Codes. Computation 2024, 12, 171. https://doi.org/10.3390/computation12090171

AMA Style

Efanov DV, Pashukov AV, Mikhailiuta EM, Khóroshev VV, Abdullaev RB, Plotnikov DG, Banite AV, Leksashov AV, Khomutov DN, Baratov DK, et al. Synthesis of Self-Checking Circuits for Train Route Traffic Control at Intermediate Stations with Control of Calculations Based on Weight-Based Sum Codes. Computation. 2024; 12(9):171. https://doi.org/10.3390/computation12090171

Chicago/Turabian Style

Efanov, Dmitry V., Artyom V. Pashukov, Evgenii M. Mikhailiuta, Valery V. Khóroshev, Ruslan B. Abdullaev, Dmitry G. Plotnikov, Aushra V. Banite, Alexander V. Leksashov, Dmitry N. Khomutov, Dilshod Kh. Baratov, and et al. 2024. "Synthesis of Self-Checking Circuits for Train Route Traffic Control at Intermediate Stations with Control of Calculations Based on Weight-Based Sum Codes" Computation 12, no. 9: 171. https://doi.org/10.3390/computation12090171

APA Style

Efanov, D. V., Pashukov, A. V., Mikhailiuta, E. M., Khóroshev, V. V., Abdullaev, R. B., Plotnikov, D. G., Banite, A. V., Leksashov, A. V., Khomutov, D. N., Baratov, D. K., & Ruziev, D. K. (2024). Synthesis of Self-Checking Circuits for Train Route Traffic Control at Intermediate Stations with Control of Calculations Based on Weight-Based Sum Codes. Computation, 12(9), 171. https://doi.org/10.3390/computation12090171

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