A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
Abstract
:Featured Application
Abstract
1. Introduction
2. Operation Principle of the Proposed DTC
2.1. Principle of Vernier DTC
2.2. Circuit Description of 3D Vernier DTC
3. Experimental Results
3.1. Implementation with Cyclone IV E FPGA
3.2. Implementation with Stratix III FPGA
4. Discussion
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Cyclone IV E | Stratix III | |
---|---|---|
Fabrication Process | 90 nm | 65 nm |
Input frequency | 5–474 MHz | 5–717 MHz |
Output frequency | 600–1300 MHz | 600–1600 MHz |
Input Divisor (D) | 1–512 | 1–512 |
Feedback Divisor (N) | 1–512 | 1–512 |
Post scale counter (C) | 1–512 | 1–512 |
Cyclone IV E DTC | Stratix III | |
---|---|---|
Process | 90 nm | 65 nm |
Input Frequency | 50 MHz | 50 MHz |
Output Fast Frequency | 160 MHz | 640 MHz |
Output Medium Frequency | 155 MHz | 635 MHz |
Output Slow Frequency | 150 MHz | 630 MHz |
Input Bits | 32 | 48 |
Theoretical Resolution | 13.44ps | 195fs |
PLLs | 3 | 3 |
ALUTs | 344 | 448 |
Dedicated Logic Registers | 201 | 237 |
Power Consumption | 160 mW | 210 mW |
[7] | [8] | [11] | [18] | [19] | This Work | ||
---|---|---|---|---|---|---|---|
Process | 28 nm FPGA | 40 nm FPGA | 65 nm FPGA | 40 nm FPGA | 65 nm ASIC | 90 nm FPGA | 65 nm FPGA |
Power | - | 196 mW | 681 mW* | 165 mW | 72 mW | 160 mW | 210 mW |
Principle | VPDL | Dual PLLs | Dual PLLs | VPDL | Dual PLLs | Three PLLs | |
Working Frequency | 500 MHz | 100.04 MHz | 1025 MHz | 200 MHz | >1 GHz | 160 MHz | 640 MHz |
Resolution | 10ps | 3.93ps | 1.58ps | 1.02ps | 6.25ps | 13.5ps | 203.3fs |
Dynamic range | 8 s | 43 s | 59.3 min | 590 ns | 100 ns | 58 ms | 54 s |
Integrated Linearity (LSB) | −1.09–4.73 | −2.6–2.5 | −0.93–0.75 | −0.35–0.62 | <15 | −0.43–0.58 | −3.8–4.4 ** |
Integrated Linearity (ps) | −10.9–47.3 | −10.2–9.8 | −1.47–1.19 | −0.36–0.63 | <93.8 | −5.8–7.83 | −0.76–0.88 ** |
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Yan, C.; Hu, C.; Wu, J. A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA. Appl. Sci. 2019, 9, 2705. https://doi.org/10.3390/app9132705
Yan C, Hu C, Wu J. A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA. Applied Sciences. 2019; 9(13):2705. https://doi.org/10.3390/app9132705
Chicago/Turabian StyleYan, Chenggang, Chen Hu, and Jianhui Wu. 2019. "A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA" Applied Sciences 9, no. 13: 2705. https://doi.org/10.3390/app9132705
APA StyleYan, C., Hu, C., & Wu, J. (2019). A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA. Applied Sciences, 9(13), 2705. https://doi.org/10.3390/app9132705