In this section, we first describe the methods used for the filter design, then illustrate the fabrication steps, and finally introduce the characterization setup.
2.1. Filter Design
In order to obtain a proper filter design, we started with a simple mathematical description of an ideal ring resonator transfer function, comparing it with the filter requirements that are reported in Table 1
. It is worth noting that the requirements of the adjacent and non-adjacent suppression of channels are relatively relaxed, as the structure of next-generation passive optical network units (ONUs) often has the optical signal passing through two filters. On the other hand, this introduces the requirement of an extremely low filter insertion loss (IL).
By analyzing the filter-cascade transfer function, we determined that a cascade of at least two resonators is required to satisfy the requirements of a Si-photonic-based WDM NG-PON, and that the bus-to-ring (kB) and ring-to-ring (kR) field-coupling-coefficients, should be set to 0.26 and 0.05, respectively.
Following this, we performed a series of 3D-FDTD simulations, to identify the geometry of waveguides and coupling regions that could provide the desired coupling coefficients. All simulations were performed using the commercially available “FDTD Solutions” (by Lumerical Solutions Inc., Vancouver, BC V6E 2M6, Canada), by considering the silicon waveguide and resonator structures to be fully surrounded by SiO2
cladding layers, and by working on TE light polarization. Furthermore, minimum feature sizes and other manufacturing constraints were provided by the fabrication procedures at the CMOS-compatible Si-photonic foundry of CEA-Leti. The principal limits imposed by the fabrication and overall integration requirements are:
the minimum gap between adjacent waveguides was set to 200 nm, in order to allow a full-etch of the region using standard lithographic techniques;
the bus waveguide had to be 500 nm wide, so as to match the width of the waveguides used for the other components of the final chip;
the height of the waveguides could be 220 nm (corresponding to the height of the Si layer present on the SOI wafers), or could be reduced to 100 nm, as a fabrication step with a 120-nm etch depth was already present in the process flow, but no other height-value could be used for the filter’s design;
it was important to realize a fabrication-tolerant design, as the fabrication process was based on standard lithographic techniques and was not exploiting the e-beam high-resolution, as often done in scientific research where performance is the main challenge and production-price is not an issue.
Analysis immediately identified that standard (500 × 220 nm, width × height) Si-waveguides could not achieve the required bus-ring coupling coefficient, while maintaining a waveguide-to-waveguide gap > 200 nm. However, by taking advantage of the fact that the TE optical mode propagating in height-reduced waveguides more deeply extends outside of the Si-core (see the top part of Figure 1
), it is possible to increase the waveguide coupling coefficients. This creates the possibility of two different solutions, which were investigated separately—(i) the use of race-track resonators with standard waveguide; and (ii) the use of reduced-height waveguides with a curved coupling region.
In both cases, the coupling region is increased, which provides a higher coupling efficiency. In addition, for the second case (curved coupling region), we expect a reduction of propagation losses [19
], and a simultaneous increase of the coupling coefficients, as the optical mode further expands outside of the waveguide-core region.
For racetrack-based filters, the length of the straight section was initially determined through numerical simulations, so as to obtain the required coupling (while keeping the gap between the bus waveguide and the resonator equal to 200 nm). The curvature radius was then calculated, based on the free-spectral-range constraints reported in Table 1
. Finally, the inter-resonator gap was determined, as once the racetrack shape is fixed, there is only one possible inter-resonator gap which can be used to obtain the desired coupling coefficient kR.
The ring-based filters were initially defined so that the ring radius matched the physical length of the racetrack filters, and were then analyzed with regard to the dependence of the coupling coefficients on both the bus-to-ring gap, and the ring-waveguide width. Two principal constraints limited the range of solutions that could be considered—(i) the bus waveguide width was kept equal to 500 nm, to allow easy matching with the other on-chip components; (ii) the waveguide height was set to 100 nm, as this value was achievable without requiring additional processing steps in the fabrication of the overall chip.
It is worth underlining that, while having the possibility to tune the waveguide height would have yielded an interesting degree of freedom, the design efforts were aimed at obtaining the best performance, while using only standard, and previously validated, CMOS processes, available at the CEA-Leti Si-photonics foundry. Therefore, only 220-nm and 100-nm high waveguides were considered.
2.2. Structures Parameters
The design procedure for the racetrack-based structure was quite straight-forward, and identified the configuration described in the third column of Table 2
In contrast, the parameters for the design of the rings-based filters required a deeper analysis, because the necessary coupling coefficient could be obtained by a range of different resonator waveguide-width and Bus-to-Resonator gap combinations. Therefore, the selection of the optimum width-&-gap combinations was made by accounting for the tolerances in the design for minimum feature sizes and fabrication deviations. For this reason, we plotted a contour map of the achievable bus-to-waveguide coupling, expressed in logarithmic units, as a function of the width and gap parameters.
The results of this analysis, shown in Figure 2
, highlight that the tolerances offered by different designs can be very different. The plots allow the parameters of the most tolerant design to be identified, for designs with widths in the range of 800–850 nm (i.e., 6% tolerance), and gaps in the range of 400–420 nm (i.e., 5% tolerance). These can still deliver the required coupling coefficient, with a deviation of just ± 0.5 dB. It is worth noticing that, once the waveguide width was selected, the inter-resonator gap can be immediately derived by numerical simulations, because it is the only parameter that can be tuned to achieve the desired kR
(see Table 2
2.3. Fabrication Procedure
The 200 mm SOI (silicon on insulator) wafers have a 220 nm thick silicon-layer, and a 2 µm thick buried oxide layer, and were processed with a MPW (multi-project wafer) run at the CEA-Leti Si-photonics foundry, using standard CMOS process flows. An initial step in the wafer-processing, is the definition of the fiber grating-couplers by 193 nm DUV lithography, and a specific 120 nm partial etch of the Si-layer (with a uniformity better than 3% for the whole wafer). This partial etch is used to pattern the fiber couplers, and to define the height of the reduced-height 100 nm strip waveguides (220 nm Si-layer − 120 nm Si-etch = 100 nm Si-waveguide), used to achieve our low-loss micro-resonator filters. The realized gratings allowed the coupling of light directly from the input fiber to the Si waveguide, which was either 220-nm high or 100-nm high, according to the considered filter design.
The other etching process used has a depth of 220 nm ± 3% (full-etch), and a uniformity of 1.5% for the whole wafer. Both Si-etching processes are performed using ICP RIE, and dry etching equipment is used to obtain very low losses for optical waveguides. It must be noticed that this, fully CMOS-compatible, etching procedure is very different from the strategies that have been exploited in the past in order to realize height-reduced waveguides ([12
] and references therein), which required steam oxidation of the Si-layer and subsequent HF stripping.
A HDP (high density plasma) oxide cladding layer encapsulates the waveguide, and optically insulates the waveguide from the Ti/TiN heater, used to tune the filters. The oxide layer thickness is selected to give the best trade-off between heating efficiency and optical losses. The heater consists of a 10nm-thick layer of Ti (used for adhesion), and of a 110 nm-thick TiN resistive layer, that is patterned to create the thermo-optic phase shifter above the waveguide. Finally, a silicon-oxide cladding layer is deposited, and a tungsten via is added, to make contact with the heater layer. This oxide layer provides optical isolations from the aluminum metallization, used for electrical routing to the contact pads. A schematic cross-section of the full device is shown in Figure 3
a, with a top-view microscope image of the racetrack-based structure in Figure 3