A Scalable Parallel Architecture Based on Many-Core Processors for Generating HTTP Traffic
Abstract
:1. Introduction
- The software architecture of a Web traffic generation system is proposed by using the hierarchical design methodology including the control layer, virtual user layer and traffic generation layer, to provide high scalability.
- We present a user-control method using the cubic spline interpolation based on the analysis of the Web user behavior simulation method of accessing the real server. The method enables the system to generate the background traffic with the characteristics of a real network over a long time scale according to the Internet user’s access time in different scenarios.
- In order to meet the requirements of concurrency, we have implemented a TGMP prototype. Three high concurrency strategies are employed, which enable the system to simulate a large number of virtual users at the same time, and generate more Web traffic.
- We has been implemented and deployed in the real network at the third floor of the YiFu building in the CQUPT campus. The experiments show that compared with other systems, TGMP yields a more satisfactory performance in which 50,000 users access the Web server simultaneously.
2. Background and Challenges
2.1. Overview of the TILEGX36 Architecture
2.2. The Existing Approaches of Traffic Generation
2.3. Challenges
3. Traffic Generator Systems Architecture
4. User Control Method by Cubic Spline Interpolation
5. The High Concurrency Strategy
5.1. Optimization of Parameters
5.2. Event-Driven
5.3. Parallel Architectures on TILERAGX36
5.3.1. Task Decomposition
5.3.2. Task Mapping
5.3.3. IPC Scheme
5.3.4. Dynamic Load-Balancing Based on the Minimum Number of Requests (DMR)
6. Evaluation
6.1. Experimental Setup
6.2. The Traffic Self-Similarity
6.3. Load Balancing
6.4. Concurrent Performance
6.5. System Stability
6.6. Comparison with Existing System
7. Conclusions
Supplementary Materials
Acknowledgments
Author Contributions
Conflicts of Interest
References
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Algorithm 1. Cubic Spline Interpolation Algorithm. |
---|
Input: the number of actual users N, actual online user percentage . |
Output: the virtual user reference set B, the number of active virtual user A. |
1. Compute the number of virtual users which satisfies |
where ; |
2. Obtain virtual users-time percent data in each time slot i calculated as |
; |
3. Use the cubic spline interpolation algorithm, and compute continuous time |
function based on interpolation processing ; |
4. Identify the time slot j which divides 24 h into 30 s; |
5. Initialize ; |
6. while h do |
7. ; |
8. ; |
9. end while |
10. Obtain the virtual user reference set B in chronological order; |
11. Assume the number of active virtual user in time slot j; |
12. while h do |
13. if then |
14. Delete out of active users. |
15. else |
16. Add extra active users. |
17. end if |
18. end while |
//procuring the CPU affinity |
cpu_set_t cpus; |
if (tmc_cpus_get_my_affinity(&cpus) != 0) |
tmc_task_die(“tmc_cpus_get_my_affinity() failed.”); |
//bind to the allocated CPU |
if (tmc_cpus_set_my_cpu(tmc_cpus_find_nth_cpu(&cpus, rank)) < 0) |
tmc_task_die(“tmc_cpus_set_my_cpu() failed.”); |
Tools | Performance | Method | Scalability | Technology | Platform |
---|---|---|---|---|---|
TRex | 200 Gb/s | Traffic Replay | Good | DPDK | Intel DPDK 1/10/40 Gbps interface support |
TGMP | Simulate 50,000 users User Behavior | User Behavior | Good | Many-core processor | TILERAGX36 |
MoonGen | Up to 178.5 Mpps at 120 Gbit/s | Traffic Model | General | DPDK | Modern commodity NICs is support for multi-core CPUs |
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Wang, X.; Xu, C.; Jin, W.; Wang, J.; Wang, Q.; Zhao, G. A Scalable Parallel Architecture Based on Many-Core Processors for Generating HTTP Traffic. Appl. Sci. 2017, 7, 154. https://doi.org/10.3390/app7020154
Wang X, Xu C, Jin W, Wang J, Wang Q, Zhao G. A Scalable Parallel Architecture Based on Many-Core Processors for Generating HTTP Traffic. Applied Sciences. 2017; 7(2):154. https://doi.org/10.3390/app7020154
Chicago/Turabian StyleWang, Xinheng, Chuan Xu, Wenqiang Jin, Jiajie Wang, Qianyun Wang, and Guofeng Zhao. 2017. "A Scalable Parallel Architecture Based on Many-Core Processors for Generating HTTP Traffic" Applied Sciences 7, no. 2: 154. https://doi.org/10.3390/app7020154
APA StyleWang, X., Xu, C., Jin, W., Wang, J., Wang, Q., & Zhao, G. (2017). A Scalable Parallel Architecture Based on Many-Core Processors for Generating HTTP Traffic. Applied Sciences, 7(2), 154. https://doi.org/10.3390/app7020154