Design of an SAR-Assisted Offset-Calibrated Chopper CFIA for High-Precision 4–20 mA Transmitter Front Ends

Abstract

In loop-powered 4–20 mA transmitter systems, sensors like temperature, pressure, flow, and gas sensors are chosen based on specific application requirements. These systems are widely adopted in high-precision measurement scenarios, including industrial automation, process control, and environmental monitoring. The transmitter requires a high-performance analog front end (AFE) for precise amplification and signal conditioning. This paper presents a low-noise instrumentation amplifier (IA) for high-precision transmitter front ends, featuring a Successive Approximation Register (SAR)-assisted offset calibration architecture. The proposed structure integrates a chopper current-feedback instrumentation amplifier (CFIA) with an automatic offset calibration loop (AOCL), significantly suppressing internal offset errors and enabling high-accuracy signal acquisition under stringent power and environmental temperature constraints. The designed amplifier provides four selectable gain settings, covering a range from ×32 to ×256. Fabricated in a 0.18 μm CMOS process, the CFIA operates at a 1.8 V supply voltage, consumes a static current of 182 μA, and achieves an input-referred noise as low as 20.28 nV/√Hz at 1 kHz, with a common-mode rejection ratio (CMRR) up to 122 dB and a power-supply rejection ratio (PSRR) up to 117 dB. Experimental results demonstrate that the proposed amplifier exhibits excellent performance in terms of input-referred noise, offset voltage, PSRR, and CMRR, making it well-suited for front-end detection in field instruments that require direct interfacing with measured media.

1. Introduction

In modern 4–20 mA transmitter system-on-chip (SoC) applications, resistive sensors such as RTDs and Wheatstone bridges typically generate weak differential analog signals that require high-precision amplification and conditioning. To ensure reliable signal acquisition under harsh environmental and power-constrained conditions, the front-end circuit must exhibit low noise, high input impedance, high common-mode rejection ratio (CMRR), and high power supply rejection ratio (PSRR) [1,2]. Accordingly, the analog front end in this work incorporates a low-noise instrumentation amplifier (IA) with SAR-assisted offset calibration as its core signal acquisition stage, thereby achieving high accuracy and high integration [3].

In the design of instrumentation amplifiers (IAs), low noise, high input impedance, and low power consumption have always been key research objectives. Common IA architectures include the three-op-amp topology, capacitively coupled instrumentation amplifier (CCIA), and current-feedback instrumentation amplifier (CFIA). Conventionally, the well-known three-op-amp instrumentation amplifier (IA) [4,5,6] architecture offers high input impedance. However, its common-mode rejection ratio (CMRR) is highly sensitive to resistor matching, making it challenging to achieve consistently high CMRR performance. CCIA [7,8,9,10,11], by employing coupling capacitors for DC bias isolation, offers lower power and noise, making it suitable for on-chip integration and enabling a smaller area compared to the three-op-amp topology. However, due to its capacitive input, the CCIA’s input impedance is typically lower and requires a positive feedback loop to boost it [12], which can compromise stability. The current-feedback instrumentation amplifier (CFIA) is widely adopted in sensor interface circuits due to its several advantages, such as high input impedance, high common-mode rejection ratio (CMRR), and low power consumption [13,14,15,16,17,18]. However, its input offset voltage and noise can degrade sampling accuracy. To achieve low-noise performance in instrumentation amplifiers (IAs), techniques such as auto-zeroing, correlated double sampling (CDS), and chopper stabilization are commonly employed [19,20,21]. Unlike thermal noise, flicker noise and DC offset fall within the same frequency band as the sensor signal. Their suppression is essential to ensure measurement accuracy, as they can directly superimpose on the useful signal. Auto-zeroing and CDS suppress low-frequency noise and offset by sampling the offset voltage on input capacitors and canceling it out. However, these sampling techniques can introduce aliasing, causing high-frequency thermal noise to fold into the baseband and degrade overall system performance. Chopper stabilization mitigates this issue by up-converting flicker noise and DC offset to higher frequencies, which effectively reduces baseband noise and helps the system achieve thermal noise-limited performance. Nevertheless, this modulation process introduces ripple components at the output, which can compromise signal purity. To further suppress this ripple, a ripple reduction loop (RRL) is typically employed. The RRL demodulates the ripple signal and feeds it back through an integrator to the amplifier’s input, effectively reducing output ripple while preserving the chopper’s low-frequency noise suppression capability [22].

However, conventional chopper CFIA architectures, though effective in suppressing 1/f noise and low-frequency offset, still face two critical issues: (1) the ripple signal introduced by the chopping process is up-modulated to the output, impacting system accuracy [23]; and (2) they cannot achieve dynamic correction of long-term offset drift caused by temperature variation, aging, and other effects, thereby limiting their application in high-precision and long-term stable systems.

To address these challenges, this paper proposes a low-noise instrumentation amplifier based on the CFIA topology, which incorporates chopper modulation, SAR-assisted automatic offset calibration, and ripple reduction techniques. By integrating SAR logic and a high-resolution DAC, the static offset can be adaptively compensated. Furthermore, a ripple reduction loop (RRL) is implemented to suppress the modulated residuals, thereby improving the system’s signal acquisition accuracy and long-term stability under low-power conditions. This design is especially suitable for high-performance resistive sensor interface applications.

2. Circuit Implementation

This paper presents a low-power, low-noise instrumentation amplifier for sensor-based temperature transmitter systems. The overall architecture of the transmitter is illustrated in Figure 1. The system primarily consists of a differential input; auto-offset-calibration-assisted current-feedback instrumentation amplifier (CFIA); a fourth-order low-pass filter (LPF); a buffer; and a 16-bit sigma-delta ADC. In addition, several auxiliary modules are integrated on chip, including an on-chip temperature sensor, a high-precision current source circuit with multipoint trimming, a reference circuit, a low-dropout (LDO) linear regulator, a frequency-locked loop (FLL), a chopper clock generator, and a serial peripheral interface (SPI).

The CFIA front end features high input impedance and employs a nested compensation scheme (via a cascaded low-noise amplifier topology) to ensure overall amplifier stability. To compensate for DC offset errors caused by transistor mismatch, temperature drift, or packaging stress, the system incorporates an automatic offset calibration loop (AOCL) based on SAR logic for static offset compensation.

Moreover, to further improve output signal quality, a chopper modulation residual ripple reduction loop (RRL) is implemented at the amplifier output. This loop, utilizing capacitive coupling and a differential transconductance structure, effectively filters out residual modulated ripple. The gain of the CFIA amplifier can be programed via a 2-bit decoder, supporting four selectable gain settings, 30.10 dB, 32.12 dB, 42.14 dB, and 48.16 dB, thus meeting the requirements of various sensor interfaces with different signal strengths.

Basic Structure and Gain Characterization of the CFIA

The current-feedback instrumentation amplifier (CFIA) has been widely adopted in various sensor signal acquisition applications due to its high input impedance, low noise, and low power consumption. As illustrated in Figure 2, the typical architecture of a CFIA consists of three transconductance amplifiers (G_m1, G_m2, and G_m3), where the output current is fed back to the input node through a resistive network, forming a current-feedback closed loop that enables stable gain control.

The output voltage of this structure can be expressed as:

$$V_o=\left({\displaystyle \frac{G_{m1}\cdot G_{m3}}{1+\frac{R_1}{2R_2+R_1}{G}_{m2}{G}_{m3}}}\right)\cdot V_{DM}+\left({\displaystyle \frac{\Delta G_{m1}}{1+\frac{R_1}{2R_2+R_1}{G}_{m2}{G}_{m3}}}\right)\cdot V_{CM}$$

(1)

When G_m1 = G_m2 and the product of G_m1 and G_m3 is sufficiently large, the closed-loop gain of the system can be approximated as:

$$V_o\approx \left(1+{\displaystyle \frac{2R_2}{R_1}}\right)\cdot V_{DM}$$

(2)

It can be seen that the gain of the CFIA is primarily determined by the feedback resistor ratio R₂/R₁, which enables programable gain control. To achieve high gain accuracy, close matching between G_m1 and G_m2 is required, while the loop gain formed by G_m1 and G_m3 must be sufficiently large to ensure overall system precision.

3. Circuit Architecture and Implementation

3.1. Design of the Chopper-Modulated Input Stage Amplifier

Figure 3 illustrates the architecture of the proposed low-noise instrumentation amplifier (CFIA). It primarily consists of a differential-input transconductance stage (G_m11, G_m12), chopper modulation switches, an amplification chain (G_m2→G_m31→G_m4), an automatic offset calibration loop (AOCL), and a ripple reduction loop (RRL).

In practical applications, instrumentation amplifiers face challenges such as input DC offset voltage induced by device mismatch, process variations, and packaging stress, along with low-frequency 1/f noise inherent to MOS devices. To mitigate the offset and equivalent input noise caused by external factors and process variations, this work adopts an SAR-controlled AOCL calibration mechanism. This is combined with a front-end chopper modulation and back-end filtering strategy for 1/f noise suppression.

Specifically, the chopper switches modulate the input signal at a frequency of 150 kHz, up-converting low-frequency noise components to higher frequencies. These are then filtered out by a low-pass filter at the output to enhance signal purity. The automatic calibration structure employs SAR logic to control a high-resolution 12-bit R-2R DAC, performing successive approximation correction of the residual input offset at a 4 kHz cycle rate. This closed-loop structure effectively compensates for offset drift caused by temperature variations, aging, and process-induced mismatch.

To further enhance output drive capability and system linearity, a class-AB output stage is adopted. This stage provides rail-to-rail output swing, low power consumption, and high drive capability, meeting the requirements of subsequent interfacing stages.

3.2. Chopper-Modulated Input Stage Design

As illustrated in Figure 4, the front-end input transconductance amplifier adopts a folded cascode topology consisting of three main parts: G_m11, G_m12, and G_m2. This structure employs chopper modulation and gain-boosted transconductance stages, effectively suppressing both offset and noise while performing signal acquisition and primary amplification for sensor interfaces.

Specifically, G_m11 and G_m12 are responsible for capturing the input and feedback signals, respectively. The core transistors M1 and M2 sample the input differential signals, while M3 and M4 sense the output voltage across the feedback resistors. The chopper switches in series with their gates modulate both the input and feedback signals to a frequency of 150 kHz. The right-hand-side cascode chopper switches further modulate the 1/f noise of the MOS transistors to 150 kHz and demodulate the input and feedback signals back to the baseband. This modulation process effectively shifts low-frequency noise components to higher frequencies, allowing them to be filtered out by subsequent low-pass filters, thereby significantly improving the system’s low-frequency noise performance.

The input and feedback signals, converted into current signals by G_m11 and G_m12, are summed at the cascode transconductance amplifier G_m2. Owing to the use of gain-boosting techniques, G_m2 exhibits the highest output impedance in the entire CFIA and is connected to a compensation capacitor C_m2, making its output node the dominant pole of the CFIA. This amplifier provides high gain, which effectively suppresses the equivalent input noise generated by the subsequent stages. Additionally, it offers excellent common-mode rejection, minimizing the influence of common-mode voltage variations from the sensor.

$$A_v=g_{m1}\cdot \left(\left(g_{m14}\cdot r_{o14}\cdot A\cdot (r_{o16}\parallel r_{o1}\parallel r_{o4})\right)\parallel \left(g_{m12}\cdot A\cdot r_{o12}\cdot r_{o10}\right)\right)$$

(3)

In this context, g_m denotes the transconductance and A represents the gain of the amplifier used in the gain-boosting stage.

3.3. Design of the Intermediate and Output Stage Amplifiers

As shown in Figure 5, the intermediate and output amplification stages consist mainly of transconductance amplifiers G_m31, G_m32, and the class-AB output stage G_m4. This stage not only maintains the overall signal gain but also provides the necessary drive capability for subsequent modules.

G_m31 and G_m32 are differential transconductance amplifier units, receiving their input signals from the output of the preceding stage G_m2 and from the ripple reduction loop (RRL), respectively. The currents are summed through common-gate amplifiers M13 and M14. The output stage G_m4 adopts a class-AB topology, enabling rail-to-rail output swing with strong drive capability, thus effectively driving downstream circuits.

In addition, to maintain a stable-output common-mode level, a common-mode feedback (CMFB) circuit is implemented at the output. By sensing the output common-mode voltage and comparing it to a reference, the CMFB loop ensures that the output common-mode voltage is regulated at half of the supply voltage (VDD/2).

Since the CFIA amplifier presented in this work adopts a three-stage cascaded architecture, a nested Miller compensation (NMC) scheme [24] is introduced between G_m31, G_m32, and the output stage G_m4 to ensure the overall stability of the multistage amplification chain. As shown in Figure 6, this compensation technique employs feedback capacitors C_m1 and C_m2 between different gain stages to achieve pole splitting, thereby effectively suppressing system instability while preserving the high gain advantage provided by the multistage amplifier structure.

When a three-stage amplifier employs the nested Miller compensation (NMC) structure, its open-loop transfer function can be expressed as follows:

$$A_{v\_\mathrm{NMC}}(s)={\displaystyle \frac{g_{m1}{g}_{m2}{g}_{mL}{R}_1{R}_2{R}_o\left(1-s\frac{C_{m2}}{g_{mL}}-s^2\frac{C_{m1}{C}_{m2}}{g_{m2}{g}_{mL}}\right)}{\left(1+s{C}_{m1}{g}_{m2}{g}_{mL}{R}_1{R}_2{R}_o\right)\left[1+s\frac{C_{m2}(g_{mL}-g_{m2})}{g_{m2}{g}_{mL}}+s^2\frac{C_L{C}_{m2}}{g_{m2}{g}_{mL}}\right]}}$$

(4)

Due to the Miller effect, the dominant pole is located at $p_{-3dB}=1/C_{m1}{g}_{m2}{g}_{mL}{R}_1{R}_2{R}_o$. The above expression is valid under the condition that g_mL$\gg$, g_m1, and g_m2. Since this condition is assumed, both C_m1 and C_m2 are relatively small, and the right-half-plane zero introduced in the numerator becomes insignificant, having a negligible effect on the phase margin. Thus, the above equation can be further simplified as:

$$A_{v\_\mathrm{NMC}}(s)\approx {\displaystyle \frac{1}{s\frac{C_{m1}}{g_{m1}}\left(1+s\frac{C_{m2}}{g_{m2}}+s^2\frac{C_L{C}_{m2}}{g_{m2}{g}_{mL}}\right)}}$$

(5)

In the above expression, the non-dominant poles $p_2$ and $p_3$ correspond to the solutions of the quadratic term in the denominator. To ensure amplifier stability and a phase margin not lower than 60°, the following condition must be satisfied:

$${\displaystyle \frac{g_{m1}}{C_{m1}}}\le {\displaystyle \frac{1}{3}}\cdot {\displaystyle \frac{g_{m2}}{C_{m2}}}\le {\displaystyle \frac{1}{9}}\cdot {\displaystyle \frac{g_{mL}}{C_L}}$$

(6)

Based on the above expression, the phase margin can be calculated as ${\mathrm{PM}=90}^{\circ }{-\arctan (\mathrm{GBW}/p}_1{)-\arctan (\mathrm{GBW}/p}_2)\approx {65}^{\circ }$, which is sufficient to meet stability requirements across different process corners.

3.4. Ripple Reduction Loop: Circuit Structure and Implementation

The offset and input noise of the amplifier can be equivalently referred to the input of G_m31, where this voltage is denoted as V_OS. The offset voltage V_OS generates ripple at the output through the chopper CFIA. The ripple produced by V_OS at the output can be expressed as:

$$V_{\mathit{ripple}}={\displaystyle \frac{V_{\mathit{os}}\cdot G_{m31}}{2f_{\mathrm{chop}}\cdot C_{m1,2}}}$$

(7)

To suppress the ripple caused by noise and offset voltage, this work introduces an AC-coupled continuous-time ripple reduction loop (RRL). Figure 7 shows the complete block diagram of the RRL and the entire suppression process for the offset voltage V_OS. The RRL consists of sensing capacitors C_s1,2, a demodulation chopper, an integrator, and a compensation transconductor G_m32. The capacitors C_s1,2 sense and convert the large ripple voltage at the amplifier output into an AC current, which is then integrated by the integrator into a voltage. This voltage is further converted by G_m32 into a current to compensate for the offset current of G_m31. The RRL creates a notch at the chopping frequency, with a bandwidth determined by design parameters such as C_s1,2 and G_m4. Since C_s1,2 is loaded onto the amplifier output, its value should be kept as small as possible.

The integrator in the RRL consists of a current buffer and an integration capacitor. However, offset in the current buffer introduces second-harmonic ripple, requiring a large integration capacitor for adequate filtering—especially at low chopping frequencies. To address this issue, an auto-zeroed switched-capacitor (SC) integrator is adopted. Unlike conventional auto-zeroed SC integrators, which are reset during one phase to store the offset on an auto-zero capacitor (thus rendering the output unavailable for compensation during that phase), the proposed scheme ensures valid output voltage in all phases. The architecture of this RRL is depicted in Figure 8.

The demodulator operates synchronously with the chopper frequency. The remaining switches, SW1 and SW2, are operated at half the chopping frequency, as shown in Figure 3. Each SW1,2 switching cycle consists of an integration phase and an auto-zero phase, each covering a full chopping cycle. Therefore, during the integration phase, the RRL can sense a complete period of ripple. The phase diagram in Figure 3 details the timing relationship between the chopper and the SW phases. During the integration phase, C_s1,2 converts the ripple voltage into an AC current, which is demodulated and integrated on C_F1,2. The voltage on C_F1,2 is then converted by G_m4 into a current to compensate for the offset current of G_m1.

During the auto-zero phase, C_s1,2 are grounded to prevent further ripple current integration. The transconductor G_m operates in unity-gain configuration so that its offset can be sampled and stored on C_DS1,2. During this time, C_F1,2 are disconnected from the output of G_m, holding the terminal voltage of SW2, and connected to the input of G_m32. In this way, correct compensation current can be injected into G_m31 during both phases. Ideally, the compensation current fully cancels the offset current of G_m31, resulting in a ripple-free steady-state output.

As shown in Figure 8, a simplified schematic of the ripple reduction loop (RRL) is presented. Assuming that nodes D and E are virtual grounds, the following current relationships can be derived:

$$K={\displaystyle \frac{I_B}{I_E}}={\displaystyle \frac{C_4}{C_1}}$$

(8)

It can be deduced that the current I_C is integrated on the capacitor C₁ after passing through the chopper and differentiated at C_s and finally reaches node D via another chopper. The gain factor K between I_C and I_CS is independent of frequency. Since the current passes through two choppers operating at the same frequency, the error introduced by these choppers can be neglected. Therefore, the relationship between I_CS and I_C can also be expressed as K:

$$K={\displaystyle \frac{I_{CS}}{I_C}}={\displaystyle \frac{C_S}{C_1}}$$

(9)

Since the DC gain A₀ of the transconductor G_m is finite, node D is not an ideal virtual ground (though the error caused by the non-ideal virtual ground at nodes D and E is neglected in this work). Thus:

$$V_0=-A_0{V}_i$$

(10)

After the current flows through capacitor C_s and then passes through the chopper, the equivalent impedance seen from the non-ideal virtual ground of the integrator (node D) toward the chopper can be expressed as:

$$Z_{SC4}={\displaystyle \frac{1}{f_c\cdot C_S}}$$

(11)

Here, $f_c$ denotes the chopping frequency of the switches, and the output V_out is assumed to be at virtual ground. In this case, the combined effect of C_s and the chopper can be modeled using the Norton equivalent circuit shown in Figure 9.

According to Figure 8, the voltage at node D, V_D, can be expressed as follows:

$$V_D=I_{CS}\cdot Z_{CS}+(V_o-V_D)\cdot s\cdot C_{F1}\cdot Z_{CS}$$

(12)

By combining Equations (10) and (12), the transfer function H(s) of G_m and C_F1 can be obtained as:

$$H(s)={\displaystyle \frac{V_0}{I_{CS}}}=-{\displaystyle \frac{Z_{CS}{A}_0}{1+s{Z}_{CS}(1+A_0)C_{F1}}}$$

(13)

The loop gain L(s) of the ripple reduction loop (RRL) can be expressed as:

$$L(s)=K\cdot H(s)\cdot G_{m32}$$

(14)

By substituting Equations (13) and (9) into the above expression, we obtain:

$$L(s)={\displaystyle \frac{C_S}{C_1}}\cdot {\displaystyle \frac{Z_{CS}{A}_0}{1+s{Z}_{CS}{A}_0{C}_{F1}}}\cdot G_{m32}$$

(15)

Setting L(s) = 1, the gain-bandwidth product (GBW) of the filter can be obtained as:

$$f_0={\displaystyle \frac{G_{m32}{C}_S}{2\pi C_1{C}_{F1}}}$$

(16)

When the loop gain L(s) = L(0), we have:

$$L(0)=A_0{G}_{m32}\cdot {\displaystyle \frac{C_S}{C_1}}\cdot Z_{CS}={\displaystyle \frac{A_0{G}_{m32}}{C_1{f}_c}}$$

(17)

From all the above expressions, the formula for loop ripple suppression can be derived as:

$$V_{\mathit{out}\mathit{ripple},\mathrm{RRL}}={\displaystyle \frac{V_{\mathit{out},\mathit{ripple}}}{L(0)}}={\displaystyle \frac{V_{\mathit{os}}\cdot G_{m31}}{2A_0\cdot G_{m32}}}$$

(18)

This implies that, to achieve effective filtering and ripple suppression, both C_F1 and A₀ should be sufficiently large. In this design, G_m employs a high-gain transconductance amplifier.

3.5. SAR-Assisted Automatic Offset Voltage Calibration Loop Design

To further enhance overall system performance, an automatic offset calibration loop (AOCL) based on SAR logic is introduced in this work. As shown in Figure 9, the AOCL consists of a comparator, a 12-bit SAR logic block, and a 12-bit R-2R digital-to-analog converter (DAC). The AOCL can be activated for one-time calibration under zero-input conditions during power-up or manually triggered as needed. The 12-bit SAR logic generates DAC control signals using a binary search algorithm. The resulting 12-bit digital output controls the 12-bit R-2R DAC, which generates a compensation feedback voltage that can be applied to the differential common-mode level of the output.

Figure 9. Automatic offset calibration loop (AOCL).

Figure 9. Automatic offset calibration loop (AOCL).

The operating principle of the AOCL, shown in Figure 9, is as follows: During the calibration phase (as depicted in Figure 3), the CFIA’s differential input is shorted to the common-mode level, allowing the amplifier’s offset voltage to manifest at the output. This output voltage is then sensed by the comparator and fed back to the SAR logic controller. The controller iteratively adjusts the DAC’s compensation current bit by bit (as illustrated in Figure 10) until the offset is canceled.

To improve both calibration accuracy and hardware efficiency, the DAC in this work (as shown in Figure 11) adopts a hybrid architecture combining thermometer code and an R-2R structure. Specifically, the most significant bits (MSB, upper 4 bits) employ thermometer decoding for coarse adjustment, while the least significant bits (LSB, lower 8 bits) use a conventional R-2R ladder for fine adjustment. The output voltage of the DAC can be expressed as:

$$V_{\mathit{out}+}-V_{\mathit{out}-}=\left(1+2\cdot {\displaystyle \frac{R_2}{R_1}}\right)(V_{\mathit{in}+}-V_{\mathit{in}-})+{\displaystyle \frac{R_2}{R_{\mathit{DAC}}}}\left[(V_{\mathit{in}+}-V_{\mathit{in}-})-(V_{\mathit{DACout}+}-V_{\mathit{DACout}-})\right]$$

(19)

Here, R₁ and R₂ are the resistors in the CFIA feedback network, V_in is the differential input signal, and V_DACout is the differential output voltage of the DAC. The DAC output is routed through a 7/8 ratio resistor network to adjust the compensation current, thereby enabling precise offset voltage compensation.

Figure 11. Twelve-bit R-2R digital-to-analog converter (DAC).

Figure 11. Twelve-bit R-2R digital-to-analog converter (DAC).

The comparator in the AOCL (as shown in Figure 12) consists of two preamplifier stages for offset voltage reduction, followed by a positive feedback latch stage. The latch stage is reset when the CLK signal is high; when CLK transitions from high to low, the comparator operates. The differential outputs of the latch stage, V_out+ and V_out−, are stored by an SR latch to generate V_{COMP_OUT}. The operating frequency of the comparator is 4 kHz. Since the comparator senses the common-mode level at the CFIA output, the input-referred noise at this node is attenuated by the gain of the CFIA.

Figure 13 shows the SAR logic. The SAR logic block consists of two columns of 14 flip-flops. The first column acts as a shift register to receive data from the comparator. The second column takes data from the first column, updates the comparator output, and generates the control input for the DAC. Initially, the MSB of the DAC input is set high and the LSB is set low. When the comparator detects the common-mode voltage at the CFIA output, the result is updated to the MSB, and this process continues sequentially down to the LSB. When all bits have been processed, the end-of-conversion (EOC) signal goes high, indicating the completion of AOCL operation.

4. Discussion and Conclusions

Figure 14 shows the chip micrograph of the proposed 4–20 mA transmitter system. The circuit is implemented in a 0.18 μm 1P4M BCD process, and the transmitter chip size is 2.8 mm × 2.1 mm. The complete system operates over a supply voltage range of 5–36 V, while the proposed CFIA is powered by a 1.8 V LDO, consuming 182 μA. Figure 15 and Figure 16 and Figure 17 and Figure 18 show the magnitude and phase responses of the input-stage and intermediate transconductance amplifiers, respectively. The chopper frequency is set to 150 kHz. The DC gain of the CFIA is programable via a 2-bit decoder, with a gain range covering 30.10 dB to 48.16 dB, as illustrated in Figure 19. The gain-bandwidth product is 2.16 MHz. Figure 20 presents the post-layout simulated results for four gain settings, showing the CFIA amplifying an input signal of 1 mV amplitude, 0.9 V common-mode voltage, and 4 kHz frequency.

Figure 21 shows the equivalent input-referred noise of the CFIA across all process corners. At 1 kHz, the best input-referred noise is 13.79 nV/√Hz and the worst is 20.28 nV/√Hz. Figure 22 and Figure 23 present the simulated common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) across all process corners. The CMRR of the CFIA ranges from a best case of 170 dB to a worst case of 122 dB, while the PSRR ranges from 136 dB to 117 dB. Figure 24 shows the Monte Carlo simulation results for the input offset voltage of the CFIA, with all simulations covering all process corners and extreme values of temperature and supply voltage.

Figure 10 presents the calibration process of the automatic offset calibration loop (AOCL). The yellow, blue, green, and purple waveforms represent the 4 kHz AOCL clock, AOCL end-of-conversion (EOC) signal, the positive output (V_OUT+) of the CFIA, and the negative output (V_OUT−), respectively. When a differential offset of 100 mV is applied to the input (as shown in Figure 3), the AOCL operation calibrates the output offset to approximately 1 LSB. The calibration time of the AOCL is 3 ms.

A low-noise, chopper-stabilized current-feedback instrumentation amplifier (CFIA) is proposed for 4–20 mA transmitter systems to achieve high-precision signal acquisition from resistive sensors. For clarity, the detailed simulation data and the figures derived from them are included in the Supplementary Materials. The CFIA adopts a three-stage amplification architecture with a nested compensation scheme to ensure stability. The input stage provides a gain of 133.73 dB and a phase margin of 78.73°, while the subsequent two stages, which employ a push–pull output amplifier configuration, achieve a combined gain of 70.95 dB with a phase margin of 66.76°. To mitigate the input offset voltage caused by internal and external factors, an automatic offset calibration loop (AOCL) is integrated. Chopper modulation is utilized to suppress low-frequency flicker noise, and an embedded ripple reduction loop (RRL) significantly attenuates the ripple components introduced by the chopping process.

Table 1. Performance summary of proposed current-feedback instrumentation amplifier (CFIA) and comparison with other instrumentation amplifiers (IAs).

Parameter	This Work	[25]	[26]	[16]	[13]
Technology (μm)	0.18	0.18	0.18	0.18	0.5
Architecture	CFIA	CFIA	CBIA	CFIA	CFIA
DOC Techniques	CH+RRL	Multipath +RRL	CH +CMCP +HPF	CH + RRL	AZ + CH
fchop or faz (kHz)	150	-	4.1	20/200	-
Supply Voltage (V)	1.8	3.3	1.2	3.3	3–5.5
Current Consumption (μA)	182	169	20.7	200	1700
Gain Bandwidth (Hz)	2.16M	59.2 k	-	-	0.8M
Input Referred Noise (nV/√Hz@1 KHz)	20.28	28.3	87	23	27
CMRR (dB)	122	162	66	130	138
PSRR (dB)	117	112	-	-	142
Input Referred Offset (μV)	<1	-	-	5	2.8
Automatic Offset Calibration	Yes	No	No	No	No

compares the performance of the proposed solution with state-of-the-art designs. Fabricated using a 0.18 μm 1P4M BCD process, the system operates at a 1.8 V supply voltage with a static current consumption of 182 μA. Post-layout simulation results demonstrate that the CFIA achieves a common-mode rejection ratio (CMRR) of 122 dB, a power-supply rejection ratio (PSRR) of 117 dB, and a low input-referred noise of 20.28 nV/√Hz at 1 kHz. With its high precision and low power consumption, the proposed front end is well-suited for resistive sensor interfaces in industrial loop-powered applications.