A 0.3 V Current Differencing Buffered Amplifier and Its Application in Current-Mode Third-Order Low-Pass Filters

Abstract

This paper introduces an innovative low-voltage, low-power current differencing buffered amplifier (CDBA). The proposed CDBA utilizes a bulk-driven MOS transistor operating in the subthreshold region, allowing it to function effectively at low supply voltages while minimizing power consumption, making it suitable for sensor and biomedical applications. To demonstrate the performance of the proposed CDBA, it is incorporated into the design of a current-mode, third-order low-pass filter that is specifically tailored for bio-sensing applications. Both the CDBA and the low-pass filter are designed and simulated in Cadence Virtuoso using the TSMC 0.18 µm CMOS process. The CDBA operates at a supply voltage of 0.3 V, consuming 170 nW of power, while the third-order low-pass filter achieves a dynamic range of 57.2 dB with a total harmonic distortion (THD) of 1%.

1. Introduction

The current differencing buffered amplifier (CDBA) was first introduced in [1]. This device features a positive current input ($p$ terminal), a negative current input ($n$ terminal), and a current output ($z$ terminal). When an impedance is connected to the $z$ terminal, the voltage at this terminal becomes equal to the voltage at the $w$ terminal (the voltage output terminal). Therefore, this device offers advantageous features such as immunity to parasitic capacitance, wide bandwidth, and a high slew rate [2]. The CDBA has various applications, including universal filters [2,3,4,5,6,7], high-order filters [1,8,9,10,11,12,13], sinusoidal oscillators [14,15,16,17], inductance simulators [18,19,20,21,22], proportional–integral–derivative (PID) controllers [23], fractional-order multifunction filters [24,25], and meminductor emulators [26,27,28]. Clearly, the CDBA is a compelling active building block for implementing analog circuits. However, these applications typically require a high supply voltage and consume a significant amount of power because the CDBA structures used are not designed for low-voltage, low-power operations. Although several high-performance CDBA structures have been reported in the literature [29,30,31,32], they still suffer from the drawback of requiring high supply voltages. The CDBA in [7,12] operates with a ±1.25 V supply voltage, while the CDBA in [10,31] operates with a ±1 V supply voltage. The CDBA in [14] requires a ±2 V supply voltage, and the one in [18] operates at ±2.5 V. In [29], a ±0.6 V supply voltage is used, consuming 565.25 μW of power. Another CDBA in [30] operates with a 0.7 V supply voltage, whereas the CDBA in [32] functions with a ±0.8 V supply voltage.

Currently, energy efficiency is becoming an increasingly crucial parameter for analog systems, driven by the growing demand for portable applications. It is well known that the threshold voltage of MOS transistors is the main obstacle in designing analog circuits to operate with a low supply voltage. Fortunately, this obstacle can be overcome using the bulk-driven MOS transistor (MOST) technique. This technique allows analog circuits to operate with a supply voltage as low as 0.5 V, even when the threshold voltage is also 0.5 V [33,34,35]. To achieve low-power circuits, a well-known technique involves the operation of MOS transistors in weak inversion.

Low-pass filters can be applied to various systems, including telecommunications, control, and biomedical applications. They allow signals within a specific frequency range to pass while eliminating out-of-band noise. This work focuses on low-pass filters for applications in biomedical systems. Low-pass filters are widely used in biomedical applications, including electroencephalographic (EEG), electromyographic (EMG), and electrocardiographic (ECG) systems. Many low-pass filters suitable for these systems can be found in the literature; see, for example, [36,37,38,39,40,41,42,43]. The filters in [36,37,38,39,40,41] operate in voltage mode, whereas those in [42,43] operate in current mode. This work focuses on current-mode filters due to their wide dynamic range, ease of signal addition and subtraction, and low supply voltage requirements [44,45,46].

Therefore, this paper proposes a low-voltage, low-power current differencing buffered amplifier (CDBA). The bulk-driven MOST technique is employed to achieve low supply voltage, while the MOST operating in weak inversion is used to reduce the power consumption of the proposed CDBA. The proposed CDBA is designed in the Cadence Virtuoso environment using 0.18 µm CMOS technology from TSMC. It operates at a supply voltage of 0.3 V and consumes 170 nW of power, with a bias current set to 10 nA. The proposed CDBA has been applied to a fully current-mode third-order low-pass filter with a cut-off frequency of approximately 110 Hz. This cut-off frequency was chosen to meet typical requirements in biomedical signal processing applications, particularly for electrocardiogram (ECG) and electromyogram (EMG) signals, where most of the relevant frequency content lies below 150 Hz. For ECG signals, in particular, the majority of the signal energy is concentrated below 100–150 Hz. The selection of a 110 Hz cut-off frequency therefore provides a balance between preserving the desired signal bandwidth and attenuating high-frequency noise. The proposed filter achieves a dynamic range of 57.2 dB with a total harmonic distortion (THD) of 1%.

2. Circuit Description

2.1. Proposed 0.3 V CDBA

The electrical symbol of the CDBA is shown in Figure 1. Its operation in an ideal case is described by Equation (1). The circuit can be seen as a current differential amplifier with zero-impedance inputs $p$ and $n$ and infinite-impedance output $z$. The difference in currents flowing into the $p$ and $n$ terminals is conveyed to the $z$ terminal with a current gain equal to unity. In addition, there is an additional voltage buffer between the $z$ and $w$ terminals with a voltage gain equal to unity and a zero output impedance.

$$\left(\begin{array}{c}{I}_z\\ V_w\\ V_p\\ V_n\end{array}\right)=\left(\begin{array}{cccc}0& 0& 1& -1\\ 1& 0& 0& 0\\ 0& 0& 0& 0\\ 0& 0& 0& 0\end{array}\right)\left(\begin{array}{c}{V}_z\\ I_w\\ I_p\\ I_n\end{array}\right)$$

(1)

The CMOS structure of the CDBA proposed in this work is shown in Figure 2. The circuit consists of two identical non-inverting current conveyors (CCIIs), namely M1–M8 and M1c–M8c, as well as one voltage buffer M1b–M7b. The CCIIs were presented and verified experimentally in [47]. Their structure was developed from the ultra-low-voltage buffer (M1–M3, M5–M7) first proposed in [48], by adding a high-impedance output stage (M4 and M8), thus creating a $z$ output of the conveyor. The circuit exploits bulk-driven transistors that allow for avoiding the constraints associated with threshold voltages of MOS transistors, providing a rail-to-rail signal swing even at very low supply voltages. Considering the first conveyor M1-M8, we should note that the bulk terminal of M1 corresponds to its $Y$ input (grounded); the drain of M3 ($p$ terminal of CDBA) corresponds to the $X$ terminal; and the drain of M4 ($n$ terminal of CDBA) is its $z$ output. Thus, the current flowing into the terminal $n$ of the CDBA is subtracted from the current flowing into its $p$ terminal, and this difference is conveyed to the output $z$ of the CDBA. Between $z$ and $w$, we have a voltage buffer with an identical structure as the one used in current conveyors.

As already mentioned, the current conveyor structure consists of the $Y-X$ voltage buffer (M1–M3, M5–M7) and the output stage M4–M8. The voltage buffer [48] can be seen as a two-stage operational transconductance amplifier (OTA) operating in a voltage follower configuration. Transistors M1 and M2 form a simple non-tailed BD differential pair, biased by the current sinks M5 and M6. The input stage is followed by the second stage of OTA, consisting of the transistor M3 biased by the current sink M7. Due to the non-tailed architecture with BD transistors, the circuit can operate with a very low supply voltage of two saturation voltages of MOS transistors in weak inversion (ca. 200 mV), while offering a rail-to-rail voltage swing. An interesting feature of the proposed structure is its high voltage gain accuracy, despite the relatively low open-loop gain of the internal OTA [48]. This improves its frequency response and eliminates the need for additional compensation capacitors, even for load capacitances on the order of several picofarads. By doubling the output stage transistors, a CCII configuration can be achieved.

To obtain a CCII with a supply voltage of 0.3 V, i.e., about 60% of the threshold voltages in the used technology (0.5 V), the circuit was biased with very low currents of the order of nA. In addition, $V_{GS}$ voltages for all transistors were around mid supply, for the assumed channel lengths of 1 µm, which provides maximum headroom for the possible impact of the process, voltage and temperature (PVT) variations, and signal swing. The channel length of transistors is relatively large to increase their output resistances and consequently intrinsic voltage gains. The biasing current of the output stage is five times larger than the biasing current in each branch of the input differential amplifier, which decreases the output resistance and improves the stability margin of the internal OTA. All conveyors used in the design of the CDBA, with the additional voltage buffer, are identical and are identically biased. The current gain of both conveyors, which is equal to the current gains from the $p$ to $n$ and from the $n$ to $z$ terminals of the CDBA, as determined at shorted outputs, are given in the following equation:

$$A_i={\displaystyle \frac{g_{m\mathrm{3,4}}\frac{g_{mb1}}{g_{o1}}}{g_{m\mathrm{3,4}}\frac{g_{mb1}}{g_{o1}}+g_{o2}}}$$

(2)

In this expression, $g_{o1}=g_{ds1}+g_{ds5}$ and $g_{o2}=g_{ds3}+g_{ds7}$, where $g_m$, $g_{mb}$, and $g_{ds}$ denote the transconductance, bulk transconductance, and output conductance of the MOS transistor, respectively. Thus, the current gain error of the current mirror M3–M4 is reduced $g_{mb1}/g_{o1}$ times, compared to a simple MOS current mirror, i.e., by the number equal to the voltage gain of the input differential stage M1–M2.

Assuming $g_{m1}/g_{mb1}=g_{m2}/g_{mb2}$, the dc voltage gain of the voltage follower $z-w$, and other followers in the structure, can be expressed as follows [48]:

$$A_{vo}={\displaystyle \frac{\frac{g_{mb1}}{g_{o1}}·\frac{g_{m3}}{g_{o2}}·\frac{g_{m3}+g_{o2}}{g_{m3}+g_{mb3}+g_{o2}}}{1+\frac{g_{mb1}}{g_{o1}}·\frac{g_{m3}}{g_{o2}}·\frac{g_{m3}+g_{o2}}{g_{m3}+g_{mb3}+g_{o2}}}}$$

(3)

It should be noted that its gain error is lower than that calculated from the formula $A_o/(1+A_o)$, where $A_o$ is the open loop voltage gain of the internal OTA, and can easily be lowered much below 1%, even with open loop gain in the range of 30 dB, thus providing a very good accuracy in a simple structure. The above property is achieved thanks to the connection between the bulk and drain terminals of M₃, which provide equal $V_{BS}$ voltages for M₂ and M₃, improving accuracy, even if it lowers the voltage gain of the internal OTA.

The output resistance at the output of the voltage follower, which is equal to the resistances seen at the $p$, $n$, and $w$ terminals of the CDBA, is given as follows:

$$r_p=r_n=r_w\cong {\displaystyle \frac{1}{g_{m3}\frac{g_{mb1}}{g_{o1}}}}$$

(4)

Thus, it is a reciprocal of $g_{m3}$, which is multiplied by the voltage gain of the first stage. The output resistance at the $z$ terminal of the CDBA is given as follows:

$$r_z={\displaystyle \frac{1}{g_{ds4}+g_{ds8}}}$$

(5)

and its value is rather small, due to the lack of cascode connections in the output stage. The ratio of resistances is as follows:

$${\displaystyle \frac{r_{p,n,w}}{r_z}}\cong {\displaystyle \frac{g_{m\mathrm{3,4}}}{g_{ds4}+g_{ds8}}}·{\displaystyle \frac{g_{mb1}}{g_{o1}}}$$

(6)

This is, however, of the order of 10³ Ω/Ω, which is sufficient for the proposed application. The 3 dB bandwidth of the voltage follower is approximately equal to its gain-bandwidth product ($GBW$), which can be approximated as follows:

$$GBW\approx {\displaystyle \frac{g_{mb1}}{C_{gd3}}}$$

(7)

This is typically much lower than the 3 dB frequency of the current gains of the conveyors and the CDBA. It is worth pointing out that the parasitic pole associated with the drain/gate node of M₂ and equal to $g_{m2}/C_{\sum }$, where $C_{\sum }$ is the total parasitic capacitance associated with this node, should be located much above the GBW of the voltage follower.

The minimum supply voltage of the CDBA is given by $V_{DDmin}=\mathrm{m}\mathrm{a}\mathrm{x}(V_{SG2}+V_{SDsat6}; V_{SG\mathrm{3,4}}+V_{SDsat5})$, where $V_{SDsat}$ is the saturation voltage of an MOS transistor. Assuming that $V_{SG\mathrm{2,3},4} \approx { V}_{DSsat}$, which holds in the weak inversion region, the minimum $V_{DDmin}$ can be as low as $2V_{SDsat}$ (ca. 200 mV) [47].

2.2. Proposed Filter

Figure 3a illustrates the doubly terminated third-order LC ladder low-pass filter, where $R_s$ and $R_L$ are connected to the input and output terminals, respectively. Figure 3b presents the signal flow graph of the LC ladder low-pass filter, corresponding to the topology in Figure 3a. It can be achieved using the voltage and current relationships (KCL routine analysis) from Figure 3a, as follows:

$$I_1=I_{in}-{\displaystyle \frac{V_1}{R_s}}-I_2$$

(8)

$$V_1={\displaystyle \frac{I_1}{{sC}_1}}$$

(9)

$$I_2={\displaystyle \frac{V_1-V_3}{s{L}_1}}={\displaystyle \frac{V_2}{s{L}_1}}$$

(10)

$$V_3={\displaystyle \frac{I_2-I_{RL}}{{sC}_2}}$$

(11)

$$I_3=I_2-I_{RL}$$

(12)

where $I_{RL}$ = $I_{out}$ and $V_3$ = $V_{out}$.

The proposed fully current-mode third-order low-pass filter is shown in Figure 4. CDBA1, $R_s$, $C_1$, and $R$ function as the first lossy integrator, while CDBA3, $R_L$, $C_2$, and $R$ serve as the second lossy integrator. Additionally, CDBA2, $C_{L1}$, and $R$ act as a gyrator for implementing inductor $L_1$. The inductor $L_1$ can be designed according to the expression $L_1=C_{L1}{R}^2$. Finally, the CDBA4 is employed to sense the output current flowing through the load resistor $R_L$, while maintaining a high output impedance, which is essential for current-mode circuit applications.

3. Results

The proposed CDBA structure and filter application were designed using the Cadence Virtuoso environment, utilizing 0.18 µm CMOS technology from TSMC. The CDBA is capable of operating with a supply voltage of 0.3 V while consuming only 170 nW of power for biasing current $I_B$ = 10 nA. The transistor dimensions in µm/µm are shown in

Table 1. The transistor dimensions of the proposed CDBA.

Component	W/L (µm/µm)
M1, M2, MB, M1c, M2c, M1b, M2b	50/1
M3, M4, M3c, M4c, M3b	5 × 50/1
M5, M6, M5c, M6c, M5b, M6b	100/1
M7, M8, M7c, M8c, M7b	5 × 100/1

.

Figure 5 shows the DC current characteristics of the CDBA (a) $I_z$ versus $I_p$ (with $I_n$ = 0) and (b) $I_z$ versus $I_n$ (with $I_p$ = 0) with a grounded $z$-terminal. As shown, the current operating range extends up to ±100 nA. With the $w$-terminal loaded with a $C_L$ = 5pF capacitance, the DC voltage characteristic $V_w$ versus $V_z$ is shown in Figure 6. The circuit offers a wide operating range of up to ±120 mV.

Figure 7 shows the frequency magnitude characteristics of the CDBA—$V_w/V_z$ (with $C_L$ = 5pF), $I_z/I_p$ (with $I_n$ = 0), and $I_z/I_n$ (with $I_p$ = 0). The voltage gain $V_w/V_z$ at low frequencies was 0.996 at the −3 dB bandwidth of 35 kHz. For the current gains, $I_z/I_p$ and $I_z/I_n$, the values were 0.998 and 0.997, with bandwidths of 79.4 kHz and 100 kHz, respectively.

The performance data of the proposed CDBA are shown in Table 2. The current and voltage offsets represent the standard deviation values obtained from a Monte Carlo analysis (including process and mismatch variations) with 200 simulation runs. Table 3 provides a comparative analysis of the proposed CDBA against previously reported designs, including earlier works [12,29,31] and recent publications [49]. This comparison demonstrates the proposed CDBA’s superior performance in terms of lower supply voltage and significantly reduced power consumption. Notably, a comprehensive literature survey confirms that no existing CDBA achieves sub-volt operation with nanowatt-range power consumption. Consequently, the proposed CDBA is ideally suited for low-voltage, low-power current-mode signal processing, particularly in biomedical applications.

For the proposed filter, the component values of the LC ladder low-pass filter in Figure 3a are given by the following: $R_s$ = $R_L$ = 440 kΩ, $C_1$ = $C_3$ = 3 nF, and $L_1$ = 1.161 kH. The component values of the proposed low-pass filter in Figure 4 are as follows: $R$ = 440 kΩ, $R_s$ = $R_L$ = 520 kΩ, $C_1$ = $C_3$ = 3 nF, and $C_{L1}$ = 6nF.

Figure 8 shows the frequency magnitude and phase characteristics of the low-pass filter (LPF). The magnitude at 1 Hz and the −3 dB cut-off frequency for the RLC and LPF were −6.02 dB and −6.21 dB, and 105 Hz and 110 Hz, respectively.

The tuning capability of the filter is demonstrated by adjusting the ${C=C}_1=$ $C_3{=2C}_{L1}$ for values of $C$ = 1.5, 3, and 6 nF. The corresponding cut-off frequency was 55 Hz, 110 Hz, and 229 Hz, as shown in Figure 9.

Table 2. Performance data of the proposed CDBA.

Parameters	Value
Supply voltage	0.3 V
Bias current $I_B$	10 nA
Technology	0.18 μm
DC current swings: $I_p$$, I_n$	±100 nA
Current gains: $I_z/I_p$$, I_z/I_n$	0.997, 0.998
Current offset $I_z$$(I_p$$=I_n$= 0)	1.35 nA
–3 dB bandwidth: $I_z/I_p$$, I_z/I_n$	[79.4, 100] kHz
DC voltage swings: $V_w$	±120 mV
Voltage gain: $V_w/V_z$	0.996
Voltage offset $V_w$$(V_z$= 0)	2.4 mV
–3 dB bandwidth:$V_w/V_z$$(C_L$= 5pF)	35 kHz
$z_p$$, z_n$$, z_w$	17 kΩ
$z_z$	24.5 MΩ
Power dissipation	170 nW

Table 2. Performance data of the proposed CDBA.

Parameters	Value
Supply voltage	0.3 V
Bias current $I_B$	10 nA
Technology	0.18 μm
DC current swings: $I_p$$, I_n$	±100 nA
Current gains: $I_z/I_p$$, I_z/I_n$	0.997, 0.998
Current offset $I_z$$(I_p$$=I_n$= 0)	1.35 nA
–3 dB bandwidth: $I_z/I_p$$, I_z/I_n$	[79.4, 100] kHz
DC voltage swings: $V_w$	±120 mV
Voltage gain: $V_w/V_z$	0.996
Voltage offset $V_w$$(V_z$= 0)	2.4 mV
–3 dB bandwidth:$V_w/V_z$$(C_L$= 5pF)	35 kHz
$z_p$$, z_n$$, z_w$	17 kΩ
$z_z$	24.5 MΩ
Power dissipation	170 nW

Table 3. Comparison between the proposed CDBA and previous works.

Factor	Unit	Proposed	[12] 2006	[29] 2010	[31] 2014	[49] 2024
Technology	µm	0.18	0.5	0.18	0.18	0.045
Voltage supply	V	0.3	±1.25	±0.6	±1	±0.6
Power consumption	nW	170	0.93 × 106	565.25 × 103	1.58 × 106	271.9 × 103
Current gains: $I_z/I_p,I_z/I_n$	-	0.997, 0.998	0.991, 0.996	0.981, 0.981	1.015, 1.015	0.75, 0.75
Voltage gain: $V_w/V_z$	-	0.996	0.989	0.978	0.995	0.941
DC current swing: $I_p$$, I_n$	nA	±100	~±30 × 103	~±50 × 103	±50 × 103	-
DC offset $I_z$	nA	1.35 *	0.49 × 106	0.05 × 106	-	4.6
DC voltage swing: $V_w$	mV	±120	~±75	~±75	±215	~±180
−3 dB bandwidth: $I_z/I_p,I_z/I_n$	kHz	79.4, 100	580 × 103, 643 × 103	25 × 103, 25 × 103	238.84 × 103, 174.65 × 103	20 × 103, 20 × 103
−3 dB bandwidth: $V_w/V_z$	kHz	$35 (C_L=$5pF)	570 × 103	474 × 103	243.43 × 103	657.8 × 103
$Z_p$	kΩ	17	14	56.4	263.77	-
$Z_n$	kΩ	17	14	56.4	161.15	-
$Z_w$	kΩ	17	14	270	214.67	-
$Z_z$	MΩ	21.5	0.29	0.157	0.242	-
Achieved result	-	Sim.	Sim.	Sim.	Post-Layout Sim.	Sim.

* Standard deviation.

Table 3. Comparison between the proposed CDBA and previous works.

Factor	Unit	Proposed	[12] 2006	[29] 2010	[31] 2014	[49] 2024
Technology	µm	0.18	0.5	0.18	0.18	0.045
Voltage supply	V	0.3	±1.25	±0.6	±1	±0.6
Power consumption	nW	170	0.93 × 106	565.25 × 103	1.58 × 106	271.9 × 103
Current gains: $I_z/I_p,I_z/I_n$	-	0.997, 0.998	0.991, 0.996	0.981, 0.981	1.015, 1.015	0.75, 0.75
Voltage gain: $V_w/V_z$	-	0.996	0.989	0.978	0.995	0.941
DC current swing: $I_p$$, I_n$	nA	±100	~±30 × 103	~±50 × 103	±50 × 103	-
DC offset $I_z$	nA	1.35 *	0.49 × 106	0.05 × 106	-	4.6
DC voltage swing: $V_w$	mV	±120	~±75	~±75	±215	~±180
−3 dB bandwidth: $I_z/I_p,I_z/I_n$	kHz	79.4, 100	580 × 103, 643 × 103	25 × 103, 25 × 103	238.84 × 103, 174.65 × 103	20 × 103, 20 × 103
−3 dB bandwidth: $V_w/V_z$	kHz	$35 (C_L=$5pF)	570 × 103	474 × 103	243.43 × 103	657.8 × 103
$Z_p$	kΩ	17	14	56.4	263.77	-
$Z_n$	kΩ	17	14	56.4	161.15	-
$Z_w$	kΩ	17	14	270	214.67	-
$Z_z$	MΩ	21.5	0.29	0.157	0.242	-
Achieved result	-	Sim.	Sim.	Sim.	Post-Layout Sim.	Sim.

* Standard deviation.

Figure 8. Frequency magnitude and phase characteristics of the LPF.

Figure 8. Frequency magnitude and phase characteristics of the LPF.

Figure 9. Frequency magnitude and phase characteristics of the LPF with various $C$.

Figure 9. Frequency magnitude and phase characteristics of the LPF with various $C$.

Figure 10 presents the frequency magnitude characteristics of the low-pass filter (LPF) under four different conditions—(a) process corners, (b) voltage supply variations, (c) temperature fluctuations, and (d) Monte Carlo (MC) analysis. The process variations considered for the MOS transistors include fast–fast, fast–slow, slow–fast, and slow–slow corners. Additionally, the supply voltage was varied by ±10% around the nominal value, and the temperature was tested at −10 °C and 60 °C. In the Monte Carlo analysis, which includes process variations and mismatch, 200 simulation runs were performed. The resulting curves, as depicted in the figure, either overlap or remain closely aligned, confirming the filter′s robustness under diverse process, voltage, temperature (PVT), and MC conditions.

Figure 11a shows the transient response of the filter with different applied sine wave signals of 1, 2, 4, and 8 nA applied to the input, with a 10 Hz amplitude. The total harmonic distortion (THD) of the output signal was around 0.68%. The THD for the filter is shown up to an 80 nA input signal, where the THD of the output signal reaches 1%, as shown in Figure 11b.

The equivalent output current noise of the filter is shown in Figure 12. The integrated noise over the frequency range of 0.1–110 Hz was calculated to be 68 pA. The dynamic range for 1% THD was calculated to be 57.2 dB.

The performance of the low-pass filter in filtering ECG signals was evaluated by introducing noise into a clean ECG signal. A 3 nA noise at 400 Hz was added to the ECG, creating a noisy signal that was then passed through the LP filter. The unfiltered noisy ECG signal is shown in Figure 13a. After filtering, the output, which shows the ECG with reduced noise, is presented in Figure 13b. This demonstrates the filter’s ability to effectively suppress high-frequency noise while preserving the essential features of the ECG signal.

4. Conclusions

This paper has presented a novel CMOS architecture for a low-voltage, low-power CDBA, implemented using bulk-driven MOS transistors operating in the subthreshold region. This design strategy enables efficient functionality at ultra-low supply voltages while minimizing power consumption. The proposed CDBA was demonstrated through the design of a current-mode third-order low-pass filter, which was specifically tailored for bio-sensing applications. The CDBA operates with a 0.3 V supply and consumes only 170 nW of power, confirming its potential for low-power analog signal processing in energy-constrained environments. The filter achieves a dynamic range of 57.2 dB, which is adequate for ECG signal processing, while consuming approximately 680 nW of power.