Interleaved Modified SEPIC Converters with Soft Switching and High Power Factor for LED Lighting Appliance

Abstract

A novel ac/dc LED driver with power factor correction and soft-switching functions is proposed. The circuit topology mainly consists of two modified single-ended primary inductance converters (SEPIC) with interleaved operation. The first half stage of SEPIC operates like a boost converter and the second half stage operates like a buck–boost converter. Each boost converter is designed to operate in discontinuous current mode (DCM) to function as a power factor corrector (PFC). The two buck–boost converters that share a commonly coupled inductor are designed to operate at near boundary conduction mode (BCM). Without using any active clamping circuit, auxiliary switch or snubber circuit, the active switches can achieve zero-voltage switching on, and all diodes achieve zero-current switching off. First, operation modes in steady state are analyzed, and the mathematical equations for design component parameters are derived. Finally, a prototype circuit of 180 W rated power was built and tested. Experimental results show satisfactory performance of the proposed circuit.

1. Introduction

A light-emitting diode (LED) has the advantages of small size, high energy efficiency, long service life, fast response time, good color rendering, environmental friendliness, etc. Nowadays, LEDs have gradually replaced fluorescent lamps and high-intensity gas discharge lamps, and have been widely used in various lighting systems [1,2,3,4].

When the input voltage is an ac line voltage source, a large capacitor filter needs to be installed after the rectifier circuit to reduce the ripple of the rectified dc voltage. Since the diode of the rectifier circuit only conducts when the ac voltage is higher than the dc voltage. The conduction time is very short, and the input current is a large pulse inrush current. This results in a low power factor and high total harmonic distortion of current (THDi) [5]. High-order harmonic currents can interfere with control circuits or communication systems and cause malfunctions in measuring instruments and electrical protection equipment. Therefore, advanced countries have formulated strict specifications, such as IEC 61000-3-2 [6] and IEEE 519 [7] to regulate the power factor and THDi of electrical products [8,9]. In order to meet the specifications of power factor and THDi, a power factor corrector (PFC) should be added in front of the original ac/dc converter, so that the LED drivers have a two-stage circuit architecture [10,11]. In order to improve the shortcomings of using more components in a two-stage converter and to reduce the number of energy transfer times in the converter and thereby improve the circuit efficiency, researchers have developed a number of single-stage LED drivers in which the active switches and control circuit are shared by a PFC converter and a dc/dc converter [12,13,14,15,16,17]. However, in order to serve as switches for both the PFC converter and the DC/DC converter, some shared switches operate in hard switching.

Hard switching means that the switch cannot operate at zero-voltage switching on (ZVS) or zero-current switching off (ZCS). For active switches, if they cannot operate at ZVS, their parasitic capacitance will generate huge spike currents due to an instant short circuit when they are turned on, and the energy originally stored in the parasitic capacitance will be dissipated inside the switches. For diodes, if they cannot operate at ZCS, a reverse recovery current will be generated when the diodes are turned off. In other words, in addition to huge switching losses, hard switching is also accompanied by high current and high voltage stress. Therefore, hard switching circuits must use switches with high voltage/current specifications to reduce their failure rate. Without the use of higher specification components, the LED drivers with hard switching can only be used in low-power products. The literature [18,19,20] proposed LED drivers with single-stage topologies. Although they can achieve a high power factor, their energy conversion efficiency is not high because the active switches cannot meet ZVS operation, so they are only suitable for low-power products (9–50 W). In order to solve the hard-switching problem, pulse–width modulation (PWM) converters usually use active clamping or snubber circuits to implement ZVS and/or ZCS [21,22,23,24]. However, these soft-switching techniques require the use of additional auxiliary switches, diodes, inductors, and capacitors, which increases circuit costs. In addition, current loops in active clamping or snubber circuits generate additional conduction losses, thereby reducing circuit efficiency. In the literature [25,26,27,28], a single-stage topology is obtained by integrating a PWM converter and a resonant converter, where the PWM converter is used as the PFC circuit and the full-bridge or half-bridge resonant converter is used as the DC/DC converter. The resonant converter not only has the advantage of galvanic isolation. By designing the switching frequency to be greater than the resonant frequency of the resonant tank, the resonant tank will present an inductive load, and the active switches can operate at ZVS. However, the resonant converter requires additional rectifier and filter circuits to obtain a smooth DC output voltage, which not only increases the component count but also causes more conduction losses.

This paper proposes an ac/dc converter to drive high-power LEDs, which is obtained by modifying two single-ended primary inductance converters (SEPIC) with interleaved operation. The proposed circuit achieves a high power factor and low THDi and the switch meets soft switching. The other content of this paper is organized as follows. Section 2 proposes the circuit topology and analyzes the steady-state operation mode in detail; Section 3 deduces the mathematical equations for designing circuit component parameters; Section 4 designs, manufactures and experimentally measures the 180 W prototype circuit. Finally, some conclusions are made in Section 5.

2. Proposed LED Driver and Analysis of Steady-State Operation

2.1. Circuit Topology

Figure 1 shows the circuit topology of the high-power factor ac/dc LED driver proposed in this paper. The circuit consists of a low-pass filter (L_f, C_f), a bridge rectifier (D_r1–D_r4), and two modified SEPIC circuits. One SEPIC circuit includes inductor L_p1, diode D₁, active switch S₁, dc-link capacitor C_B1, flywheel diode D₃ and the primary winding of the coupled inductor T₁, and the other includes inductor L_p2, diode D₂, active switch S₂, dc-link capacitor C_B2, flywheel diode D₄ and secondary winding of T₁. Diodes D_S1 and D_S2 are the intrinsic body diodes of S₁ and S₂, respectively. Figure 2 shows the control voltages (v_GS1, v_GS2) of S₁ and S₂. They are both square wave voltages with a phase difference of 180 degrees and partially overlap, i.e., both S₁ and S₂ are in conduction for a certain period of time.

Typically, a SEPIC circuit is a single-stage topology using only one active switch. The first half stage of the SEPIC circuit operates like a boost converter and the second half operates like a buck–boost converter. Compared with the traditional two parallel SEPIC circuits, the circuit proposed in this paper has two differences. The first is the addition of two diodes (D₁, D₂) to avoid the currents in L_p1 and L_p2 flowing in the opposite direction. If i_p1 and i_p2 have reverse currents, the power factor correction performance will be impaired, and some excess conduction loss will occur. The second point is to use a coupled inductor T₁ instead of two separate inductors for the second half stage of the two SEPIC circuits. T₁ consists of an iron core and two windings with the same number of turns. Unlike traditional SEPIC circuits, which require additional components to enable ZVS operation for active switches. The winding current of the coupled inductor is designed to operate close to the boundary conduction mode (BCM). Based on the principle of magnetomotive force balance, the mutual inductance current will be converted between the two windings and the winding current is used to discharge the store charges in the parasitic capacitance of the active switch to fulfill ZVS operation.

2.2. Analysis of Operation Mode

The following assumptions are made to simplify the circuit analysis.

(1)

In order to ensure ZCS operation for all diodes, the currents of L_p1 and L_p2 are designed to operate in discontinuous-current mode (DCM), and the winding currents of T₁ are all designed to decrease to zero amps.

(2)

All components are considered ideal except for the parasitic capacitance (C_S1 and C_S2) and intrinsic diodes (D_S1 and D_S2) of the S₁ and S₂.

(3)

The two SCPIC circuits are identical with L_p1 = L_p2 = L_p, C_B1 = C_B2 = C_B, V_B1 = V_B2 = V_B.

(4)

Capacitors C_B1, C_B2, and C_o are large enough that the voltages across them (V_B1, V_B2, and V_O) can be regarded as constant.

(5)

The winding resistance and iron loss of T₁ are neglected. The leakage inductance in the primary and secondary windings are equal (L_l1 = L_l2 = L_l), and the mutual inductance L_m is large enough so that the mutual inductance current is regarded as a constant I_Lm.

(6)

S₁ and S₂ are turned on and off at a high frequency (f_s) well above the input line frequency (f_L). Therefore, the rectified input voltage can be regarded as a constant value in each high-frequency cycle.

In steady-state operation, the circuit can be divided into 10 operation modes in each high-frequency cycle according to the status of each component. Figure 3 shows the equivalent circuits for each operation mode, where v_rec denotes the voltage after the bridge rectification and R_o denotes the equivalent resistance of the LEDs. In Figure 3, T₁ is represented by a transformer model, where L_l1 and L_l2 are leakage inductances and v_T is the voltage across the mutual inductance. For a coupled inductor, the following equation can be derived [29].

$${\mathrm{i}}_{Ll1}+{\mathrm{i}}_{Ll2}={\mathrm{i}}_{Lm},$$

(1)

$$v_T={\displaystyle \frac{L_{m}d{i}_{Lm}}{dt}},$$

(2)

Applying Faraday’s law to the leakage inductances gives

$$v_{Ll1}+v_{Ll2}={\displaystyle \frac{L_{l1}d{i}_{Ll1}}{dt}}+{\displaystyle \frac{L_{l2}d{i}_{Ll2}}{dt}}={\displaystyle \frac{L_{l}d{i}_{Lm}}{dt}},$$

(3)

Figure 4 shows the schematic waveforms of voltage and current of the main components. The following section describes the details of each operation mode and the derivation of the associated equations.

Before operation Mode 1, both S₁ and S₂ are on. Since S₂ is turned on before S₁, most of the mutual inductance current i_Lm flows in the secondary winding of T₁ through S₂, that is, i_Ll2 >> i_Ll1. When v_GS2 changes from high level to low level, S₂ is turned off and the circuit enters operation Mode 1.

2.2.1. Operation Mode 1 (t₀ < t < t₁)

At the moment before S₂ is turned off, i_p2 reaches a peak value, denoted as i_p2,peak. When S₂ is turned off, i_p2 flows through D₂ to charge C_S2, and i_Ll2 also flows into C_B2 to charge C_S2. In practice, the parasitic capacitance is very small. C_S2 will be quickly charged to V_B + V_o. After that, i_p2 will flow through D₂, C_B2, D₄, and C_o, while i_Ll2 will flow through D₄ and C_o, as shown in Figure 3a. The voltages and current equations for L_p1 and L_p2 are as follows.

$$v_{p1}\left(t\right)=v_{rec},$$

(4)

$$i_{p1}\left(t\right)=i_{p1}\left(t_0\right)+{\displaystyle \frac{v_{rec}}{L_p}}\left(t-t_0\right),$$

(5)

$$v_{p2}\left(t\right)=-V_B-V_o+v_{rec},$$

(6)

$$i_{p2}\left(t\right)=i_{p2,peak}-{\displaystyle \frac{\left(V_B+V_o-v_{rec}\right)}{L_p}}\left(t-t_0\right),$$

(7)

The current i_p1 keeps increasing linearly while i_p2 starts to decrease linearly.

From Figure 3a, the voltage equations of the primary and secondary windings of T₁ are expressed as (8) and (9), respectively.

$$v_{Ll1}+v_T=V_B,$$

(8)

$$v_{Ll2}+v_T+V_o=0,$$

(9)

Adding (8) and (9) gives

$$v_{Ll1}+v_{Ll2}+2v_T=V_B-V_o,$$

(10)

Substituting (2) and (3) into (10) yields

$$v_T={\displaystyle \frac{L_m}{L_l+2L_m}}\left(V_B-V_o\right),$$

(11)

Substituting (11) into (8) and (9), respectively, the leakage inductance voltages can be expressed as follows.

$$v_{Ll1}={\displaystyle \frac{\left(L_m+L_l\right)V_B+L_m{V}_o}{L_l+2L_m}},$$

(12)

$$v_{Ll2}={\displaystyle \frac{-L_m{V}_B-\left(L_m+L_l\right)V_o}{L_l+2L_m}},$$

(13)

Equation (12) shows that v_Ll1 is positive, so i_Ll1 starts to rise from a negative value close to zero. After a period of time, i_Ll1 rises to become positive. Equation (13) shows that v_Ll2 is negative, and i_Ll2 starts to decrease from the peak value. In other words, when S₂ is turned off, i_Ll2 decreases and i_Ll1 increases, that is, the current originally flowing through the secondary winding of T₁ gradually converts to flow through the primary winding.

The boost converters would be designed to operate in DCM. When i_p2 declines to zero, D₂ turns off and the circuit enters the next operation mode.

2.2.2. Operation Mode 2 (t₁ < t < t₂)

In this mode, the equivalent circuit is shown in Figure 3b. The current i_p2 remains zero. Equations (4), (5), and (8)–(13) remain unchanged. Therefore, i_p1 and i_Ll1 continue to rise, and i_Ll2 continues to fall. When i_Ll2 decreases to zero, D₄ turns off and the circuit enters the next operation mode.

2.2.3. Operation Mode 3 (t₂ < t < t₃)

In this mode, i_p2 remains zero while i_p1 keeps increasing. This mode is the process of discharging C_S2 from high voltage to zero volts. As shown in Figure 3c, v_Ll1 and v_Ll2 can be expressed as follows.

$$v_{Ll1}=V_B-v_T,$$

(14)

$$v_{Ll2}=V_B-v_T-v_{DS2},$$

(15)

Adding (14) and (15) gives

$$v_{Ll1}+v_{Ll2}=2V_B-2v_T-v_{DS2},$$

(16)

Substituting (2) and (3) into (16) yields

$$v_T={\displaystyle \frac{L_m}{L_l+2L_m}}\left(2V_B-v_{DS2}\right),$$

(17)

Substituting (17) into (14) and (15) respectively, v_Ll1 and v_Ll2 can be expressed as follows.

$$v_{Ll1}={\displaystyle \frac{L_l{V}_B+L_m{v}_{DS2}}{L_l+2L_m}},$$

(18)

$$v_{Ll2}={\displaystyle \frac{L_l{V}_B-\left(L_m+L_l\right)v_{DS2}}{L_l+2L_m}},$$

(19)

At the beginning of this mode, v_DS2 is equal to V_B + V_o, (18) and (19) show that v_Ll1 is positive, and v_Ll2 is negative. The current i_Ll1 keeps on rising. On the contrary, i_Ll2 continues to decrease and becomes negative, i.e., the secondary winding current is reversed, and at this time, T₁ acts as a transformer. During the discharge of C_S2, v_DS2 decreases. Observing (17)–(19), it can be known that v_T and v_Ll2 increase, and v_Ll1 decreases. When C_S2 discharges to zero volts, D_S2 turns on and the circuit enters operation Mode 4.

2.2.4. Operation Mode 4 (t₃ < t < t₄)

Figure 3d shows the equivalent circuit of operation Mode 4. The voltage and current equations of L_p2 are

$$v_{p2}\left(t\right)=v_{rec},$$

(20)

$$i_{p2}\left(t\right)={\displaystyle \frac{v_{rec}}{L_p}}\left(t-t_3\right),$$

(21)

The current i_p2 starts to rise from zero. The voltage equations of the primary and secondary windings of T₁ are

$$v_{Ll1}+v_T=V_B,$$

(22)

$$v_{Ll2}+v_T=V_B,$$

(23)

Adding (22) and (23) gives

$$v_{Ll1}+v_{Ll2}+2v_T=2V_B,$$

(24)

Substituting (2) and (3) into (24) yields

$$v_T={\displaystyle \frac{2L_m}{L_l+2L_m}}{V}_B,$$

(25)

Substituting (25) into (22) and (23), respectively, v_Ll1 and v_Ll2 can be expressed as follows.

$$v_{Ll1}=v_{Ll2}={\displaystyle \frac{L_l}{L_l+2L_m}}{V}_B,$$

(26)

Equations (25) and (26) show that v_T is positive, and v_Ll1 and v_Ll2 are also positive and equal, therefore, i_Lm, i_Ll1 and i_Ll2 all rise. Because L_m is much larger than L_l, (26) shows that v_Ll1 and v_Ll2 are very small, therefore, i_Ll1 and i_Ll2 rise slowly.

Observing Figure 3d, it can be noticed that i_Ll2 has two current paths, one is C_B2–T₁ secondary winding–D_S2, and the other is C_B2–T₁ secondary winding–v_rec–L_p2–D₂. Before i_Ll2 rises from negative to zero, v_GS2 changes from low level to high level. Because i_Ll2 is negative, its absolute value becomes smaller during the rise process. At first, the absolute value of is i_Ll2 larger than i_p2. When i_p2 rises to become larger than the absolute value of i_Ll2, S₂ would be turned on and the circuit enters operation Mode 5.

2.2.5. Operation Mode 5 (t₄ < t < t₅)

Figure 3e shows the equivalent circuit of this mode. Because D_S2 is in the on-state before S₂ is turned on, it clamps v_DS2 at zero volts, therefore S₂ satisfies ZVS. In this mode, i_p2 has two current loops, which are L_p2–D₂–C_B2–T₁ secondary winding–v_rec, and L_p2–D₂–S₂–v_rec. D_S2 is on when the circuit is operating in mode 4 and S₂ is on when the circuit is operating in mode 5. Whether D_S2 is on or S₂ is on, v_DS2 is equal to zero volts, so the voltage and current equations for Mode 5 are identical to Mode 4. Hence, i_p1 and i_p2 all continue to rise. When v_GS1 changes from high level to low level, S₁ is turned off and the circuit enters operation Mode 6.

2.2.6. Operation Mode 6 (t₅ < t < t₆) ~ Operation Mode 10 (t₉ < t < t₁₀)

Figure 3f–j show the equivalent circuits of Mode 6 to Mode 10. The circuit operation principles of Mode 6 to Mode 10 are similar to those of Mode 1 to Mode 5 and will not be described again here. When v_GS2 changes from high level to low level, S₂ is turned off, and the circuit enters the next high-frequency cycle of operation Mode 1.

3. Mathematical Equations for Parameters Design

3.1. Boost-Typed PFC Converter

From the analysis of the operation mode, it can be known that the voltage across L_p1 (L_p2) is equal to v_rec when S₁ (S₂) is on. On the contrary, when S₁ (S₂) is turned off, L_p1 (L_p2) transfers the stored energy to C_B1 (C_B2) and C_o. L_p1 (L_p2) is served as the inductor of a boost converter. In order for the boost converter to operate in DCM throughout the input voltage cycle, V_B +V_o must be high enough to satisfy the following equation.

$$V_{\mathit{B}}+V_o\ge {\displaystyle \frac{V_m}{1-D}},$$

(27)

First, k is defined as

$$k\triangleq V_B+V_o/V_m,$$

(28)

When the value of k is greater than 2, the power factor can reach more than 0.98 and the output power can be expressed as [30]

$$P_o={\displaystyle \frac{\eta D^2{V}_m^2}{L_p{f}_s}}\cdot y,$$

(29)

where η represents the circuit efficiency and y is expressed as

$$y={\displaystyle {\int }_0^{\pi }\frac{{\mathit{sin}}^2\theta }{1-\frac{1}{k}\mathit{sin}\theta } d\theta }={\displaystyle \frac{k^3}{\sqrt{k^2-1}}}\left(1+{\displaystyle \frac{2}{\pi }}{\mathit{sin}}^{-1}{\displaystyle \frac{1}{k}}\right)-k^2-{\displaystyle \frac{2}{\pi }}\cdot k,$$

(30)

3.2. Buck–Boost Converter

Based on the previous assumptions, i_Lm can be regarded as a constant value I_Lm when L_m is sufficiently large. During Mode 1 and Mode 2, i_Ll1 rises and i_Ll2 decreases, and it is known that the increase in i_Ll1 is equal to the decrease in i_Ll2 by (1). Mode 3 describes the process in which the parasitic capacitance of S₂ is discharged from V_B + V_o to zero volts. Because C_S2 is very small and the drop in i_Ll2 is also very small, therefore, at the end of Mode 3, i_Ll2 is negative but almost equal to zero. Thus, it is known that the peaks of i_Ll1 and i_Ll2 are very close to I_Lm.

$$i_{Ll1,peak}=i_{Ll2,peak}\approx I_{Lm},$$

(31)

Operation Mode 2 ends when i_Ll2 decreases to zero. Using (13) and (31), the time required for i_Ll2 to decrease from the peak value to zero is equal to

$$t_f=t_2-t_0\approx {\displaystyle \frac{I_{Lm}{L}_l\left(L_l+2L_m\right)}{L_m{V}_B+\left(L_m+L_l\right)V_o}},$$

(32)

During the period from Mode 1 to Mode 2, v_T is negative and i_Lm decreases. On the contrary, during the period from Mode 3 to Mode 5, v_T is positive and i_Lm increases. Applying the volt–second balance law of inductance, the average value of v_T is equal to zero. From (11) and (25), we can obtain

$$\overline{v_T}={\displaystyle \frac{L_m\left(V_B-V_o\right)}{L_l+2L_m}}\cdot t_f+{\displaystyle \frac{2L_m{V}_B}{L_l+2L_m}}\cdot t_r=0,$$

(33)

where t_r represents the rising time of i_Lm. Ignoring the short charging and discharging time of C_S1 (C_S2), we can obtain

$$t_f+t_r\approx 0.5T_s,$$

(34)

Combining (33) and (34), it can be deduced that t_f and t_r are, respectively, expressed as

$$t_f={\displaystyle \frac{V_B}{V_B+V_o}}{T}_s,$$

(35)

$$t_r=\left(0.5-{\displaystyle \frac{V_B}{V_B+V_o}}\right)T_s,$$

(36)

Because both t_r and t_f must be positive values, it can be seen from (36) that the design constraint for realizing the converter proposed in this study is that

$$V_o>V_B,$$

(37)

Substituting (35) into (32) yields

$$I_{Lm}={\displaystyle \frac{V_B\left(L_m{V}_B+\left(L_m+L_l\right)V_o\right)}{L_l\left(L_l+2L_m\right)\left(V_B+V_o\right)}}{T}_s,$$

(38)

From the analysis of the operation modes, it can be seen that the output power comes from two paths. One is that L_p1 (L_p2) directly provides energy to the output terminal through D₃ (D₄). The other is that L_p1 (L_p2) first charges C_B1 (C_B2) through D₃ (D₄), and then C_B1 (C_B2) provides energy to the output terminal. The power supplied to the output terminal by each of these two paths is equal to

$$P_1={\displaystyle \frac{P_o{V}_o}{\left(V_B+V_o\right)}},$$

(39)

$$P_2={\displaystyle \frac{P_o{V}_B}{\left(V_B+V_o\right)}},$$

(40)

For a buck–boost converter, when the active switch is turned off, the inductor current flows through the flywheel diode and releases energy to the output. Combining (35) and (38) yields that the average of the descending portions of i_L1 and i_L2 added together is equal to

$$\overline{i_{Ll1, fall}}+\overline{i_{Ll2, fall}}=2\times {\displaystyle \frac{t_f{I}_{Lm}}{2T_s}}={\displaystyle \frac{V_B^2\left(L_m{V}_B+\left(L_m+L_l\right)V_o\right)}{L_l\left(L_l+2L_m\right){\left(V_B+V_o\right)}^2{f}_s}},$$

(41)

Equation (41) represents the average current delivered to the output by the buck–boost converters. Combining (40) and (41) yields

$${\displaystyle \frac{V_B\left(L_m{V}_B+\left(L_m+L_l\right)V_o\right)}{L_l\left(L_l+2L_m\right)\left(V_B+V_o\right)f_s}}={\displaystyle \frac{P_o}{V_o}},$$

(42)

The coupling coefficient of the coupled inductor is defined as

$$k_c\triangleq {\displaystyle \raisebox{1ex}{$L_m$}\!\left/ \!\raisebox{-1ex}{$L_l+L_m$}\right.},$$

(43)

Combining (42) and (43) yields

$$L_l={\displaystyle \frac{V_B{V}_o\left(k_c{V}_B+V_o\right)}{\left(1+k_c\right)\left(V_B+V_o\right)P_o{f}_s}},$$

(44)

4. Parameters Design and Experimental Results

A 180 W prototype LED driver was built and tested to demonstrate the feasibility of the proposed circuit. The specification of the proposed LED driver is listed in

Table 1. Specification of the proposed LED driver.

Item	Value
Input voltage, Vin	110 ± 10% Vrms, 60 Hz
Output voltage, VLED	216 V (60 × 3.6 V)
Output current, VLED	0.84 A (3 × 0.28 A)
Output power, Po	180 W
Switching frequency, fs (at rated power)	50 kHz

. The input supply voltage presented in the article is 110 V_rms ± 10%, not universal voltage (85–264 V_rms). Equation (45) shows the design constraint for the dc-link voltage and the output voltage. The higher the input voltage, the higher the dc-link voltage and the output voltage should be. Compared with other loads, the voltage of each LED is very small. High output voltage means a considerable number of LEDs per string. When there are too many LEDs per string, the design range of the output-rated power will be limited. The load consists of three LED strings connected in parallel, each string consisting of sixty 1 W LEDs. The rated voltage and current of each LED are 3.6 V and 0.28 A, respectively.

4.1. Parameters Design

The considerations and calculations of component parameters are as follows.

A.

Choose duty ratio and dc-link voltage.

As shown in Figure 2, the gate–source voltages of S₁ and S₂ should briefly overlap when they are at high levels, that is, the duty cycle is slightly higher than 0.5. However, a high-duty cycle requires a higher dc-link voltage for the PFC converter to operate in DCM. Here, the duty ratio is chosen to be 0.54.

$$D=0.54$$

The design constraint for dc-link voltage can be obtained by combining (27) and (37), as follows.

$$V_o>V_B>{\displaystyle \frac{V_m}{1-D}}-V_o,$$

(45)

Considering the 10% variation in the input voltage, the applicable range of the dc-link voltage is calculated as

$$216>V_B>{\displaystyle \frac{110\sqrt{2}\times 1.1}{1-0.54}}-216=156 \mathrm{V}$$

Here, the dc-link voltage is chosen to be

$$V_B=160 \mathrm{V}$$

B.

Calculate PFC inductance.

First, calculate the value of k and the value of y using (28) and (30) in sequence.

$$k={\displaystyle \frac{160+216}{110\times \sqrt{2}}}=2.42$$

$$y={\displaystyle \frac{{\left(2.42\right)}^3}{\sqrt{{\left(2.42\right)}^2-1}}}\left(1+{\displaystyle \frac{2}{\pi }}{\mathit{sin}}^{-1}{\displaystyle \frac{1}{2.42}}\right)-{\left(2.42\right)}^2-{\displaystyle \frac{2}{\pi }}\times 2.42=0.78$$

Assuming a circuit efficiency of 95%, the PFC inductance can be calculated by using (29).

$$L_p={\displaystyle \frac{0.95\times {\left(0.54\right)}^2\times {\left(110\times \sqrt{2}\right)}^2}{180\times 50\times {10}^3}}\times 0.78=0.58 \mathrm{mH}$$

C.

Determine the leakage inductance and the mutual inductance of T₁.

Selecting a coupling coefficient of 0.9, the leakage inductance can be calculated by using (44).

$$L_l={\displaystyle \frac{0.95\times 160\times 216\times \left(0.9\times 160+216\right)}{\left(1+0.9\right)\times \left(160+216\right)\times 180\times 50\times {10}^3}}=1.84\hspace{0.17em}\mathrm{mH}$$

Then, the mutual inductance is calculated to be

$$L_m=16.54\hspace{0.17em}\mathrm{mH}$$

4.2. Experimental Results

Table 2. Component parameter.

Item	Value
Low-pass filter Lf, Cf	Lf = 0.5 mH, Cf = 2 µF
Diodes Dr1–Dr4	MUR460
Diodes D1–D2	C3D10060A
PFC inductance Lp1, Lp2	0.58 mH
DC-link capacitance CB1, CB2	100 µF
Mutual inductance Lm	16.54 mH
Leakage inductance Ll1, Ll2	1.84 mH
Output capacitance Co	100 µF
Active switches S1, S2	IPW65R080CFD

shows the component parameters of the prototype LED driver. In practice, it is not easy to produce a coupled inductor whose mutual inductance and leakage inductance meet the design values at the same time. Therefore, in this prototype circuit, first, a coupled inductor with a mutual inductance equal to 16.54 mH was implemented, and then two small inductors were, respectively, connected in series with the two windings of this coupled inductor. In addition, the sum of the leakage inductance of the coupled inductor and the inductance of each small inductor is equal to 1.84 mH.

Figure 5 shows the control voltages of the two active switches. As shown in the figure, the duty cycles of v_GS1 and v_GS2 both exceed 0.5, so both S₁ and S₂ are in a conductive state for a certain period of time. Figure 6a shows the inductor current waveforms of two PFC converters for several input voltage cycles. It can be seen that the envelope of the inductor current follows the input voltage to be a sinusoidal waveform. The peak value of the inductor current is high at high input voltage, and vice versa. Therefore, the time required for the inductor current to decrease from a peak value to zero is not the same. When the input voltage is at a high point, it requires more time for the inductor current to decrease from a peak value to zero. It can be concluded that if PFC converters can operate in DCM when the input voltage is at its peak point, then they can operate in DCM throughout the input voltage cycle. Figure 6b shows the expanded waveforms when the input voltage is near the peak value. As shown, the inductor current does decrease to zero. Figure 7a shows the waveforms of input voltage and input current. It can be seen that the input current follows the input voltage and is in phase with the input voltage. A power analyzer was used to measure the power quality of the input line. At rated power operation, the values of the active power, reactive power, and apparent power were 196.7 W, 34.5 Var, and 199.7 VA, respectively. The measured power factor and THDi are 0.985 and 5.27%, respectively. The specifications of the proposed LED were measured. Figure 7b shows the harmonic spectrum of the input current. The current harmonics are compared with the IEC 61000-3-2 Class C standard [6]. It can be seen that all measured current harmonics are below the standard. It verifies that operating a boost converter in DCM can indeed achieve a high power factor and low THDi. Figure 8 shows the current waveforms in the two windings of the coupled inductor. As mentioned in the section on analysis of operation mode, Mode 3 is the time to discharge the parasitic capacitance from high voltage to zero volts, and Mode 4 is the time for the inductor current to rise from zero to greater than the absolute value of the inductor current. Generally, the parasitic capacitance is very small. The typical output parasitic capacitance of the active switch (IPW65R080CFD, Infineon Technologies, Neubiberg, Germany) is 215 pF. Therefore, the time required for Mode 3 and Mode 4 is very short. The mutual inductance current is converted between the primary and secondary windings. When the current in one winding decreases, the current in the other winding increases. Additionally, the winding current will drop to a negative value. Although this negative current is very small, it is enough to release the parasitic capacitance of the MOSFET and allow the active switch to meet ZVS. Figure 9 shows the voltage and current waveforms of the two active switches. It can be seen from these experimental waveforms that before v_GS1 (v_GS2) changes from low to high level, there is a negative current that discharges the parasitic capacitance of the active switch to zero volts. This allows the active switches to be turned on at zero voltage and zero current. Figure 10 shows the LED voltage and current waveforms. The measured LED power is 181 W, which is quite close to the design target values. The circuit efficiency is 92%. In addition, it can be seen that the LED voltage exhibits low-frequency ripples (120 Hz), and the ripple factor is calculated to be approximately equal to 7%. This ripple voltage can be reduced by using larger output capacitance or larger dc-link capacitance. Figure 11 shows the photo of the proposed LED driver test stand.

5. Conclusions

This paper proposes a new LED driver with a high power factor and low total current harmonic distortion. The circuit architecture consists of two modified SEPICs that share a coupled inductor with two windings. The two SEPICs are interleaved operated, and their active switches have a duty cycle greater than 0.5. In this paper, mathematical equations are derived, and component parameters are designed so that all inductor currents would decrease to zero, allowing all diodes to operate at ZCS. In addition, the winding current of the coupled inductor can completely release the charge of the parasitic capacitance of the active switch, so that the active switch operates at ZVS, which significantly reduces the switching loss. A prototype circuit with a rated power of 180 W is implemented and measured experimentally. The experimental results show that the power factor and THDi are equal to 0.985 and 5.27%, respectively, at rated power operation. The measured efficiency of the circuit is 92%. The experimental results have verified the feasibility of the proposed circuit.